KR102190441B1 - Liquid crystal display device including power supply unit - Google Patents

Abstract

The present invention discloses a liquid crystal display device. In more detail, the present invention facilitates the panel discharge operation due to the phenomenon that the level of the gate driving voltage is lowered when power is turned off in a liquid crystal display device having a PM-IC (Power Management-IC). The present invention relates to a liquid crystal display device including a power supply unit in which a problem that cannot be performed is improved.
According to an embodiment of the present invention, a voltage drop delay circuit is provided at the input terminal of a boost controller that generates a gate high voltage inside a PM-IC configured in the form of an IC chip. There is an effect of reducing the deviation of discharge driving by region of the liquid crystal panel by delaying the deterioration.

Description

Liquid crystal display device including a power supply unit {LIQUID CRYSTAL DISPLAY DEVICE INCLUDING POWER SUPPLY UNIT}

The present invention relates to a liquid crystal display device, and in particular, in a liquid crystal display device having a PM-IC (Power Management-IC), a panel discharge operation due to a phenomenon in which the level of the gate driving voltage is lowered when power is turned off. The present invention relates to a liquid crystal display device including a power supply unit in which the problem of not being performed smoothly is improved.

Recently, with the development of various portable devices such as mobile phones and notebook computers, and information electronic devices that implement high-resolution and high-quality images such as HDTVs, flat panel displays used therein Device) is gradually increasing. As such flat panel display devices, LCD (Liquid Crystal Display), PDP (Plasma Display Panel), FED (Field Emission Display), and OLED (Organic Light Emitting Diodes) have been actively studied, but mass production technology, ease of driving means, and high quality Currently, liquid crystal displays (LCDs) are in the spotlight for reasons of realization and realization of a large-area screen.

In particular, an active matrix liquid crystal display device in which a thin film transistor (TFT) is used as a switching element is suitable for displaying a dynamic image.

1 is a schematic view showing the structure of a conventional active matrix liquid crystal display device.

Referring to FIG. 1, a conventional liquid crystal display device includes a liquid crystal panel 10 divided into a display area A/A in which a plurality of pixels are formed in a matrix form and a non-display area N/A surrounding it, and a pixel. It consists of driving circuits for driving them.

Such a liquid crystal display device converts a digital video signal applied from the outside into an analog data signal, drives each pixel sequentially by one horizontal line by a gate driving signal, and charges the data signal to the pixels, thereby generating an image. It is a structure to implement.

In general, a liquid crystal display device employs an Under Voltage Lock Out (UVLO) method to minimize malfunction due to sudden fluctuations in a supplied system input voltage. Accordingly, when the system input voltage exceeds the set minimum and maximum voltage ranges, voltage output from the power supply unit (not shown) is started or stopped.

Meanwhile, when the liquid crystal display device is switched from a power-on state to a power-off state, a predetermined residual voltage exists in the liquid crystal panel 10 due to resistance and capacitance components. As a result, an image quality deterioration phenomenon in which a faint image is displayed occurs. Accordingly, when the level of the system input voltage is lowered to the minimum voltage set to the minimum voltage UVLO_OFF, which is the minimum voltage during power-off, the gate driver 20 outputs the gate high voltage through all gate wirings to conduct the pixels, thereby causing the liquid crystal panel ( 10) Discharging the residual voltage inside.

However, as the liquid crystal panel 10 becomes larger and larger, the line delay of the gate wiring increases, and a signal deviation occurs between the upper area (Area1) and the lower area (Area2) of the screen. A problem occurs in that discharge driving is not smoothly performed in the lower area (Area2) compared to Area1).

2 is a diagram showing waveforms of some signals when power of a conventional liquid crystal display device is turned off. In the drawing, the gate high voltage input to the gate driver and the discharge voltage, which is the gate high voltage output from the gate driver and output to the gate wiring for each upper region (Area 1 in FIG. 1) and a lower region (Area 2 in FIG. 1) of the liquid crystal panel, are shown. They are represented by Vgh and Vdis, respectively.

Referring to FIG. 2, when the level of the system input voltage Vin starts to decrease and falls to a preset UVLO_OFF voltage, the output of the driving voltage of the power driver is stopped, and discharge driving is also performed. Discharge driving is to discharge the residual voltage remaining in the liquid crystal cell by conducting the thin film transistors of all pixels of the liquid crystal panel by outputting the gate high voltage (Vgh) sequentially or simultaneously with the output of the gate driver. The gate discharge voltage Vdis has a different waveform for each region according to the signal delay.

This is because the level of the gate high voltage Vgh that determines the level of the discharge voltage Vdis decreases as the driving of the power driver stops, and the discharge voltage Vdis of the lower region Area2 is lower than the upper region Area1. It is output as a lower voltage waveform.

That is, the voltage level of the lower region (Area2) of the liquid crystal panel is lowered compared to the upper region (Area1) of the liquid crystal panel due to the signal delay of the gate high voltage (Vgh), which is the voltage level of the lower region (Area2) output from the gate driver. It is admitted to the viewer in the form of Flicker.

The present invention has been conceived to solve the above-described problem, and an object of the present invention is to improve a problem in which a discharge deviation occurs for each region of a liquid crystal panel due to signal delay during discharge driving.

In order to achieve the above object, a liquid crystal display device including a power supply unit according to an exemplary embodiment of the present invention includes: a liquid crystal panel in which a plurality of gate wirings and data wirings are intersected; A gate driver and a data driver respectively connected to the gate wiring and the data wiring; And a power supply unit supplying a gate high voltage and a gate low voltage to the gate driver and maintaining a voltage level of the gate high voltage for a predetermined period when power is turned off.

A liquid crystal display device including a power supply unit according to an exemplary embodiment of the present invention includes a voltage drop delay circuit at an input terminal of a boost controller that generates a gate high voltage inside a PM-IC configured in the form of an IC chip. When the power is turned off, the timing at which the level of the gate high voltage is lowered is delayed, thereby reducing variations in discharge driving for each region of the liquid crystal panel.

1 is a schematic view showing the structure of a conventional active matrix liquid crystal display device.
2 is a diagram showing waveforms of some signals when power of a conventional liquid crystal display device is turned off.
3 is a diagram illustrating a liquid crystal display device including a power supply unit according to an exemplary embodiment of the present invention.
4 is a diagram illustrating a structure of a power supply unit included in a liquid crystal display according to an exemplary embodiment of the present invention.
5 is a diagram illustrating waveforms of some signals when a liquid crystal display device according to an exemplary embodiment of the present invention is powered off.

In this specification, terms including ordinal numbers such as first and second are used to refer to various elements, and the corresponding elements are not limited by these terms. The terms described in the following description are used for the purpose of distinguishing one component from another component.

In particular, when a component is described as being'connected' or'connected' to another component, it may be directly connected or connected to the other component, but other components may exist in the middle. On the other hand, when a component is described as being'directly connected' or'directly connected' to another component, there is no other component in the middle.

The terms used in the present application are only used to describe specific embodiments and are not intended to limit the present invention, and expressions in the singular include plural expressions unless the context clearly indicates otherwise.

Hereinafter, a liquid crystal display device including a power supply unit according to a preferred embodiment of the present invention will be described with reference to the drawings.

3 is a diagram illustrating a liquid crystal display device including a power supply unit according to an exemplary embodiment of the present invention.

Referring to FIG. 3, the liquid crystal display device of the present invention includes a liquid crystal panel 100 in which a plurality of gate lines GL and data lines DL are cross-formed, the gate lines GL, and the data lines DL. The gate driver 120 and the data driver 130 respectively connected, the timing controller 140 for controlling the gate driver 120 and the data driver 130, and the gate high voltage Vgh and the gate low voltage Vgl are It supplies to the gate driver 120, and includes a power supply unit 160 for maintaining the voltage level of the gate high voltage (Vgh) for a certain period when the power is off.

In the liquid crystal panel 100, a plurality of gate lines GL and a plurality of data lines DL are intersected in a matrix form on a glass substrate, and a plurality of pixels PX are defined at the intersection points.

On the display area of the liquid crystal panel 100, a plurality of pixels PX corresponding to the three primary colors R, G, and B are formed in a matrix form, and at least one thin film transistor serving as a switching element in each pixel PX ( A liquid crystal capacitor (LC) comprising T) and upper and lower electrodes having a liquid crystal layer interposed therebetween is provided to display an image.

In the above-described thin film transistor T, the gate electrode is connected to the gate line GL, and the source electrode is connected to the data line DL. Further, the drain electrode is connected to the pixel electrode opposite to the common electrode. As the material forming the active layer of the thin film transistor (T), amorphous silicon (a-si silicon) and poly silicon (Poly silicon) may be used, but the device performance is also high performance according to the trend of large-sized and high-definition liquid crystal display devices. As this is required, oxide silicon having improved mobility characteristics may be used.

The gate driver 120 is a shift register formed of a plurality of thin film transistors formed in a non-display area excluding a pixel area of the liquid crystal panel 100 or a separate driving IC. The gate driver 120 includes a plurality of stages, and one gate line GL is allocated to one stage. In addition, in a large-area and high-resolution liquid crystal display device, a plurality of gate driver 120 may be provided on both sides of the liquid crystal panel 100 as shown.

In particular, during normal driving, the gate driver 120 is in response to the gate control signal GCS input from the timing controller 140 through the gate wiring GL formed in the liquid crystal panel 100, 1 to 2 horizontal periods (1). The gate high voltage (Vgh) is sequentially output every ~2H). In addition, the gate low voltage Vgl is output to the gate line GL to which the current gate high voltage Vgh is not output. Among the stages of the gate driver 120, the remaining stages other than the stage currently outputting the gate high voltage Vgh output the gate low voltage Vgl through the gate line GL.

To this end, the gate driver 120 receives the gate high voltage Vgh and the gate low voltage Vgl from the power supply 160.

Accordingly, the thin film transistor T to which the gate high voltage Vgh is applied through the gate line GL is turned on, and at the same time, an analog signal is applied from the data driver 130 through the data line DL. An image is realized as the waveform data signal Vdata is output and applied to the liquid crystal capacitors LC connected to the thin film transistor T.

The data driver 130 converts the aligned digital image signal aRGB into an analog data signal Vdata according to the reference voltage in response to the data control signal DCS input from the timing controller 140. . In addition, the data driver 130 latches the converted data signal Vdata in units of one horizontal line and outputs it to the liquid crystal panel 100 at the same time through all the data lines DL every 1 to 2 horizontal periods (1 to 2H). do.

The timing controller 140 receives a timing signal from an external system and generates control signals GCS and DCS of the gate driver 120 and the data driver 130 in response thereto. In addition, the transmitted digital image signal RGB is converted into a format that can be processed by the data driver 130 and supplied to the data driver 130.

The power supply unit 160 receives the system input voltage Vin, the power supply voltage Vdd, the ground voltage Vss, and the reference voltage for driving the liquid crystal panel 100, the gate and data driving units 120 and 130. Vref), etc. are created and supplied. In particular, such a power supply unit 160 may be configured as a PM-IC (Power Management-IC) for stable driving voltage management of the liquid crystal display, and the PM-IC is a boost controller that boosts the input voltage. controller), a buck controller to step down the voltage, and a charge pump circuit.

In particular, in the embodiment of the present invention, the Vgh output block 150 including the boost controller in the power supply unit 160 is output to the gate driver 120 for a certain period even when the level of the system input voltage Vin is lowered. It is characterized in that the high voltage (Vgh) is maintained for a certain period.

When the system input voltage Vin is greater than or equal to UVLO_ON voltage when the liquid crystal display device is powered on, the gate high voltage output block 150 boosts it to the gate high voltage Vgh level and outputs it. In addition, even if the system input voltage Vin is lowered below the UVLO_OFF voltage when the liquid crystal display is powered off and the power supply 160 stops outputting the driving voltages, the gate high voltage Vgh is set to the original level for a certain period of time. Will remain as. Accordingly, since the discharge voltages output through all the gate lines GL of the liquid crystal panel 100 are almost the same in the upper region and the lower region, a discharge deviation between regions of the liquid crystal panel 100 is minimized.

Hereinafter, a power supply unit according to an embodiment of the present invention will be described with reference to the drawings.

4 is a diagram illustrating a structure of a power supply unit included in a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to Figure 4, the power supply unit 160 of the present invention, the buck controllers (161, 162) outputting a gate low voltage (Vgl) and other step-down voltage, a gate high voltage (Vgh), and other boosted voltages. The voltage reduction delay circuit 150 which is connected to the output boost controllers 166 and 167 and the input terminal of the boost controller 161 to maintain the voltage level of the system input voltage Vin for a certain period of time and input to the boost controller 161 ). The drawing shows an example in which two buck controllers 161 and 162 and two boost controllers 166 and 167 are provided, respectively, and the number of controllers may be more or less.

In addition, the power supply unit 160 of the present invention may be further connected to a charge pump circuit 170 that generates the gate high voltage Vgh by receiving feedback of the divided voltage divided by two resistance elements.

In detail, the power supply unit 160 may be composed of one or more buck controllers 161 and 162 and boost controllers 166 and 167, and each controller has a voltage converter function that increases or decreases the input voltage. Perform. The buck controllers 161 and 162 are step-down converters that convert a high input voltage to a low output voltage, and the boost controllers 161 and 162 are step-down converters that convert a low input voltage to a high output voltage. -up) is a converter.

As an example, the liquid crystal display of the present invention may be driven by a system input voltage Vin of 3.3V, and the buck controllers 161 and 162 set the system input voltage Vin to a gate low voltage (VGL) of -5V, respectively. ), and a voltage of 3.3V or less (Vout1) for driving other liquid crystal display devices.

In addition, the boost controllers 166 and 167 receive a system input voltage Vin of 3.3V and convert it into a gate high voltage VGH of 25V and a voltage of 3.3V or higher (Vout2) for driving other liquid crystal displays. can do.

In addition, as a switching method of each of the controllers 161, 162, 166, and 167, a pulse width modulation (PWM) method or a pulse frequency modulation (PFM) method may be applied.

In particular, the boost controller 166 for outputting the gate high voltage Vgl of the present invention is connected to the voltage delay circuit 165 rather than directly applying the system input voltage Vin to the input terminal, and the boost controller 166 ) And the voltage delay circuit 165 form one VGH output block 150.

The voltage delay circuit 165 maintains the level of the voltage applied to the boost controller 166 for a certain period even if the voltage level of the system input voltage Vin decreases below UVLO_OFF according to the power-off of the liquid crystal display device. Plays a role.

That is, when the power is turned off, the voltage level of the system input voltage Vin is gradually lowered, and as the UVLO method is applied, the voltage input to all the controllers 161, 162, 166, 167 is the previous input voltage level. Will be maintained. Thereafter, when the system input voltage Vin falls below UVLO_OFF, the voltage input to the controllers 162, 166, and 167 other than the boost controller 166 of the Vgh output block 150 transitions to OV or ground voltage level. Is done.

That is, the voltage delay circuit 165 maintains the voltage level supplied to the connected boost controller 166 at a level before the voltage drop occurs for a certain period even if the system input voltage Vin is lowered to UVLO_OFF or less. To this end, the voltage delay circuit 165 may include a predetermined capacitor (not shown), and the capacitance of the capacitor may be proportional to the voltage level supplied to the boost controller 166 for the predetermined period.

The predetermined period may be determined from 2 ms or more and 6 ms or less from the UVLO off time.

Therefore, the boost controller 166 outputs the gate high voltage (Vgh) in response to the same PWM signal as when the power is turned on during the period in which the input voltage is maintained, so that the decrease in the voltage level of the gate high voltage (Vgh) is delayed for a predetermined period. do. Accordingly, it is possible to maintain the original voltage level for a time in which the discharge voltage Vdis output from the gate driver (120 in FIG. 3) discharges the residual voltage in all regions of the liquid crystal panel.

Meanwhile, each of the controllers 161, 162, 166, and 167 may further include a charge pump circuit 170 at the output terminal according to the intention of the setter. Referring to FIG. 4, the boost controller 166 may be connected to a charge pump circuit 170 that outputs a switching signal SW, which is a PWM waveform, and receives a divided voltage as feedback.

The charge pump circuit 170 includes a first node N1 connected to the output terminal of the boost controller 166, an inductor I1 connected between the power voltage Vdd terminal and the first node N1, and a first A diode D1 connected to the node N1 and the first electrode, a second node N2 connected to the output terminal of the diode D1 and the gate high voltage Vgh, and two resistors connected in series. 2 A voltage divider resistor (R1, R2) connected between the node (N1) and a ground voltage (VSS) terminal, and a second node (N1) and a ground voltage (VSS) terminal connected in parallel with the voltage divider resistors (R1, R2). It includes an output capacitor Cout connected therebetween.

In particular, one of the input terminals of the boost controller 166 is connected between the two voltage divider resistors R1 and R2, and according to this structure, the boost controller 166 is an inductor by turning on and off the switching signal SW of the PWM. The voltage is charged and discharged to (I1), and the gate high voltage (Vgh) is output through the diode (D1). In addition, the boost controller 166 receives the voltage-dropped feedback voltage FB by the two voltage divider resistors R1 and R2 and reflects it to the PWM.

Although not shown, according to the intention of the setter, the other controllers 161, 162, and 167 may be connected to the same or similar charge pump circuit.

Hereinafter, a signal waveform of a power supply unit according to an embodiment of the present invention will be described with reference to the drawings.

5 is a diagram showing waveforms of some signals when the liquid crystal display device according to an exemplary embodiment of the present invention is powered off, and as shown, the voltage level of the system input voltage Vin starts to decrease and a preset UVLO_OFF voltage When it is lowered to, discharge driving is performed as the output of the driving voltage of the power driver is stopped.

When the voltage level of the conventional input voltage Vin reaches the UVLO_OFF voltage, as the driving voltage output of the power driver stops, the voltage level of the gate high voltage Vgh is also immediately lowered, but according to an embodiment of the present invention, the voltage decreases. Even if the voltage level of the input voltage Vin is less than the UVLO_OFF voltage by the delay circuit, the voltage applied to the boost controller is maintained at the same level, so that the gate high voltage (Vgh) is the original voltage for a certain period (dt) for the sustain period. The level is maintained.

Accordingly, as the discharge voltage Vdis is maintained for a period of time during which the residual voltage can be discharged for all regions of the liquid crystal panel, a discharge deviation for each region is minimized and a flicker phenomenon is improved.

Although the above has been described with reference to the preferred embodiments of the present invention, those skilled in the art will variously modify and change the present invention within the scope not departing from the spirit and scope of the present invention described in the following claims. You will understand that you can do it.

100: liquid crystal panel 120: gate driver
130: data driving unit 140: timing control unit
150: VGH output block 160: power supply
PX: Pixel T: Thin film transistor
LC: liquid crystal capacitor RGB: video signal
aRGB: Aligned video signal GCS: Gate control signal
DCS: Data control signal GL: Gate wiring
DL: Data wiring Vdata: Data signal
Vgh: Gate high voltage Vgl: Gate low voltage
Vin: System input voltage Vdd: Power supply voltage
Vss: ground voltage Vref: reference voltage

Claims (5)

A liquid crystal panel in which a plurality of gate wirings and data wirings are cross formed;
A gate driver and a data driver respectively connected to the gate wiring and the data wiring; And
And a power supply unit supplying a gate high voltage and a gate low voltage to the gate driver, and maintaining a voltage level of the gate high voltage for a predetermined period when power is turned off,
The power supply unit
A voltage drop delay circuit that delays and outputs a voltage level drop of the system input voltage for a certain period of time; And
And at least one boost controller generating the gate high voltage during a period in which the system input voltage is delayed through the voltage drop delay circuit. The method of claim 1,
The gate driver consists of a plurality of stages,
When power is turned off, all stages sequentially or simultaneously output the gate high voltage. The method of claim 1,
The power supply unit,
And at least one buck controller generating the gate low voltage. The method according to any one of claims 1 and 3,
For the above period,
2 ms or more and 6 ms or less from the time of UVLO off. The method of claim 3,
The boost controller,
And a charge pump circuit that receives the output voltage and generates the gate high voltage.

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