CN213025340U - Ghost eliminating circuit of display panel and display device - Google Patents
Ghost eliminating circuit of display panel and display device Download PDFInfo
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- CN213025340U CN213025340U CN202021960903.1U CN202021960903U CN213025340U CN 213025340 U CN213025340 U CN 213025340U CN 202021960903 U CN202021960903 U CN 202021960903U CN 213025340 U CN213025340 U CN 213025340U
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Abstract
The utility model discloses a display panel's ghost elimination circuit and display device, this circuit includes: a power supply unit for providing a supply voltage; the threshold voltage generating unit is connected with the power supply unit and used for generating threshold voltage according to the power supply voltage; the control unit is respectively connected with the power supply unit and the threshold voltage generation unit and used for generating a control signal according to the power supply voltage and the threshold voltage; and the discharging unit is connected with the control unit, receives the control signal and the common voltage signal, and is used for discharging the common voltage signal in the power-down state of the power supply unit according to the control signal. The utility model discloses can realize that public voltage signal follows supply voltage and falls the electricity and discharge rapidly, the effectual incomplete shadow of shutdown of having eliminated display panel.
Description
Technical Field
The utility model relates to a show technical field, concretely relates to display panel's ghost elimination circuit and display device.
Background
In recent years, Liquid Crystal Display (LCD) devices have been widely used in many fields, and continue to show a rapid growth trend. With the improvement of driving technology, it has the advantages of low power consumption, thin and light weight, low voltage driving, etc., and has been widely applied to camcorders, notebook computers, desktop display devices and various projection apparatuses.
A liquid crystal display device in which a switching transistor is formed in each pixel distributed in a matrix form in a liquid crystal panel is now widely used. A liquid crystal display device generally includes a gate driver circuit, a source driver circuit, and a pixel array. The pixel array is provided with a plurality of pixel circuits, and each pixel circuit is turned on and off according to a scanning signal provided by the grid driving circuit and displays a data picture according to a data signal provided by the source driving circuit.
Taking TFT-lcd as an example, the main reason for the shutdown afterimage is that the discharge speed of the common electrode of TFT-lcd is too slow, so that the charges cannot be released quickly after shutdown and remain in the liquid crystal capacitor, and the discharge must be completed after a period of time. During this discharge process, the user may see the power-off afterimage on the lcd panel.
At present, a control signal is generated when the liquid crystal display device is turned off, the thin film transistor can be turned on completely by increasing the voltage of the gate terminal of the thin film transistor, and the residual charges in the liquid crystal capacitor can be discharged quickly by the thin film transistor in a conducting state and the data line electrically connected with the thin film transistor, so that the time for completely discharging the residual charges is shortened, and the phenomenon of shutdown afterimage is eliminated to a certain extent. However, since the discharge speed of the common electrode is not considered, the discharge is slow.
Therefore, there is a need to provide an improved technical solution to overcome the above technical problems in the prior art.
SUMMERY OF THE UTILITY MODEL
In order to solve the technical problem, the utility model provides a display panel's incomplete shadow cancelling circuit and display device can realize that public voltage signal follows supply voltage and falls the electricity and discharge rapidly, the effectual incomplete shadow of shutting down of having eliminated display panel.
According to the utility model provides a pair of display panel's ghost elimination circuit, include: a power supply unit for providing a supply voltage; the threshold voltage generating unit is connected with the power supply unit and used for generating a threshold voltage according to the power supply voltage; the control unit is respectively connected with the power supply unit and the threshold voltage generation unit and is used for generating a control signal according to the power supply voltage and the threshold voltage; and the discharging unit is connected with the control unit, receives the control signal and the common voltage signal, and is used for discharging the common voltage signal in the power-down state of the power supply unit according to the control signal.
Preferably, the threshold voltage generating unit includes: a first resistor, a first end of which receives the supply voltage and a second end of which is connected with a first node; a first end of the second resistor is connected with the first node, and a second end of the second resistor is connected with a grounding end; a first diode, the anode of which is connected with the first node and the cathode of which is connected with the second node; and a first capacitor having a positive terminal connected to the second node and a negative terminal connected to a ground terminal, wherein the threshold voltage generation unit generates the threshold voltage at the second node.
Preferably, the first resistance is a variable resistor.
Preferably, the control unit includes: and the control end of the first switch tube receives the power supply voltage through a third resistor, the first path end is connected with the second node, and the second path end generates the control signal through a fourth resistor.
Preferably, the first switch tube is a PNP type triode, the first pass end of the first switch tube is an emitter of the PNP type triode, and the second pass end of the first switch tube is a collector of the PNP type triode.
Preferably, the first switch tube is a PMOS transistor, the first path end of the first switch tube is a source electrode of the PMOS transistor, and the second path end of the first switch tube is a drain electrode of the PMOS transistor.
Preferably, the discharge unit includes: and the control end of the second switch tube receives the control signal, the first path end receives the public voltage signal through a fifth resistor, and the second path end is connected with the grounding end.
Preferably, the second switch tube is an NPN-type triode, the first path end of the second switch tube is a collector of the NPN-type triode, and the second path end of the second switch tube is an emitter of the NPN-type triode.
Preferably, the second switch tube is an NMOS transistor, the first pass end of the second switch tube is a drain of the NMOS transistor, and the second pass end of the second switch tube is a source of the NMOS transistor.
According to the utility model provides a pair of display device, include: a display panel including a plurality of data lines, a plurality of gate lines, a common electrode line, and a plurality of pixels; a source driving circuit coupled to the data lines for providing a plurality of gray scale data; a gate driving circuit coupled to the gate lines for providing a plurality of gate driving signals; and a timing control circuit connected to the source driving circuit and the gate driving circuit, respectively, for providing a plurality of switching signals to the source driving circuit and providing a start signal and a plurality of clock signals to the gate driving circuit, wherein the display device further includes: the image sticking elimination circuit of the display panel is connected with the common electrode wire and used for discharging the voltage on the common electrode wire in the power-off state of the display device.
The utility model has the advantages that: the utility model discloses a display panel's ghost elimination circuit and display device, wherein, threshold voltage is for generating based on supply voltage, power-on back threshold voltage is in the state that is less than supply voltage promptly, consequently can not discharge public voltage signal under the power-on state, can guarantee display panel normal work, and shut down at display panel and supply voltage power-off state is under, just can control when also needing supply voltage to descend to be less than threshold voltage and realize the discharge to public voltage signal, and then can effectually avoid the erroneous discharge operation when supply voltage has the voltage shake, can realize public voltage signal simultaneously and follow supply voltage and fall the electricity and discharge rapidly, the effectual shutdown ghost that has eliminated display panel.
The generation of the threshold voltage is realized based on the variable resistor, so that the digital system of the threshold voltage is adjustable, and the applicability of the circuit is improved.
The triode is adopted as a switching element in the control unit and the discharge unit, the voltage difference between the base electrode and the emitter electrode is small when the triode is saturated, the response speed is high, and the discharge action of the common electrode on the display panel can be accelerated.
The field effect transistor is used as a switching element in the control unit and the discharge unit, so that the switching characteristic is stable, and the stability of the circuit is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a display device according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a sub-pixel unit in a display device according to an embodiment of the present invention;
fig. 3 is a block diagram illustrating a structure of an image sticking elimination circuit of a display panel according to an embodiment of the present invention;
fig. 4 is a schematic circuit diagram illustrating an image sticking elimination circuit of a display panel according to a first embodiment of the present invention;
fig. 5 is a schematic circuit diagram illustrating an image sticking elimination circuit of a display panel according to a second embodiment of the present invention;
fig. 6a shows a schematic waveform diagram of a common voltage signal after power-on provided by the embodiment of the present invention;
fig. 6b shows a schematic waveform diagram of the common voltage signal after power down according to the embodiment of the present invention.
Detailed Description
In order to facilitate understanding of the present invention, the present invention will be described more fully hereinafter with reference to the accompanying drawings. The preferred embodiments of the present invention are shown in the drawings. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
The present invention will be described in detail below with reference to the accompanying drawings.
Fig. 1 shows a schematic structural diagram of a display device provided according to an embodiment of the present invention, and fig. 2 shows a schematic structural diagram of a sub-pixel unit in a display device provided according to an embodiment of the present invention.
As shown in fig. 1, in the present embodiment, the display device 100 includes a display panel 1, a timing control circuit 2, a source driving circuit 3, and a gate driving circuit 4.
The display panel 1 includes a plurality of data lines S1 to Sn, a plurality of gate lines G1 to Gm, and a plurality of pixels disposed at positions where the respective data lines and gate lines intersect.
As shown in FIG. 2, each pixel of the display panel is connected to a data line SkAnd one scanning line GkAnd each pixel includes a thin film transistor TFT and a pixel electrode. Wherein the pixel electrode comprises a liquid crystal capacitor C connected in parallelLcAnd a storage capacitor CS. One end of the pixel electrode is connected with the display electrode, and the other end is connected with the common electrodeCommon electrode VcomAnd (4) connecting. Grid and scanning line G of thin film transistor TFTkConnected to the first path terminal and the data line SkThe second via terminal is connected to the display electrode, and a parasitic capacitance is also present between the gate and drain of the thin film transistor TFT. Wherein m, n and k are natural numbers. Under the control of a grid signal, the rotation angle of the liquid crystal molecules is controlled by electric fields formed by the pixel electrode and the common electrode which are respectively applied to the liquid crystal capacitor, and the display of a single liquid crystal pixel is realized. The storage capacitor is mainly used for keeping normal display of the previous line of images within one frame time when the grid driving signal is scanned line by line.
Further, the display panel 1 includes, but is not limited to: any one of a cathode ray tube display panel, a digital light processing display panel, a liquid crystal display panel, a light emitting diode display panel, an organic light emitting diode display panel, a quantum dot display panel, a Mirco-LED display panel, a Mini-LED display panel, a field emission display panel, a plasma display panel, an electrophoretic display panel, or an electrowetting display panel.
The timing control circuit 2 is connected to the source driving circuit 3 and the gate driving circuit 4, respectively, for providing a plurality of switching signals SWn to the source driving circuit 3, and a start signal STV and a plurality of clock signals CLKm to the gate driving circuit 4.
The source driving circuit 3 is coupled to the data lines S1 to Sn for providing gray scale data.
The gate driving circuit 4 includes a plurality of gate driving units, each of which is coupled to one gate line of the display panel 1 for providing a gate driving signal to sequentially drive a plurality of gate lines G1 to Gm on the display panel 1.
Further, when the plurality of data lines S1 to Sn are driven in a state where the gate lines G1 to Gm are activated, gray-scale voltages corresponding to pixel data are written in pixels connected to the activated plurality of gate lines G1 to Gm through the plurality of data lines S1 to Sn, and thus the pixels are driven, charging the pixels.
Fig. 3 is a block diagram illustrating a structure of a ghost eliminating circuit of a display panel according to an embodiment of the present invention, and fig. 4 is a schematic circuit diagram illustrating a ghost eliminating circuit of a display panel according to a first embodiment of the present invention.
In this embodiment, the display device further includes a residual image eliminating circuit (hereinafter, referred to as "residual image eliminating circuit") of the display panel, where the residual image eliminating circuit is connected to the common electrode line on the display panel, and is configured to rapidly discharge the voltage on the common electrode line in a power-off state of the display device.
Example one
Further, in this embodiment, referring to fig. 3 and 4, the image sticking elimination circuit includes: a power supply unit 11, a threshold voltage generation unit 12, a control unit 13, and a discharge unit 14.
The power supply unit 11 is configured to provide a supply voltage.
It should be noted that the power supply unit 11 is mainly used to provide a power supply voltage for the display panel and the internal circuits thereof, wherein the power supply unit 11 includes a power-on state and a power-off state. When the display panel receives the power-on signal, the power supply unit 11 is in a power-on state, that is, the power supply voltage output by the power supply unit 11 gradually rises from 0V to a rated output value, and then the display panel normally operates under the power supply voltage of the rated output value. When the display panel receives the shutdown signal, the power supply unit 11 is in a power-down state, that is, the power supply voltage output by the power supply unit 11 gradually decreases from the rated output value to 0V. It can be understood that if the discharge speed of the common electrode of the TFT-lcd is too slow, when the display panel is turned off, the charges on the common electrode are not completely released, which may cause a certain shutdown afterimage.
The threshold voltage generation unit 12 is connected to the power supply unit 11, and generates a threshold voltage from the power supply voltage.
Further, the threshold voltage generating unit 12 includes: the circuit comprises a first resistor R1, a second resistor R2, a first diode D1 and a first capacitor C1. The first end of the first resistor R1 receives the supply voltage VCC, and the second end of the first resistor R1 is connected to the first node a. A first terminal of the second resistor R2 is connected to the first node a, and a second terminal of the second resistor R2 is connected to the ground terminal. An anode of the first diode D1 is connected to the first node a, and a cathode of the first diode D1 is connected to the second node b. The positive terminal of the first capacitor C1 is connected to the second node b, and the negative terminal of the first capacitor C1 is connected to the ground terminal. Wherein the threshold voltage generating unit generates a threshold voltage at the second node b.
Preferably, the first resistor R1 is a variable resistor. At this time, the potential of the first node a is adjustable, and further the potential of the second node b is adjustable, that is, the voltage value of the threshold voltage generated by the threshold voltage generating unit 12 can be changed by adjusting the effective resistance value of the first resistor R1 connected to the circuit, so that the circuit is suitable for different application scenarios, and the circuit is beneficial to improving the applicability.
Preferably, the first capacitor C1 is an active capacitor, and has a larger capacity for storing energy better under the same volume.
The control unit 13 is connected to the power supply unit 11 and the threshold voltage generation unit 12, respectively, and is configured to generate a control signal according to the power supply voltage VCC and the threshold voltage.
Further, the control unit 13 includes: a third resistor R3, a fourth resistor R4 and a first switch tube Q1. A first end of the third resistor R3 receives the supply voltage VCC, and a second end of the third resistor R3 is connected to the control end of the first switch transistor Q1. The first terminal of the first switch Q1 is connected to the second node b to receive the threshold voltage, the second terminal of the first switch Q1 is connected to the first terminal of the fourth resistor R4, and the control unit 13 outputs the control signal at the second terminal of the fourth resistor R4.
Further, in this embodiment, the first switch Q1 is a PNP transistor. The first pass end of the first switch tube Q1 is an emitter of a PNP type triode, and the second pass end of the first switch tube Q1 is a collector of the PNP type triode.
The discharging unit 14 is connected to the control unit 13, and receives the control signal and the common voltage signal, and is configured to discharge the common voltage signal in a power-down state of the power supply unit according to the control signal.
Further, the discharge unit includes: fifth resistor R5And a second switching tube Q2. Wherein, a first end of the fifth resistor R5 is connected to a common electrode line on the display panel to receive a common voltage signal VcomA second end of the fifth resistor R5 is connected to the first path end of the second switch Q2. The control terminal of the second switch Q2 is connected to the second terminal of the fourth resistor R4 for receiving the control signal, and the second pass terminal of the second switch Q2 is connected to the ground terminal.
Further, in this embodiment, the second switching transistor Q2 is an NPN transistor. The first pass end of the second switch Q2 is a collector of the NPN transistor, and the second pass end of the first switch Q1 is an emitter of the NPN transistor.
In the embodiment, the voltage difference between the base electrode and the emitter electrode is small when the triode is saturated, the response speed is high, and the discharge action of the common electrode on the display panel can be accelerated.
Based on the above description, it can be seen that, in the power-up state, when the voltage of the power supply voltage VCC gradually increases, the potential at the first node a also starts to increase through the voltage division effect of the first resistor R1 and the second resistor R2, and simultaneously, the potential at the second node b also starts to increase based on the voltage reduction effect of the first diode D1, and then the first capacitor C1 is charged, and when the charging is completed, the potential at the second node b, i.e., the threshold voltage, i.e., the voltage across the first capacitor C1 is the voltage across the first capacitor C1
Wherein, due to
Being smaller than 1, the potential at the second node b, i.e. the voltage across the first capacitor C1, is smaller than the supply voltage VCC. When the supply voltage VCC is stable, the potential of the control terminal, e.g., the base, of the first switch Q1 is equal to the supply voltage VCC, and the potential of the first pass terminal, e.g., the emitter, of the first switch Q1 is equal to the potential of the second node b and the threshold voltage, so that the emitter voltage of the first switch Q1(PNP type triode) is lower than the base voltage, the first switch Q1 is turned off, and at the same time, the control terminal of the second switch Q2(NPN type triode) has no current, and the current is supplied to the control terminal, e.g., the base, of the first switch Q1(PNP type triodeThe voltage is 0, so the second switch tube Q2 is also in the off state. At this time, the common voltage signal V on the common electrode line of the display panelcomCan be normally output. Further, referring to fig. 6a, fig. 6a shows a waveform schematic diagram of the common voltage signal after power-on provided by the embodiment of the present invention, as shown in fig. 6a, after the common voltage VCC is powered on and stably outputted, the common voltage signal V on the common electrode line of the display panel is showncomAnd is also in a stable output state. That is, the utility model discloses a ghost elimination circuit does not influence display panel's normal work after last electricity.
In the power-down state, when the voltage of the power supply voltage VCC starts to decrease, the potential of the control terminal, such as the base, of the first switch transistor Q1 also starts to decrease. Meanwhile, after the voltage of the supply voltage VCC decreases, due to the discharging effect of the second capacitor C1, the threshold voltage received by the first path end of the first switch tube Q1, such as the emitter, i.e., the potential at the second node b, i.e., the threshold voltage, may remain unchanged for a certain time, so that, when the potential of the control end of the first switch tube Q1, such as the base, decreases to a value (e.g., 0.3V) lower than the threshold voltage, the first switch tube Q1 starts to be turned on, and the second switch tube Q2 is turned on, so as to start to turn on the common voltage signal V on the common electrode line of the display panelcomAnd discharging is performed. Further, referring to fig. 6b, fig. 6b shows that according to the embodiment of the present invention, the waveform of the common voltage signal is shown after the power down, as shown in fig. 6b, after the common voltage VCC begins to power down, the common voltage signal V on the common electrode line of the display panel is showncomIt is also pulled down quickly to ground potential. That is, the utility model discloses an afterimage elimination circuit can realize public voltage signal V when falling the electricity and shutting downcomThe power supply voltage VCC is quickly discharged along with the power supply voltage VCC, so that shutdown afterimage of the display panel is effectively eliminated.
It can be understood that by adjusting the effective resistance of the first resistor R1 connected into the circuit, the threshold voltage generated at the second node b can be changed, and the applicability of the circuit can be enhanced.
Example two
Fig. 5 is a schematic circuit diagram of an image sticking elimination circuit of a display panel according to a second embodiment of the present invention, and fig. 5 is a schematic circuit diagram of the image sticking elimination circuit.
As shown in fig. 5, the image sticking elimination circuit disclosed in this embodiment is substantially the same as the image sticking elimination circuit disclosed in the first embodiment, and the same parts are not repeated.
The difference lies in that: in this embodiment, the first switch Q1 in the control unit 13 is a PMOS transistor. The first pass end of the first switch Q1 is a source of a PMOS transistor, and the second pass end of the first switch Q1 is a drain of the PMOS transistor. And the second switching transistor Q2 in the discharge unit 14 is an NMOS transistor. The first pass end of the second switch Q2 is a drain of the NMOS transistor, and the second pass end of the second switch Q2 is a source of the NMOS transistor. The switching characteristics of the field effect transistor are stable, which contributes to improving the stability of the circuit.
To sum up, the threshold voltage is generated based on the power supply voltage, namely the threshold voltage is in a state smaller than the power supply voltage after power-on, therefore, the public voltage signal can not be discharged in the power-on state, normal work of the display panel can be ensured, and when the display panel is shut down, namely the power supply voltage is in a power-off state, the power supply voltage is required to be reduced to be smaller than the threshold voltage, the public voltage signal can be controlled to be discharged, so that the erroneous discharge operation when the power supply voltage has voltage jitter can be effectively avoided, meanwhile, the public voltage signal can be rapidly discharged after being subjected to power-off along with the power supply voltage, and shutdown ghost of the display panel is effectively eliminated.
It should be noted that, in this document, the contained terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present invention and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious changes and modifications may be made without departing from the scope of the present invention.
Claims (10)
1. An image sticking elimination circuit of a display panel, comprising:
a power supply unit for providing a supply voltage;
the threshold voltage generating unit is connected with the power supply unit and used for generating a threshold voltage according to the power supply voltage;
the control unit is respectively connected with the power supply unit and the threshold voltage generation unit and is used for generating a control signal according to the power supply voltage and the threshold voltage;
and the discharging unit is connected with the control unit, receives the control signal and the common voltage signal, and is used for discharging the common voltage signal in the power-down state of the power supply unit according to the control signal.
2. The image sticking elimination circuit of claim 1, wherein the threshold voltage generation unit comprises:
a first resistor, a first end of which receives the supply voltage and a second end of which is connected with a first node;
a first end of the second resistor is connected with the first node, and a second end of the second resistor is connected with a grounding end;
a first diode, the anode of which is connected with the first node and the cathode of which is connected with the second node; and
a first capacitor, the positive terminal of which is connected with the second node and the negative terminal of which is connected with the grounding terminal,
wherein the threshold voltage generation unit generates the threshold voltage at the second node.
3. The image sticking elimination circuit of claim 2, wherein the first resistance is a variable resistor.
4. The image sticking elimination circuit of claim 2, wherein the control unit comprises:
and the control end of the first switch tube receives the power supply voltage through a third resistor, the first path end is connected with the second node, and the second path end generates the control signal through a fourth resistor.
5. The image sticking elimination circuit of claim 4, wherein the first switch tube is a PNP type triode, the first pass end of the first switch tube is an emitter of the PNP type triode, and the second pass end of the first switch tube is a collector of the PNP type triode.
6. The image sticking elimination circuit of claim 4, wherein the first switch tube is a PMOS transistor, the first pass end of the first switch tube is a source of the PMOS transistor, and the second pass end of the first switch tube is a drain of the PMOS transistor.
7. The image sticking elimination circuit of claim 1, wherein the discharge unit comprises:
and the control end of the second switch tube receives the control signal, the first path end receives the public voltage signal through a fifth resistor, and the second path end is connected with the grounding end.
8. The image sticking elimination circuit of claim 7, wherein the second switch tube is an NPN-type triode, the first pass end of the second switch tube is a collector of the NPN-type triode, and the second pass end of the second switch tube is an emitter of the NPN-type triode.
9. The image sticking elimination circuit of claim 7, wherein the second switch tube is an NMOS transistor, the first pass end of the second switch tube is a drain of the NMOS transistor, and the second pass end of the second switch tube is a source of the NMOS transistor.
10. A display device, comprising:
a display panel including a plurality of data lines, a plurality of gate lines, a common electrode line, and a plurality of pixels;
a source driving circuit coupled to the data lines for providing a plurality of gray scale data;
a gate driving circuit coupled to the gate lines for providing a plurality of gate driving signals; and
a timing control circuit respectively connected with the source driving circuit and the gate driving circuit for providing a plurality of switching signals to the source driving circuit and providing an enable signal and a plurality of clock signals to the gate driving circuit,
wherein the display device further comprises:
the image sticking elimination circuit of the display panel according to any one of claims 1 to 9, connected to the common electrode line, for discharging a voltage on the common electrode line in a power-off state of the display device.
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| CN202021960903.1U CN213025340U (en) | 2020-09-09 | 2020-09-09 | Ghost eliminating circuit of display panel and display device |
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| CN202021960903.1U CN213025340U (en) | 2020-09-09 | 2020-09-09 | Ghost eliminating circuit of display panel and display device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113380210A (en) * | 2021-06-22 | 2021-09-10 | 昆山龙腾光电股份有限公司 | Rapid power-down circuit and display device |
| CN113436587A (en) * | 2021-06-22 | 2021-09-24 | 昆山龙腾光电股份有限公司 | Regulating circuit |
| CN114495854A (en) * | 2021-12-28 | 2022-05-13 | 绵阳惠科光电科技有限公司 | Driving circuit, driving method and display device |
| CN114694612A (en) * | 2022-03-23 | 2022-07-01 | Tcl华星光电技术有限公司 | Shutdown discharge circuit and shutdown discharge method |
-
2020
- 2020-09-09 CN CN202021960903.1U patent/CN213025340U/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113380210A (en) * | 2021-06-22 | 2021-09-10 | 昆山龙腾光电股份有限公司 | Rapid power-down circuit and display device |
| CN113436587A (en) * | 2021-06-22 | 2021-09-24 | 昆山龙腾光电股份有限公司 | Regulating circuit |
| CN113436587B (en) * | 2021-06-22 | 2022-09-23 | 昆山龙腾光电股份有限公司 | Regulating circuit |
| CN113380210B (en) * | 2021-06-22 | 2023-03-28 | 昆山龙腾光电股份有限公司 | Rapid power-down circuit and display device |
| CN114495854A (en) * | 2021-12-28 | 2022-05-13 | 绵阳惠科光电科技有限公司 | Driving circuit, driving method and display device |
| CN114694612A (en) * | 2022-03-23 | 2022-07-01 | Tcl华星光电技术有限公司 | Shutdown discharge circuit and shutdown discharge method |
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