CN110619857B - Driving circuit and display device - Google Patents
Driving circuit and display device Download PDFInfo
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- CN110619857B CN110619857B CN201910797072.6A CN201910797072A CN110619857B CN 110619857 B CN110619857 B CN 110619857B CN 201910797072 A CN201910797072 A CN 201910797072A CN 110619857 B CN110619857 B CN 110619857B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
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Abstract
The application discloses a driving circuit and a display device, wherein the driving circuit comprises a time sequence control circuit, a first time sequence control circuit and a second time sequence control circuit, wherein the time sequence control circuit provides a first starting signal and a first clock signal; the level shift circuit adjusts the voltage value ranges of the first starting signal and the first clock signal to generate a second starting signal and a second clock signal; the gate driving circuit generates a plurality of gate driving signals according to the starting control signal and the clock control signal; a source driving circuit for providing a gray scale voltage according to display data; and the adjusting circuit is used for detecting whether the time for outputting the gray scale voltage by the source electrode driving circuit is earlier than the rising edge of the second starting signal or not, if so, taking a reference signal as the starting control signal and the clock control signal, and if not, taking the second starting signal as the starting control signal and taking the second clock signal as the clock control signal.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a driving circuit and a display device.
Background
The liquid crystal display device has the advantages of good picture quality, small volume, light weight, low driving voltage, low power consumption, no radiation, relatively low manufacturing cost and the like, and is dominant in the field of flat panel display at present. It is widely used in desk computer, palm computer, personal digital assistant, portable telephone and other office automation and audio-visual equipment.
Fig. 1 is a schematic view showing a structure of a display device in the related art.
As shown in fig. 1, the display device includes a panel 1100 and a backlight module (not shown), a timing control circuit 1200, a gate driving circuit 1300, a source driving circuit 1400, and a level shifting circuit 1500. A pixel array (not shown) including a plurality of pixel units each defined by a plurality of gate lines connected to the gate driving circuit 1300 and a plurality of data lines connected to the source driving circuit 1400 crossing each other is disposed on the array substrate of the display panel 1100. Each pixel unit is internally provided with a thin film transistor, a liquid crystal capacitor and a storage capacitor, the grid electrode of the thin film transistor is connected with the grid line, the source electrode of the thin film transistor is connected with the data line, and the drain electrode of the thin film transistor is connected with the pixel electrode. The gate driving circuit 1200 may sequentially output gate driving signals to the gate lines, and the source driving circuit 1400 may output source driving signals to the data lines, thereby charging the liquid crystal capacitors and the storage capacitors in the corresponding pixel units.
The timing control circuit 1200 is used to provide the gate driving circuit 1300 with the first start signal STV0 and the first clock signal CLK0, where the first start signal STV0 and the first clock signal CLK0 are often processed by the level shift circuit 1500 and then output to obtain the second start signal STV1 and the second clock signal CLK 1. The timing control circuit 1200 is also used to provide a third clock signal CLKs to the source driving circuit 1400. The gate driving circuit 1300 scans the pixel cells corresponding to the gate lines row by row according to the second start signal STV1 and the second clock signal CLK 1. When the pixel units are gated, the source driving circuit 1400 applies gray scale voltages corresponding to display data to the pixel electrodes in the pixel units of each column through the plurality of data lines according to the third clock signal CLKs, thereby causing the display panel 1100 to present an image.
Obviously, the source driving circuit 1400 and the gate driving circuit 1300 should operate synchronously. However, the level shift circuit 1500 often has a soft start, so that the second start signal STV1 provided to the gate driving circuit 1400 after being processed by the level shift circuit 1500 lags behind the gray scale voltage output by the source driving circuit 1400, which causes the gate driving circuit 1300 to leak a large current to be damaged, thereby reducing the service life of the display device.
Disclosure of Invention
The invention provides a driving circuit and a display device aiming at the problems in the prior art, and solves the problem that a grid driving circuit is damaged due to large current leakage.
According to an aspect of an embodiment of the present invention, there is provided a driving circuit including:
a timing control circuit providing a first start signal and a first clock signal;
the level shift circuit adjusts the voltage value ranges of the first starting signal and the first clock signal to generate a second starting signal and a second clock signal;
the gate driving circuit generates a plurality of gate driving signals according to the starting control signal and the clock control signal; and
a source driving circuit for providing a gray scale voltage according to display data;
wherein the driving circuit further comprises:
and the adjusting circuit is connected with the source electrode driving circuit to receive the gray scale voltage, is connected with the level shifting circuit to receive the second starting signal and the second clock signal, and detects whether the time of outputting the gray scale voltage by the source electrode driving circuit is prior to the rising edge of the second starting signal or not, if so, a reference signal is used as the starting control signal and the clock control signal, and if not, the second starting signal is used as the starting control signal and the second clock signal is used as the clock control signal.
Optionally, the adjustment circuit comprises:
a first comparator, wherein the positive input end of the first comparator is connected with the level shift circuit to receive the second starting signal, the negative input end of the first comparator receives a first reference voltage, and the output end of the first comparator provides a first detection signal;
a positive input end of the second comparator is connected with the source electrode driving circuit to receive the gray scale voltage, a negative input end of the second comparator receives a second reference voltage, and an output end of the second comparator provides a second detection signal;
a latch for providing the latch signal of the current state according to the first detection signal and the latch signal of the previous state; and
and the switching unit is used for respectively providing the starting control signal and the clock control signal to a control output end according to the latching signal and the second detection signal.
Optionally, the adjusting circuit further comprises:
and the on and off of the switch tube is controlled by the second detection signal, a first path end of the switch tube receives an inverted signal of the latch signal, and a second path end of the switch tube provides a switching signal.
Optionally, the switching unit includes:
a first path connected between an output of the second enable signal and the control output;
a second path connected between an output of the second clock signal and the control output;
a third path connected between an output of the reference signal and the control output;
when the switching signal is in a first level state, the third path is conducted;
and when the switching signal is in a second level state, the first path and the second path are conducted.
Optionally, the first path includes a first transistor connected between an output of the second enable signal and the control output, the second path includes a second transistor connected between an output of the second clock signal and the control output, and the third path includes a third transistor connected between an output of the reference signal and the control output.
Optionally, a control end of the first transistor receives an inverted signal of the switching signal, a first path end receives the second start signal, and a second path end is connected to the control output end;
the control end of the second transistor receives an inverted signal of the switching signal, the first path end receives the second clock signal, and the second path end is connected with the control output end;
a control end of the third transistor receives the switching signal, a first path end receives the reference signal, and a second path end is connected with the control output end;
when the first path is conducted, taking the second starting signal as the starting control signal;
when the second path is conducted, the second clock signal is used as the clock control signal;
and when the third path is conducted, taking the reference signal as the starting control signal and the clock control signal.
Optionally, the switch transistor includes an N-type thin film transistor, the first transistor includes an N-type thin film transistor, the second transistor includes an N-type thin film transistor, and the third transistor includes an N-type thin film transistor.
Optionally, the adjusting circuit further comprises: and the first inverter is connected between the latch and the first path end of the switching tube and is used for providing an inverted signal of the latch signal.
Optionally, the switching unit further includes: and a first end of the second inverter is connected with the second path end of the switching tube, and a second end of the second inverter is connected with the control end of the first transistor and the control end of the second transistor and is used for providing an inverted signal of the switching signal.
According to another aspect of the embodiments of the present invention, there is provided a display device including:
the display panel comprises the driving circuit arranged in the non-display area of the display panel.
According to the driving circuit and the display device provided by the embodiment of the invention, whether the time for outputting the gray scale voltage by the source driving circuit is prior to the rising edge of the second start signal output by the level shifting circuit is detected. And if not, taking the second starting signal as the starting control signal and taking the second clock signal as the clock control signal, so that the grid driving circuit generates a plurality of grid driving signals according to the starting control signal and the clock control signal. Therefore, the problem that the rising edge of the second starting signal provided for the grid driving circuit lags behind the gray scale voltage output by the source driving circuit, so that the grid driving circuit is damaged due to large current leakage is solved, and the service life of the display device is prolonged.
Drawings
The above and other object features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 shows a schematic structural view of a related art display device.
Fig. 2 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Fig. 3 shows a schematic structural diagram of an adjusting circuit according to an embodiment of the present invention.
Fig. 4 shows a signal waveform diagram of fig. 3.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown.
Numerous specific details of the invention are set forth in the following description in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
Fig. 2 is a schematic structural diagram of a display device according to an embodiment of the present invention.
As shown in fig. 2, the display device of the embodiment of the present invention includes: the display device includes a display panel 2100, a backlight module (not shown), a timing control circuit 2200, a gate driving circuit 2300, a source driving circuit 2400, a level shift circuit 2500, and an adjustment circuit 2600.
The display panel 2100 includes n × m pixel cells of an n × m array, n gate lines G1 to Gn, and m source lines S1 to Sm, m and n being natural numbers of 1 or more, respectively. Each pixel unit includes a pixel capacitance (formed by a pixel electrode and a common electrode) and a transistor electrically connected to the pixel electrode. The transistor is, for example, a Thin Film Transistor (TFT). In the display panel 2100, the gates of the transistors in the pixel units in the same row (the "row" corresponds to, for example, the lateral direction shown in the figure) are connected and one gate line is drawn toward the edge area of the display panel 2100, and the pixel units in n rows may draw the gate lines G1 to Gn toward the edge area of the display panel 2100. The sources of the transistors in the pixel cells located in the same column (the "column" corresponds to, for example, the longitudinal direction shown in the figure) are connected and one source line is drawn, and the m columns of pixel cells draw source lines S1 to Sm, respectively. In each pixel unit, the drain of the transistor is connected to the pixel electrode. The source driving circuit 2400 provides data signals to the source lines S1 through Sm for outputting the gray scale voltages Sgray to the pixel cells to change the gray scale levels of the respective pixel cells in the display panel 2100. The gate driving circuit 2300 supplies scan signals to the gate lines G1 to Gn for controlling the turn-on and turn-off of the pixel units of each row.
The timing control circuit 2200 provides a first start signal STV0 and a first clock signal CLK 0. The first start signal STV0 may be a one-frame start signal. The level shift circuit 2500 is connected to the timing control circuit 2200, and is configured to adjust the voltage ranges of the first start signal STV0 and the first clock signal CLK0 to obtain a second start signal STV1 and a second clock signal CLK1 corresponding to the adjusted voltage ranges. Alternatively, the level shift circuit 2500 boosts the first start signal STV0 and the first clock signal CLK0 of low voltage into the second start signal STV1 and the second clock signal CLK1 to drive Thin Film Transistors (TFTs) of pixel cells in the display panel 2100.
The gate driving circuit 2300 is connected to the adjusting circuit 2600 to receive the start control signal STV and the clock control signal CLK, and generate n gate driving signals according to the start control signal STV and the clock control signal CLK. The source driver circuit 2400 supplies the gray scale voltage Sgray1 according to the display data. The gray scale voltage Sgray1 may be a gray scale voltage corresponding to the first row of pixel units in the display panel 2100. In some embodiments, the gray scale voltage Sgray1 can also be the gray scale voltage corresponding to other rows of pixel units of the display panel 2100.
The adjustment circuit 2600 is connected to the source driving circuit 2400 to receive the gray scale voltage Sgray1, and connected to the level shift circuit 2500 to receive the second start signal STV1 and the second clock signal CLK 1. The adjustment circuit 2600 detects whether the time at which the source driver circuit 2400 outputs the grayscale voltage Sgray1 is earlier than the rising edge of the second start signal STV1, and if so, uses the reference signal VGH as the start control signal STV and the clock control signal CLK, and if not, uses the second start signal STV1 as the start control signal STV and the second clock signal CLK1 as the clock control signal CLK.
Alternatively, the level value of the reference signal VGH is equal to the level value when the second start signal STV1 and/or the second clock signal CLK1 are at a high level.
In addition, the number of the first clock signals CLK0 provided by the timing control circuit 2200 may be one or more, and the number of the first clock signals CLK0 may be determined according to the number of the clock control signals CLK required in the gate driving circuit 2300. Generally, in order to enable Thin Film Transistors (TFTs) in the display panel 2100 to be normally turned on row by row, four clock signals or more are generally required to achieve the display effect of the row by row scanning. Taking the example where the timing control circuit 2200 provides the four first clock signals CLK0, the timing control circuit 2200 generates the first start signal STV0 and sequentially generates the four first clock signals CLK0 at intervals of T1, T2, T3, and T4, respectively, with reference to the rising edge of the first start signal STV 0. Alternatively, the low level of the first start signal STV0 and the four first clock signals CLK0 is 0V, the high level is 3.3V, the duration of the high level is T5, and the period is T6. The second start signal STV1 boosted by the level shift circuit 2500 and the four second clock signals CLK1 have a low level of-6V and a high level of 30V, and the time interval, the high level duration and the cycle time of the four second clock signals CLK1 with respect to the rising edge of the second start signal STV1 are not changed.
In an alternative embodiment, the timing control circuit 2200 is further connected to the source driving circuit 2400 for providing the third clock signal CLKs to the source driving circuit 2400. In accordance with the third clock signal CLKs, the source driving circuit 2400 applies the gray-scale voltage Sgray corresponding to the display data to the pixel electrodes in the respective columns of pixel cells corresponding to the currently turned-on gate lines through the source lines S1 to Sm. It is understood that the number of the third clock signals CLKs provided by the timing control circuit 2200 to the source driving circuit 2400 may be determined according to the operational requirements of the source driving circuit 2400.
Fig. 3 shows a schematic structural diagram of an adjusting circuit according to an embodiment of the present invention. It should be noted that the transistors mentioned in this embodiment are all N-type thin film transistors, and the first via terminal and the second via terminal of each transistor may be interchanged (i.e., the drain and the source may be interchanged). Implementations of the invention are not so limited and in some other embodiments the transistors may also include P-type thin film transistors.
As shown in fig. 3, the adjustment circuit 2600 includes: the first comparator OP1, the second comparator OP2, and the latch L are, for example, an SR flip-flop, a switching unit 2610, a switch tube T1, and a first inverter I1.
The first comparator OP1 has a positive input terminal connected to the level shift circuit 2500 for receiving the second start signal STV1, a negative input terminal for receiving the first reference voltage Vref1, and an output terminal for providing the first detection signal. The first reference voltage Vref1 can be set according to the operation requirement of the gate driving circuit 2300. The second comparator OP2 has a positive input terminal connected to the source driving circuit 2400 for receiving the gray-scale voltage Sgray1, a negative input terminal for receiving the second reference voltage Vref2, and an output terminal for providing the second detection signal. The second reference voltage Vref2 may be set according to display data corresponding to each column of pixel cells in the display panel 2100.
The latch L provides a latch signal of a current state according to the first detection signal and a latch signal of a previous state. The switching unit 2610 supplies a start control signal STV and a clock control signal CLK to the control output terminal according to the latch signal and the second detection signal, respectively. The on and off of the switch tube T1 is controlled by the second detection signal, the first path terminal of the switch tube T1 receives the inverted signal of the latch signal, and the second path terminal provides the switching signal. The first inverter I1 is connected between the latch L and the first path terminal of the switch transistor T1 for providing an inverted signal of the latch signal.
The switching unit 2610 includes: a first path, a second path, and a third path. The number of the second paths and the third paths may be determined according to the number of the second clock signals CLK1, and it is to be understood that the number of the second paths and the third paths should not be construed as any limitation to the embodiments of the present invention.
The first path is connected between the output of the second start signal STV1 and the control output. The second path is connected between the output terminal of the second clock signal CLK1 and the control output terminal. The third path is connected between the output terminal of the reference signal VGH and the control output terminal. When the switching signal is in the first level state (high level), the third path is conducted. When the switching signal is in the second level state (low level), the first path and the second path are conducted. The first path includes a first transistor M1 connected between an output terminal and a control output terminal of the second start signal STV1, the second path includes a second transistor M2 connected between an output terminal and a control output terminal of the second clock signal CKL1, and the third path includes a third transistor M3 connected between an output terminal and a control output terminal of the reference signal VGH. It is to be understood that the number of the second transistor M2 and the third transistor M3 corresponds to the number of the second path and the third path, respectively, and the number of the second transistor M2 and the third transistor M3 should not limit the embodiments of the present invention in any way.
The control terminal of the first transistor M1 receives the inverted signal of the switching signal, the first path terminal receives the second start signal STV1, and the second path terminal is connected to the control output terminal. The control terminal of the second transistor M2 receives the inverted signal of the switching signal, the first path terminal receives the second clock signal CLK1, and the second path terminal is connected to the control output terminal. A control terminal of the third transistor M3 receives the switching signal, a first path terminal receives the reference signal VGH, and a second path terminal is connected to the control output terminal. When the first path is turned on, the second start signal STV1 is used as the start control signal STV. When the second path is on, the second clock signal CLK1 is used as the clock control signal CLK. When the third path is turned on, the reference signal VGH is used as the start control signal STV and the clock control signal CLK.
In an optional embodiment, the switching unit 2610 further includes: a second inverter I2. A first terminal of the second inverter I2 is connected to the second pass terminal of the switch transistor T1, and a second terminal of the second inverter I2 is connected to the control terminal of the first transistor M1 and the control terminal of the second transistor M2 for providing an inverted signal of the switching signal.
In the above embodiments, the Source driver circuit 2400 is implemented by using a Source driver chip (Source IC), for example, and the Gate driver circuit 2300 is implemented by using a Gate driver chip (Gate IC), for example.
Fig. 4 shows a signal waveform diagram of fig. 3. The principle of the driving circuit and the display device of the present invention will be described in detail with reference to fig. 3 and 4 and the specific embodiments.
The display apparatus shown in fig. 3 is powered by a switching power supply VCC (not shown), which can convert ac power into dc power and supply stable and reliable current to the display apparatus to control the power-on and power-off states of the display apparatus. When the switching power supply VCC supplies a high level, the display device starts to operate.
After the display device is turned on, the timing control circuit 2200 provides the first start signal STV0 and the first clock signal CLK0 to the level shifter circuit 2500. The timing control circuit 2200 also provides a third clock signal CLKs to the source driving circuit 2400. The source driving circuit 2400 applies a gray scale voltage Sgray corresponding to display data to pixel electrodes in each row of pixel units corresponding to the currently turned-on gate line through a plurality of data lines according to the third clock signal CLKs.
The level shift circuit 2500 is connected to the timing control circuit 2200, and adjusts the voltage ranges of the first start signal STV0 and the first clock signal CLK0 to obtain the corresponding second start signal STV1 and the second clock signal CLK1 after adjusting the voltage ranges. However, the level shift circuit 2500 often has a soft start, so that the source driving circuit 2400 outputs the gray scale voltage Sgray1 at a time earlier than the rising edge of the second start signal STV1 output by the level shift circuit 2500.
As shown in fig. 4, before the time T1, the timing at which the source driving circuit 2400 outputs the gray-scale voltage Sgray1 is earlier than the rising edge of the second start signal STV1 output by the level shift circuit 2500, the second comparator OP2 compares the gray-scale voltage Sgray1 with the second reference voltage Vref2, the gray-scale voltage Sgray1 is greater than the second reference voltage Vref2, and the second detection signal output by the second comparator OP2 is "1". When the second detection signal is at high level "1", the switch transistor T1 is turned on. The first comparator OP1 compares the second start signal STV1 with the first reference voltage Vref1, the second start signal STV1 is smaller than the first reference voltage Vref1, and the first detection signal output by the first comparator OP1 is "0". The set terminal S of the SR flip-flop L receives the first detection signal "0", the reset terminal R of the SR flip-flop L is set to "1", and then the latch signal output by the forward output terminal Q of the SR flip-flop L is "0". The latch signal output by the positive output end Q of the SR flip-flop L is inverted by the first inverter I1 to obtain an inverted signal "1" of the latch signal. The first path terminal of the switch tube T1 receives the inverted signal "1" of the latch signal, and the second path terminal provides the switching signal "1".
The switching signal "1" turns on the third path, and the inverted signal "0" of the switching signal turns off the first path and the second path. When the third path is turned on, the reference signal VGH is used as the start control signal STV and the clock control signal CLK.
After the time T1, the level shift circuit 2500 normally outputs the second start signal STV1, and the second comparator OP2 compares the gray-scale voltage Sgray1 with the second reference voltage Vref2, and the gray-scale voltage Sgray1 is greater than the second reference voltage Vref2, so the second detection signal output by the second comparator OP2 is "1". When the second detection signal is at high level "1", the switch transistor T1 is turned on. The first comparator OP1 compares the second start signal STV1 with the first reference voltage Vref1, the second start signal STV1 is greater than the first reference voltage Vref1, and the first detection signal output by the first comparator OP1 is "1". The set terminal S of the SR flip-flop L receives the first detection signal "1", the reset terminal R of the SR flip-flop L is set to "0", and then the latch signal output by the forward output terminal Q of the SR flip-flop L is "1". The latch signal output by the positive output end Q of the SR flip-flop L is inverted by the first inverter I1 to obtain an inverted signal "0" of the latch signal. The first path terminal of the switch tube T1 receives the inverted signal "0" of the latch signal, and the second path terminal provides the switching signal "0".
The switching signal "0" causes the third path to be closed, and the inverted signal "1" of the switching signal causes the first path and the second path to be conductive. When the first path is turned on, the second start signal STV1 is used as the start control signal STV. When the second path is on, the second clock signal CLK1 is used as the clock control signal CLK.
In some alternative embodiments, after the level shift circuit 2500 normally outputs the second start signal STV1, the SR flip-flop L may lock the operating state of the regulation circuit 2600 after the second start signal STV1 is normally output by setting the set terminal S and the reset terminal R of the SR flip-flop L to "0" at the same time.
According to the driving circuit and the display device provided by the embodiment of the invention, whether the time for outputting the gray scale voltage by the source driving circuit is prior to the rising edge of the second start signal output by the level shifting circuit is detected. And if not, taking the second starting signal as the starting control signal and taking the second clock signal as the clock control signal, so that the grid driving circuit generates a plurality of grid driving signals according to the starting control signal and the clock control signal. Therefore, the problem that the rising edge of the second starting signal provided for the grid driving circuit lags behind the gray scale voltage output by the source driving circuit, so that the grid driving circuit is damaged due to large current leakage is solved, and the service life of the display device is prolonged.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated.
Claims (10)
1. A driver circuit, comprising:
a timing control circuit providing a first start signal and a first clock signal;
the level shift circuit adjusts the voltage value ranges of the first starting signal and the first clock signal to generate a second starting signal and a second clock signal;
the gate driving circuit generates a plurality of gate driving signals according to the starting control signal and the clock control signal; and
a source driving circuit for providing a gray scale voltage according to display data;
wherein the driving circuit further comprises:
and the adjusting circuit is connected with the source electrode driving circuit to receive the gray scale voltage, is connected with the level shifting circuit to receive the second starting signal and the second clock signal, and detects whether the time of outputting the gray scale voltage by the source electrode driving circuit is prior to the rising edge of the second starting signal or not, if so, a reference signal is used as the starting control signal and the clock control signal, and if not, the second starting signal is used as the starting control signal and the second clock signal is used as the clock control signal.
2. The driving circuit according to claim 1, wherein the adjustment circuit comprises:
a first comparator, wherein the positive input end of the first comparator is connected with the level shift circuit to receive the second starting signal, the negative input end of the first comparator receives a first reference voltage, and the output end of the first comparator provides a first detection signal;
a positive input end of the second comparator is connected with the source electrode driving circuit to receive the gray scale voltage, a negative input end of the second comparator receives a second reference voltage, and an output end of the second comparator provides a second detection signal;
the latch provides a latch signal of the current state according to the first detection signal and the latch signal of the previous state; and
and the switching unit is used for respectively providing the starting control signal and the clock control signal to a control output end according to the latching signal of the current state and the second detection signal.
3. The driving circuit of claim 2, wherein the adjustment circuit further comprises:
and the on and off of the switch tube is controlled by the second detection signal, a first path end of the switch tube receives an inverted signal of the latch signal in the current state, and a second path end of the switch tube provides a switching signal.
4. The driving circuit according to claim 3, wherein the switching unit includes:
a first path connected between an output of the second enable signal and the control output;
a second path connected between an output of the second clock signal and the control output;
a third path connected between an output of the reference signal and the control output;
when the switching signal is in a first level state, the third path is conducted;
and when the switching signal is in a second level state, the first path and the second path are conducted.
5. The driver circuit of claim 4, wherein the first path comprises a first transistor coupled between the output of the second enable signal and the control output, wherein the second path comprises a second transistor coupled between the output of the second clock signal and the control output, and wherein the third path comprises a third transistor coupled between the output of the reference signal and the control output.
6. The driving circuit according to claim 5, wherein the control terminal of the first transistor receives an inverted signal of the switching signal, the first path terminal receives the second enable signal, and the second path terminal is connected to the control output terminal;
the control end of the second transistor receives an inverted signal of the switching signal, the first path end receives the second clock signal, and the second path end is connected with the control output end;
a control end of the third transistor receives the switching signal, a first path end receives the reference signal, and a second path end is connected with the control output end;
when the first path is conducted, taking the second starting signal as the starting control signal;
when the second path is conducted, the second clock signal is used as the clock control signal;
and when the third path is conducted, taking the reference signal as the starting control signal and the clock control signal.
7. The driving circuit as claimed in claim 6, wherein the switch transistor comprises an N-type thin film transistor, the first transistor comprises an N-type thin film transistor, the second transistor comprises an N-type thin film transistor, and the third transistor comprises an N-type thin film transistor.
8. The driving circuit of claim 3, wherein the adjustment circuit further comprises: and the first inverter is connected between the latch and the first path end of the switching tube and is used for providing an inverted signal of the latch signal.
9. The drive circuit according to claim 6, wherein the switching unit further comprises: and a first end of the second inverter is connected with the second path end of the switching tube, and a second end of the second inverter is connected with the control end of the first transistor and the control end of the second transistor and is used for providing an inverted signal of the switching signal.
10. A display device, comprising:
a display panel comprising the driving circuit according to any one of claims 1 to 9 disposed in a non-display region thereof.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1716364A (en) * | 2004-06-29 | 2006-01-04 | 精工爱普生株式会社 | Driving circuit of electrooptical device, driving method, electrooptic device and electronic apparatus |
| CN1763596A (en) * | 2004-10-13 | 2006-04-26 | Nec液晶技术株式会社 | Mode-selecting apparatus, display apparatus including the same, and method of selecting a mode in display unit |
| CN108389555A (en) * | 2018-02-06 | 2018-08-10 | 昆山龙腾光电有限公司 | Driving circuit and display device |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1716364A (en) * | 2004-06-29 | 2006-01-04 | 精工爱普生株式会社 | Driving circuit of electrooptical device, driving method, electrooptic device and electronic apparatus |
| CN1763596A (en) * | 2004-10-13 | 2006-04-26 | Nec液晶技术株式会社 | Mode-selecting apparatus, display apparatus including the same, and method of selecting a mode in display unit |
| CN108389555A (en) * | 2018-02-06 | 2018-08-10 | 昆山龙腾光电有限公司 | Driving circuit and display device |
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