JP3150929B2 - Power off discharge circuit for liquid crystal display device and liquid crystal display device using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a liquid crystal display (LCD: L).
More specifically, the present invention relates to a circuit for discharging a gate-on voltage charged in a liquid crystal panel when a liquid crystal display device is powered off.

[0002]

2. Description of the Related Art In a general thin film transistor liquid crystal display device, one pixel is composed of one thin film transistor, a liquid crystal capacitor connected to the thin film transistor, and a storage capacitor. The thin film transistor functions as a switch for applying a voltage to the liquid crystal capacitor. When the transistor is turned on, the liquid crystal capacitor is charged by the gray scale voltage. The storage capacitor is connected in parallel with the liquid crystal capacitor, and prevents the voltage charged in the liquid crystal capacitor from leaking when the transistor is turned off. Here, a voltage required to turn on the thin film transistor is a gate-on voltage,
The voltage required for turning off is referred to as a gate-off voltage. In practical applications, the gate-on voltage is above 20V and the gate-off voltage is below -7V. As a liquid crystal panel becomes larger and has higher definition, a gate on / off voltage having a larger DC level is required. In such a thin film transistor liquid crystal display device, the voltage charged in the liquid crystal capacitor controls the light transmittance of the liquid crystal in the corresponding pixel, thereby displaying a color.

Hereinafter, a thin film transistor liquid crystal display device having a general front gate panel structure will be described with reference to the accompanying drawings. As shown in FIG. 1, the general thin film transistor liquid crystal display device includes a timing control circuit 1, a gate drive circuit 2, a source drive circuit 3, a gray scale voltage generator 4, a liquid crystal panel 5, a gate on / off voltage generator 6.
It consists of.

[0004] The timing control circuit 1 outputs a color signal (RGB).
, Synchronization signal (Hsync, Vsync) and clock signal (CLK)
And the output of the timing control circuit 1 is provided to a gate drive circuit 2 and a source drive circuit 3. The output of the gray voltage generator 4 is connected to be provided to the source driving circuit 3, and the gate on / off voltage (Von, Voff) output from the gate on / off voltage generator 6 is provided.
Are connected to be provided to the gate driving circuit 2. The liquid crystal panel 5 is composed of a number of gate lines G0 to Gn and a number of data lines D1 to Dm which intersect each other vertically. The gate driving circuit 2 is connected to each of the gate lines, and the source driving circuit 3 is connected to each of the data lines. When the liquid crystal panel 5 is examined in more detail, one thin film transistor, one holding capacitor Cst, and one liquid crystal capacitor Cp exist in a region where each gate line and a data line intersect. The thin film transistor has a gate connected to a gate line, a source connected to a corresponding data line, and a drain connected to a liquid crystal capacitor Cp and a storage capacitor Cst in parallel. The other terminal of the liquid crystal capacitor is connected to the common electrode,
The other terminal of the storage capacitor is connected to the previous gate line. Therefore, the voltage across the liquid crystal capacitor is determined by the common electrode voltage and the corresponding data line voltage, and the voltage across the storage capacitor is determined by the corresponding data line voltage and the previous gate line voltage. In particular, in the liquid crystal panel having the former gate structure, no pixel is connected to the first gate line G0. The former gate connection structure is widely used because it has an advantage that the aperture ratio is higher than that of the independent wiring method in which the holding capacitors are connected by a separate line.

The timing control circuit 1 controls the timing of the color signal using the color signals RGB, the synchronization signals Hsync and Vsync, and the clock signal CLK, and generates a control signal for operating the driving circuits 2 and 3. The grayscale voltage generator 4 and the gate on / off voltage generator 6 generate a large number of grayscale voltages and gate on / off voltages, respectively. The plurality of gray voltages are provided to the source driving circuit 3, and the gate on / off voltages are provided to the gate driving circuit 2. The gate drive circuit 2 includes a gate on / off voltage and timing control circuit 1
, A gate driving voltage for turning on each gate line sequentially for one horizontal scanning time is generated using the signal output from the gate driver, and the generated gate driving voltage is applied to each gate line. Here, one horizontal scanning time is a time consumed for applying a data driving voltage to all pixels connected to one gate line. The source drive circuit 3 selects one of the gray scale voltages for each data line according to the color signal output from the timing control circuit 1, and applies the selected voltage to the corresponding data line.
Next, each data line voltage is recorded in one row of pixels connected to the gate line that is turned on.

FIG. 2 shows an example of a gate drive voltage applied to the thin film transistor liquid crystal display having the preceding gate panel structure. Referring to FIG. 2, an arbitrary one gate line (Gn-1) includes one gate line (Gn-1) in one frame.
It turns out that it is turned on during the horizontal scanning time and turned off in the remaining section. Also, each gate line is sequentially turned on.

The operation of the liquid crystal panel in the gate on / off state will be described in detail. For example, in FIG. 1, when a gate-on voltage is applied to the gate line G1 and a gate-off voltage is applied to the remaining gate lines, all the thin film transistors connected to the gate line G1 are turned on. Next, a data driving voltage provided from the source driving circuit 3 through the data lines D1 to Dm is applied to the liquid crystal capacitor Cp1 and the holding capacitor Cst1 via the turned-on thin film transistor. Accordingly, the liquid crystal capacitor Cp1 is charged by the voltage corresponding to the difference between the data drive voltage and the common electrode voltage, and the storage capacitor Cp1 is charged.
st1 is charged by a voltage corresponding to a difference between the data driving voltage and the gate-off voltage of the previous gate line G0.
Also, the storage capacitor Cst2 of the next row connected to the gate line G1 is charged by the gate-on voltage applied to the gate line G1. During the gate-off period, the voltage across the storage capacitor Cst2 is higher than the voltage of the liquid crystal capacitor Cp2,
Since the liquid crystal capacitor Cp2 is continuously supplied with electric charge,
The liquid crystal capacitor Cp2 can hold the voltage applied when the gate is turned on.

In this state, when the user turns off the power switch or shuts off the external power supply due to a power failure or the like, it is necessary to completely discharge the charge stored in the holding capacitor in the liquid crystal panel and the liquid crystal capacitor. It takes some time. This is because when the power is cut off, the thin film transistor is turned off and the drain terminal floats (float).
This is because the charging charge of the holding capacitor and the liquid crystal capacitor is naturally discharged. As a result, there is a problem that the screen gradually disappears due to slow charge discharge even if the user shuts off the power supply. In addition, there is a problem that the liquid crystal is degraded due to the DC voltage acting on the liquid crystal capacitor for a predetermined time immediately after the power is cut off.

In order to solve the above problems, the applicant of the present invention has filed a Korean Patent Application No. 95-29444, entitled "Screen Erasing Circuit of Thin Film Transistor Liquid Crystal Display and Method of Driving the Same". In the above "screen eraser circuit of thin film transistor liquid crystal display device and driving method thereof", the voltage of the gate off terminal of the gate on / off voltage generator is rapidly discharged as soon as the power is turned off. In a power-on state, the gate-off terminal is substantially connected to a gate line in the liquid crystal panel by switching of a gate driving circuit. For example, when there are 400 gate lines, a gate-off voltage is applied to 399 gate lines, and a gate-on voltage is applied to one gate line. The above-mentioned patent is to quickly remove the charge stored in the storage capacitor and the liquid crystal capacitor of the panel by discharging the voltage of the gate-off terminal immediately after power-off.

[0010]

However, in the above-mentioned prior art, the charge charged by the liquid crystal capacitor and the holding capacitor connected to the gate line to which the gate-off voltage was applied immediately before power-off is removed. . Therefore, in a pixel to which a gate-on voltage has been applied immediately before power-off, there is a problem that not only does the screen disappear slowly but also degradation due to DC stress occurs.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and has as its object to rapidly discharge a gate line voltage to which a gate-on voltage has been applied during power-off. An object of the present invention is to provide a power off discharge circuit for a liquid crystal display device.

[0012]

The power-off discharge circuit according to the present invention is applied to a liquid crystal display device including a liquid crystal panel having a preceding gate connection structure. The liquid crystal panel includes a plurality of gate lines and a plurality of data lines crossing the gate lines, and a pixel is formed in a region where each of the gate lines crosses the data line. The pixel includes a thin film transistor, a liquid crystal capacitor, and a holding capacitor. The thin film transistor has a gate connected to a corresponding gate line, a source connected to a corresponding data line, and one terminal of a liquid crystal capacitor and a holding capacitor commonly connected to a drain of the thin film transistor. The other terminal of the liquid crystal capacitor is connected to the common electrode,
The other terminal of the storage capacitor is connected to the previous gate line.

The liquid crystal display device has a gate-on / off voltage generator having gate-on and gate-off terminals, and a gate drive circuit connected to the gate-on and gate-off terminals of the voltage generator and connected to each gate line of the liquid crystal panel. including. The gate on / off voltage generator generates a gate on voltage and a gate off voltage and provides them to the terminal, and the gate driving circuit generates one of the gate on or off voltage for each gate line according to a predetermined control signal. And applies the selected voltage to the corresponding gate line. At this time, the control signal is predetermined so that each gate line is sequentially turned on.

In order to achieve the above object, a power-off discharge circuit according to the present invention comprises a transistor having a drain connected to a gate-on terminal of the gate-on / off voltage generator, a source having a ground, and a bias voltage applied to the gate of the transistor. And a power-off sensing circuit to provide. The power-off sensing circuit generates a bias voltage for turning off the transistor in a power-on state, and generates a bias voltage for turning on the transistor in a power-off state. Accordingly, in the power-off state, when the transistor is turned on by the power-off sensing circuit, the voltage of the gate-on terminal is rapidly discharged through the current path formed by the transistor and the ground.

According to a feature of the present invention, the power-off sensing circuit includes a diode having an anode connected to a first voltage and a capacitor having one end connected to a cathode of the diode and the other end connected to a second voltage. Is done. A contact between the diode and the capacitor is connected to a gate of the transistor. The threshold voltage of the diode is Vth
1. When the threshold voltage of the transistor is Vth2, the first voltage is preferably smaller than (Vth1 + Vth2), and the second voltage is [first voltage− (Vth2).
1 + Vth2)]. The first voltage is preferably a ground or a negative voltage. Under these conditions, in the power-on state, the potential at the contact point between the diode and the capacitor is a voltage that is lower than the first voltage by the threshold voltage Vth1 of the diode. Therefore, the transistor is an NMOS (N-typ)
In the case of eMetal Oxide Semiconductor, the transistor is turned off by the potential of the contact. The capacitor is charged by a voltage corresponding to a difference between the potential of the contact and a second voltage. At this time, when the power is turned off, the first voltage value and the second voltage value become zero. Since the capacitor has an attribute to hold the voltage between both ends, the potential of the contact is minimized by the threshold voltage Vth2.
Greater value. As a result, the threshold voltage Vth
With the potential of the contact greater than two, the transistor is turned on and the voltage at the gate-on terminal can be rapidly discharged.

According to another feature of the invention, the power-off sensing circuit includes an inverter having an input terminal, an output terminal, a positive voltage terminal, and a ground terminal; and an inverter having an input terminal and a positive voltage terminal. The inverter includes a resistor connected between the positive voltage terminal and the ground terminal of the inverter. A power supply voltage is applied to an input terminal of the inverter, and an output terminal of the inverter is connected to a gate of the transistor. The inverter provides a voltage at a positive voltage terminal to an output terminal when the power supply voltage is at a low level;
When the power supply voltage is at the high level, the ground level is provided to the output terminal. In a power-on state, the power supply voltage is at a high level, and in a power-off state, the power supply voltage is at a low level. Therefore, the voltage at the output terminal of the inverter becomes the ground level in the power-on state, and becomes the voltage at the positive voltage terminal in the power-off state. In the power-on state, the output of the inverter is at the ground level, so that the transistor is continuously turned off. The voltage at the positive voltage terminal is a value obtained by delaying the power supply voltage by a time constant determined by the resistor and the capacitor. If the power-on state changes to the power-off state, the power supply voltage goes to a low level. At the positive voltage terminal, the power supply voltage is held at a high-level power supply voltage for a time determined by the time constant, and then goes to a low level. Go down. While the power supply voltage drops to a low level and is held at a high level at the positive voltage terminal, the inverter outputs a high level voltage at the positive voltage terminal. Accordingly, the voltage output from the inverter turns on the transistor, and the gate-on voltage can be discharged through the transistor.

[0017]

Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 3 is a configuration diagram of a liquid crystal display device to which the power-off (Von) discharge circuit according to the first embodiment of the present invention is applied. As shown in FIG. 3, the power-off discharge circuit according to the first embodiment of the present invention. Is applied to a liquid crystal display device including a timing control circuit 1, a gate drive circuit 2, a source drive circuit 3, a grayscale voltage generator 4, a liquid crystal panel 5, a gate on / off voltage generator 6, and a gate on voltage discharge circuit 7. Is done.

Among the components, the same components as those of the liquid crystal display device shown in FIG. 1 are denoted by the same reference numerals. As described above, the liquid crystal panel 5 has a front gate connection structure, and the gate-on voltage discharge circuit 7 according to the first embodiment of the present invention is connected to the gate-on terminal between the gate-on / off voltage generator 6 and the gate drive circuit 2. Have been.

FIG. 4 shows the gate-on voltage discharging circuit 7 of FIG. 3 in more detail. Referring to FIG. 4, the gate-on voltage discharging circuit 7 includes a transistor T1, a diode D
1 and a capacitor C1. The transistor T1 is an NMOS, the drain is connected to the gate-on terminal, and the source is grounded. Diode D
The first voltage Va is applied to the anode of the first transistor T1, and the cathode is connected to the gate of the transistor T1. The second voltage Vb is applied to one end of the capacitor C1, and the other end of the capacitor C1 is connected to the cathode of the diode D1 and the transistor T1.
It is connected to the contact N1 of one gate. The diode D
It is assumed that a threshold voltage of 1 is Vth1 and a threshold voltage of the transistor T1 is Vth2.

Next, the operation of the gate-on voltage discharging circuit according to the first embodiment of the present invention will be described with reference to FIGS. When in the power-on state, the contact N
1 is equal to the threshold voltage Vth2 of the transistor T1.
Must be smaller. This is because, in the power-on state, the transistor must be turned off so that the discharge at the gate-on terminal by the transistor T1 does not occur. Since the potential of the contact N1 in the power-on state is represented by Va-Vth1, the equation of Va-Vth1 <Vth2 holds. Therefore, the expression Va <Vth1 + Vth2 must be satisfied.

In the power off state, the second
Since the voltage Vb is at the ground level, the potential of the contact N1 is the voltage charged across the capacitor C1 in the power-on state. Such an operation is usually called charge pumping. Since the transistor T1 must be turned on in the power-off state, the voltage across the capacitor must be higher than the threshold voltage Vth2 of the transistor T1 in the power-on state. This is represented by the following equation.

(Va-Vth1) -Vb> Vth2 This equation is also expressed as Vb <Va- (Vth1 + Vth2). In order to satisfy the above-described bias condition, in the first embodiment of the present invention, it is assumed that the first voltage is 0V and the second voltage is -10V. Here, the threshold voltages Vth1 and Vth2 are generally considered to be 0.7V.

In the power-on state, the diode D1
Is turned on, and the capacitor C1 holds a voltage corresponding to the difference between the potential of the contact N1 and the second voltage Vb.
As shown in FIG. 5, the potential VN1 of the contact N1 is -0.7 V
It is. The -0.7V turns off the transistor T1, and the voltage Von of the gate-on terminal is provided to the gate driving circuit 2.

In this state, when the power supply enters a power-off state in which the external power supply is cut off, second voltage Vb is set to ground level 0V
And the potential VN1 of the contact N1 becomes the voltage across the capacitor C1 by charge pumping. The capacitor C1
Is the potential V of the contact N1 in the power-on state.
Since it is the difference between N1 and the second voltage Vb, -0.7-(-10) = 9.3V.

Referring to FIG. 5, immediately after power-off, the second
The voltage Vb becomes the ground level 0 V, and the potential VN of the contact N1
It can be seen that 1 becomes 9.3V. The voltage of 9.3V gradually decreases due to the spontaneous discharge of the capacitor C1. Therefore,
The transistor T1 is turned on by the 9.3V gate voltage, and the voltage Von at the gate-on terminal shown in FIG. 5 is rapidly discharged.

The above-described first embodiment of the present invention discloses a power-off sensing circuit using first and second voltages assumed in advance and charge pumping of a capacitor.
The power-off sensing circuit provides the bias condition required in the present invention to the transistor. When the transistor is turned on immediately after power off, the voltage of the gate-on terminal can be rapidly discharged.

Next, a gate-on voltage discharging circuit 8 according to a second embodiment of the present invention will be described with reference to FIGS. The gate-on voltage discharging circuit 8 according to the second embodiment of the present invention is connected to the gate-on terminal between the gate-on / off voltage generator 6 and the gate driving circuit 2 of FIG.

Referring to FIG. 6, a gate-on voltage discharging circuit 8 according to a second embodiment of the present invention includes a PMOS (P-type
Metal Oxide Semiconductor) Transistor T2, two NMOS transistors T3, T4, three resistors R1, R
2, R3 and two capacitors C2, C3. The two transistors T2 and T3 are CMOS (Com
(Plementary Metal Oxide Semiconductor) Consists of an inverter. Each of the two transistors T2 and T3 has a drain and a gate connected to each other. A common gate of the two transistors T2 and T3 is an input terminal, and a common drain is an output terminal. The input terminal has a power supply voltage V
cc is applied, and this voltage Vcc is 5 V normally used in the system. A resistor R1 is connected between a source of the transistor T2 and an input terminal, and a source of the transistor T3 is grounded. A capacitor C2 is connected between the source of the transistor T2 and the ground. The drain of the transistor T4 is connected to a contact N2 between the gate-on terminal and the gate driving circuit 2 via a resistor R3, and the source is grounded. A capacitor C3 is connected between the gate of the transistor T4 and the ground, and a resistor R is connected between the common drain of the two transistors T2 and T3 and the gate of the transistor T4.
2 are connected.

In the second embodiment of the present invention, it is assumed that the threshold voltage of the transistor T2 is -1.5V, and the threshold voltages of the transistors T3 and T4 are 1.5V. In the second embodiment of the present invention, a power-off detection method for detecting a power-off state by using a power supply voltage VCC, an inverter and a resistor-capacitor circuit is applied.

In a power-on state where external power is normally supplied, the power supply voltage VCC is 5V. The transistor T3 of the inverter is turned on by 5V applied to the input terminal Vin, and the potential of the output terminal Vout becomes the ground level 0V. The 0 V potential is applied to the transistor T4
Is turned off, and the voltage of the gate-on terminal is provided to the gate drive circuit 2 without being discharged.

When a power-off state is entered in this state, power supply voltage VCC drops to ground level 0V. Since the resistor R1 and the capacitor C2 form a series RC circuit, the power supply voltage VCC appears at the junction of the two elements R1 and C2 after being delayed by a time constant determined by the resistance value and the capacitance. Thereafter, the voltage charged in the capacitor C2 is naturally discharged. Referring to FIG. 7, the power supply voltage VCC drops rapidly to the ground level 0 V immediately after power-off, and the potential Vc at the contact point between the resistor R1 and the capacitor C2 is 5 V for a time t1 determined by the time constant from the time of power-off. Then gradually decrease.

During the time t1, the gate-source voltage of the transistor T2 is -5 V, and the gate-source voltage is smaller than the threshold voltage.
Is turned on. Accordingly, the common drain voltage of the two transistors T2 and T3 becomes the potential Vc of the contact. The common drain voltage charges the capacitor C3, and the potential Vd at the contact point between the resistor R2 and the capacitor C3 rises to 4V. Here, rising to 4V means that
This is because the potential Vc of the contact drops partially due to the resistance R2. FIG. 7 shows a waveform in which the potential Vd of the contact changes with time. In the time interval t1, the potential of the contact Vd is the threshold voltage of the transistor T4.
At the moment when the voltage exceeds 5V, the transistor T4 is turned on. That is, in a section where the potential Vd of the contact is higher than 1.5 V, the transistor T4 is always turned on. When the transistor T4 is turned on, the voltage of the gate-on terminal is rapidly discharged, and the potential of the contact N2 rapidly decreases as shown in FIG.

After the elapse of the time interval t1, as shown in FIG. 7, the discharge of the capacitor C2 causes the potential Vc of the contact point to be reached.
Gradually decreases. Also at this time, if the potential Vc of the contact is higher than 1.5 V, the gate-source voltage becomes -1.5 V
Since it is less, transistor T2 is turned on. While the transistor T2 is turned on, the potential Vd at the contact changes almost the same as the potential Vc at the contact.
Therefore, the potential Vd of the contact also becomes 4 when the time interval t1 elapses.
It gradually drops from V.

When the potential Vc of the contact becomes lower than 1.5 V, the transistor T2 is turned off and the voltage across the capacitor C3 is discharged naturally. The interval t2 where the potential Vc of the contact is larger than 1.5 V is determined by the time constant of the capacitor C3 and the resistor R2. That is, if the time required to completely discharge the voltage of the gate-on terminal is determined, the transistor T4 must be turned on for longer than this time. The turn-on time of the transistor T4 can be adjusted by a time constant determined by the resistor R2 and the capacitor C3.

The gate-on voltage discharging circuit according to the second embodiment uses the transistor T4 only in the power-off state.
Is turned on to discharge the voltage of the gate-on terminal. On the other hand, in the second embodiment, the common drain terminal of the two transistors T2 and T3 can be directly connected to the gate of the transistor T4. In this case, the turn-on time of the transistor T4 can be adjusted by a time constant determined by the resistor R1 and the capacitor C2.

[0036]

As described above, the power-off discharge circuit according to the present invention senses the power-off state and immediately discharges the voltage of the gate-on terminal immediately after power-off. Therefore, the liquid crystal display device to which the present invention is applied can prevent the image by the pixel line on the panel to which the gate-on voltage is finally applied after power-off from gradually disappearing. Further, the power-off discharge circuit according to the present invention can prevent the deterioration of the liquid crystal due to DC stress by rapidly discharging the gate-on voltage remaining on the panel immediately after power-off.

As mentioned above, the present invention has been described with reference to the most practical and preferred embodiments, but the present invention is not limited to these embodiments, but rather falls within the spirit and scope of the appended claims. Construed to include various modifications and equivalents.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a conventional liquid crystal display device.

FIG. 2 is a waveform diagram showing an example of a gate line voltage for driving the liquid crystal display device shown in FIG.

FIG. 3 shows a power-off Von according to the first embodiment of the present invention;
1 is a configuration diagram of a liquid crystal display device to which a discharge circuit is applied.

FIG. 4 shows a power-off Von according to the first embodiment of the present invention;
It is a detailed circuit diagram of a discharge circuit.

FIG. 5 is a waveform diagram of main point voltages shown in the circuit of FIG. 4;

FIG. 6 shows a power-off Von according to a second embodiment of the present invention;
It is a detailed circuit diagram of a discharge circuit.

FIG. 7 is a waveform diagram of main point voltages shown in the circuit of FIG. 6;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 timing control circuit 2 gate drive circuit 3 source drive circuit 4 grayscale voltage generator 5 liquid crystal panel 6 gate on / off voltage generator 7, 8 gate on voltage discharge circuit

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Lee Hyung-kun 633 Daeol-dong, Daechi-dong, Gangnam-gu, Seoul, Korea No. 708 (56) References JP 9-127486 (JP, A) JP JP-A-6-104654 (JP, A) JP-A-7-104711 (JP, A) JP-A-8-220508 (JP, A) JP-A-2-2355092 (JP, A) JP-A-52-48338 (JP JP-A-61-281293 (JP, A) JP-A-4-58219 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G02F 1/133 505 G02F 1/133 520 G09G 3/36

Claims (16)

(57) [Claims] 1. A liquid crystal display device including a gate-on / off voltage generator having a gate-on terminal, comprising: a gate, a source, and a drain, wherein the drain is connected to the gate-on terminal, the source is grounded, and the source is grounded. A transistor to be turned on or off, a first voltage applied to the anode, a diode connected to the gate of the transistor at the cathode, a second voltage applied to one terminal, and a cathode connected to the diode and the transistor connected to the other terminal. And a capacitor connected to a contact between the gate of the power-off circuit and a power-off state, wherein the transistor is turned off by a potential of the contact in a power-on state, and the transistor is turned on by a potential of the contact in a power-off state. . 2. The power-off discharge circuit according to claim 1, wherein said transistor is an NMOS. 3. When the threshold voltage of the transistor is referred to as a first threshold voltage and the threshold voltage of the diode is referred to as a second threshold voltage, the first voltage is (first threshold voltage + first threshold voltage) in a power-on state. 2), the second voltage has a value smaller than (first voltage-first threshold voltage-second threshold voltage), and the first voltage in the power-off state. 3. The power-off discharge circuit according to claim 1, wherein the voltage and the second voltage are at a ground level. 4. A liquid crystal panel having a plurality of gate lines, one row of pixels connected to each gate line, and a storage capacitor of each pixel connected to a preceding gate line, and a gate on / off voltage. A gate-on / off voltage generator having a gate-on terminal and a gate-off terminal for generating and outputting the voltage; a gate-on / off voltage output from the gate-on / off voltage generator being input, in response to a predetermined control signal A gate drive circuit for selecting the gate on or off voltage for each gate line, and applying the selected voltage to each gate line; a gate, a source, and a drain; a drain connected to the gate on terminal; A transistor whose source is grounded and which is turned on or off depending on the gate voltage, and One voltage is applied, the cathode has a diode connected to the gate of the transistor, and the second terminal has one terminal applied, and the other terminal is connected to a contact between the cathode of the diode and the gate of the transistor. A liquid crystal display device comprising: a power-off discharge circuit including a capacitor, wherein the transistor is turned off by a potential of the contact in a power-on state, and the transistor is turned on by a potential of the contact in a power-off state. 5. The liquid crystal display device according to claim 4, wherein a transistor of the power-off discharge circuit is an NMOS. 6. When the threshold voltage of the transistor is a first threshold voltage and the threshold voltage of the diode is a second threshold voltage, the first voltage is (first threshold voltage + first threshold voltage) in a power-on state. A second threshold voltage), a value smaller than the second voltage (first voltage-first threshold voltage-second threshold voltage), and the first voltage in a power-off state. 6. The liquid crystal display device according to claim 4, wherein the second voltage is at a ground level. 7. A liquid crystal display device including a gate on / off voltage generator having a gate on terminal, comprising: a gate, a source, and a drain, wherein a drain is connected to the gate on terminal, a source is grounded, and a gate is connected to the gate. A transistor to be turned on or off; an input terminal, an output terminal, a power supply terminal, and a ground terminal; a power supply voltage is applied to the input terminal; the output terminal is connected to a gate of the transistor; An inverter for providing power at a power terminal or a ground terminal to an output terminal; a first resistor connected between an input terminal of the inverter and a power terminal; and between a power terminal and a ground terminal of the inverter. A power supply voltage is at a high level in a power-on state, and the power supply voltage is at a low level in a power-off state. At the moment of power-off, the power supply voltage is transmitted to the power supply terminal after being delayed for a predetermined time, so immediately after power-off, the voltage at the power supply terminal of the inverter is provided to the output terminal, and Power-off discharge circuit that turns on a transistor. 8. The method according to claim 1, wherein the delay time is equal to the first resistance and the first resistance.
The power-off discharge circuit according to claim 7, wherein the power-off discharge circuit is determined according to a time constant of a capacitor. 9. The pMOS having a source connected to the power supply terminal, a gate connected to the input terminal, and a drain connected to the output terminal.
A transistor having a source connected to the ground terminal, a gate connected to the input terminal, and a drain connected to the output terminal;
The power-off discharge circuit according to claim 7, comprising a transistor. 10. A second resistor connected between the output terminal of the inverter and the gate of the transistor, one end of which is grounded, and the other end connected between the second resistor and the gate of the transistor. The power-off discharge circuit according to claim 7, further comprising: a second capacitor connected to the inverter and charged by a voltage of an output terminal of the inverter. 11. The power-off discharge circuit according to claim 10, wherein a turn-on time of the transistor immediately after power-off is determined by a time constant of the second resistor and the second capacitor. 12. A liquid crystal panel having a plurality of gate lines, one row of pixels connected to each gate line, and a storage capacitor of each pixel connected to a liquid crystal panel connected to a previous gate line, and a gate on / off voltage. A gate-on / off voltage generator having a gate-on terminal and a gate-off terminal for generating and outputting the voltage; a gate-on / off voltage output from the gate-on / off voltage generator being input, in response to a predetermined control signal A gate drive circuit for selecting the gate on or off voltage for each gate line, and applying the selected voltage to each gate line; a gate, a source, and a drain; a drain connected to the gate on terminal; A transistor whose source is grounded and which is turned on or off according to the gate voltage; A power supply terminal, a power supply terminal, and a ground terminal; a power supply voltage is applied to an input terminal; the output terminal is connected to a gate of the transistor; and a power supply terminal or a ground terminal power supply is connected to an output terminal according to a state of the power supply voltage. An inverter provided, a first resistor connected between an input terminal of the inverter and a power terminal, and a first capacitor connected between a power terminal and a ground terminal of the inverter. In a power-on state, the power supply voltage is at a high level, in a power-off state, the power supply voltage is at a low level, and at the moment of power-off, the power supply voltage is transmitted to the power supply terminal after being delayed for a predetermined time. Therefore, the liquid crystal display device includes a power-off discharge circuit for turning on the transistor by supplying the voltage of the power supply terminal of the inverter immediately after power-off to the output terminal. 13. The delay time is determined according to a time constant of the first resistor and the first capacitor.
3. The liquid crystal display device according to 1. 14. The inverter of the power-off discharge circuit,
A source is connected to the power supply terminal, a gate is connected to the input terminal, and a drain is connected to the output terminal.
A transistor having a source connected to the ground terminal, a gate connected to the input terminal, and a drain connected to the output terminal;
13. The liquid crystal display device according to claim 12, comprising a transistor. 15. The power-off discharge circuit, comprising: a second resistor connected between an output terminal of the inverter and a gate of the transistor; one end grounded, and the other end connected to the second resistor and the transistor. The liquid crystal display of claim 12, further comprising: a second capacitor connected to a contact between the first and second gates and charged by a voltage of an output terminal of the inverter. 16. The liquid crystal display device according to claim 15, wherein a turn-on time of the transistor immediately after power-off is determined by a time constant of the second resistor and the second capacitor.