CN1755783A - Electric charge neutralization control circuit for liquid crystal display device and control method thereof - Google Patents

Electric charge neutralization control circuit for liquid crystal display device and control method thereof Download PDF

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Publication number
CN1755783A
CN1755783A CN 200410080067 CN200410080067A CN1755783A CN 1755783 A CN1755783 A CN 1755783A CN 200410080067 CN200410080067 CN 200410080067 CN 200410080067 A CN200410080067 A CN 200410080067A CN 1755783 A CN1755783 A CN 1755783A
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China
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mentioned
signal
liquid crystal
grid
time delay
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CN 200410080067
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Chinese (zh)
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黄信忠
黄俊颖
陈益正
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Chunghwa Picture Tubes Ltd
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Chunghwa Picture Tubes Ltd
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Priority to CN 200410080067 priority Critical patent/CN1755783A/en
Publication of CN1755783A publication Critical patent/CN1755783A/en
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Abstract

The control circuit for charging neutrality in LCD comprises disable signal detection unit and delay unit. Wherein, when detecting the LCD stopping display image signal, sending first signal to indicate power module disable and starting level of pixel transistor shut after first delay time, and second signal to indicate all pixel transistors to start their grid. Thereby, the grid of pixel transistor can neutralize stored charge in first delay time on source to solve tide phenomenon for different discharge speed of TFT.

Description

The charging neutrality control circuit and the method thereof of liquid crystal indicator
Technical field
The invention relates to a kind of charging neutrality circuit, and particularly utilize in the energy-accumulating element and the circuit arrangement of electric charge the invention that solves the tidal phenomena of LCD about a kind of.
Background technology
In the thin film transistor (TFT) manufacturing process, main technique comprises processes such as coating photoresistance material, exposure, development, film forming, etching.Wherein the step of coating photoresistance material since mainly with rotating disk bearing glass substrate with the coating photoresistance material, the photoresist that causes glass substrate zone line coating easily around coated photoresist thin; On the other hand, when etched step, the etching speed that the zone line of glass substrate is done passage etching backlight (Back Channel Etching (BCE)) causes the pathway closure leakage current of the thin film transistor (TFT) after finishing lower than next fast in peripheral region.Though this kind glass substrate is with the pixel capacitance accessing image data being cut into after panel sets dresses up module, however the pathway closure leakage current when power-off distribute and different according to different districts, the speed of discharge is also different naturally.Therefore, be positioned at the long time release electric charge of pixel capacitance needs when power-off of glass substrate zone line.
With reference to shown in Figure 1, Fig. 1 is with the liquid crystal panel synoptic diagram of thin film transistor (TFT) explained hereafter on glass substrate, comprise liquid crystal panel 100, be example wherein with the upper right corner pixel region 102 that is divided into four zones, the low and higher separatrix of sealing irregular curve 110 expression pathway closure leakage currents.When power-off, because 110 area surrounded need the long time to discharge electric charge, meaning is that the self-corresponding pixel of image time of disappearing is longer, for the user, can see and disappearing as residual picture such as the morning and evening tides, be example with 102 blocks, and the direction that disappears is shown in the direction of arrow among Fig. 1.
In addition, the common used thin film transistor (TFT) technology of LCD, cause the pairing conducting electric current of film crystal tube grid (Ion) and close leakage current (Ioff) and differ about 10 5 powers doubly to 6 powers, for example the transistor gate pole tension is 24V when conducting state, then Ion is about the mA order of magnitude, and the transistor gate pole tension is-6V then to close leakage current Ioff and be about the pA order of magnitude in off position the time.When display power supply is closed, because Ioff is little a lot of than Ion, so for resolution panels, the easier image retention tidal phenomena of observing; In more detail, cause the electric capacity difference when shutting power supply moment because of thin film transistor (TFT) thickness difference, required discharge time is also inequality, so the time that the liquid crystal rotation is replied is also different, so ghost picture as occurring ebbing tide as tide on panel.This moment, thin film transistor (TFT) itself also switched to closed condition, electric charge in pixel capacitance can only discharge via the data scanning line by leakage current, yet Ioff is the pA order of magnitude as can be known from the above mentioned, the velocity of discharge is for user's naked eyes, the significantly inhomogeneous afterimage that disappears just occurring, also is tidal phenomena.Non-purely the Ioff electric current raising of this phenomenon just can be improved, because the result who on technology the specification Ioff of thin film transistor (TFT) own is improved can cause other picture characteristics variation, flutter phenomenon (flicker) for example occurs.Therefore at the tidal phenomena of thin film transistor (TFT), need on circuit design, ask improvement.
With reference to figure 2A, the figure shows the circuit 200 that when power-off, the transistor gate pole tension is quickened to be pulled to earthing potential GND in the known technology, wherein utilize energy-accumulating element, move GND apace in the voltage trend that power-off makes grid voltage move the GND current potential gradually to simultaneously.Can find out respectively that by Fig. 2 B and Fig. 2 C improvement of circuit front and back grid potential returns the difference of earth level in response.Yet, be only applicable to thin film transistor (TFT) when closing with such mechanism, can rapidly its grid voltage be received the GND level; If the thin film transistor (TFT) cut-in voltage is the transistorized grid of conducting membrane effectively, then tidal phenomena still exists.Therefore, need a kind of circuit that effectively integrates, make grid voltage when power-off, still enough the electric charge on the pixel be neutralized effectively mutually, to solve the tidal phenomena problem of liquid crystal panel.
Summary of the invention
In sum, one object of the present invention is to provide a kind of charging neutrality control circuit, be applicable to display panels, need not changing under the condition of panel film-forming process, the tidal phenomena that can't provide effective discharge path to cause when closing because of thin film transistor (TFT) is provided.
Another purpose of the present invention is to provide a kind of charging neutrality control circuit, this circuit is to be integrated in the ASIC(Application Specific Integrated Circuit) (ASIC) that liquid crystal panel has, the time point of control TFT conducting, and machine in the film crystal tube grid standard-sized sheet on all liquid crystal panels, make liquid crystal panel that sufficiently high transistor triggering level be arranged after shutdown, effectively with the charging neutrality on the pixel, to eliminate tidal phenomena.
According to charging neutrality control circuit provided by the invention, be applicable to the tidal phenomena of eliminating display panels, a signaling switch detecting unit (signal-off detector) that is built in ASIC(Application Specific Integrated Circuit) (ASIC) in the utilization detects the state of control signal.When this signaling switch detecting unit detects output signal less than main control unit, the expression system is in closed condition, grid standard-sized sheet signal this moment (All-gate-on) is low activation level, and with the total conducting of the grid of thin film transistor (TFT)s all on the liquid crystal panel, the electric weight that accumulate liquid crystal storage capacitors by the loop this moment disengages via the source terminal of thin film transistor (TFT), with the storage capacitors in the pixel and the charging neutrality of other energy-accumulating element.
According to charging neutrality control circuit provided by the invention, adapt in the ASIC(Application Specific Integrated Circuit) (ASIC) of liquid crystal panel, this charging neutrality control circuit comprises signal detection component and gate delay unit, wherein this detecting signal unit is coupled to main logic unit, and provide two low level enable signals, one of them is power supply enable signal DC-DC.ENA, the switching device shifter place that is coupled to power input turns off input voltage, and be coupled to VGH delay cell, make VGH that be arranged time delay before turning off power supply, open required critical voltage with the grid of keeping thin film transistor (TFT).All the other for example analog voltage source, transistor close other power units such as voltage and common voltage, then be set in when the DC-DC.ENA signal is sent and close.This detecting signal unit is sent a grid in addition and is opened (All-gate-on) signal totally and make the grid of all thin film transistor (TFT)s open, and determine this of some actuation time, be controlled at DC-DC.ENA via the gate delay unit and begin action after producing specified time interval constantly.
General in the system of liquid crystal panel, normal shutdown programm is according to following order powered-down successively: backlight module, signal provide module and power module.Shutdown power supply sequential according to the present invention is with the described sequential operation in below.After the DC-DC.ENA action, analog voltage source VDDA, controlling grid scan line voltage VEEG and common voltage Vcom etc. all will close notable earlier, and its voltage all is decremented to zero potential GND in time.On the other hand, in order to allow the grid of thin film transistor (TFT) open totally, delay in the time of VGH must being closed, making has sufficiently high voltage level that grid is opened.And the mistiming after VGH and the DC-DC.ENA action is adjusted by VGH delay cell.Grid must just force all grids to open after VDDA is decremented to GND total opportunity of opening, and the path by the transistor source side reaches charging neutrality rapidly; Grid total opportunity of opening the latest must be before VGH voltage reaches the minimum voltage that can open transistorized grid.
In sum, charging neutrality control circuit among the present invention can be integrated on ASIC(Application Specific Integrated Circuit) (ASIC) module of liquid crystal panel, to solve the problem of tidal phenomena, utilization ASIC(Application Specific Integrated Circuit) (ASIC) internal circuit cooperates external circuit to reach, therefore can reduce the use number of element on the printed-wiring board (PWB), reach the effect that reduces cost, and the layout-design of simplifying printed-wiring board (PWB).Charging neutrality circuit in according to the present invention, control VGH opens opportunity, and opportunity of grid standard-sized sheet, opens when having enough VGH level to guarantee by film crystal after making the panel shutdown command assign, effectively the quantity of electric charge on the pixel is neutralized, to solve the morning and evening tides problem.In addition, owing to the reasons such as film-forming process of thin film transistor (TFT) cause the different tidal phenomenas that cause of transistor characteristic of each areal distribution on the panel, under the condition that does not change technology, utilize the present invention to improve.
State with other purpose, feature and advantage and can become apparent on the present invention for allowing, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 is the tidal phenomena synoptic diagram of the display panels painted according to known technology.
Fig. 2 A is the quick discharging circuit block schematic diagram of painting according to known technology.
Fig. 2 B is the capacitor discharge curve map of painting according to known technology.
Fig. 2 C is the electric capacity rapid discharge curve map of painting according to known technology.
Fig. 3 is the charging neutrality synoptic diagram of the corresponding thin film transistor (TFT) of pixel capacitance painted according to a preferred embodiment of the present invention.
Fig. 4 is the solution tidal phenomena integrated circuit block diagram of painting according to a preferred embodiment of the present invention.
Fig. 5 is the control signal synoptic diagram according to the solution tidal phenomena circuit of a preferred embodiment of the present invention.
Fig. 6 is the potential response synoptic diagram according to the thin film transistor (TFT) of a preferred embodiment of the present invention.
The main element symbol description
100 liquid crystal panels
102 block of pixels
The low and higher separatrix of 110 pathway closure leakage currents
200 quick discharging circuits
301 data scanning lines
302 controlling grid scan lines
310 electric charge energy-accumulating elements
320 transistors
400 solve the tidal phenomena circuit
410 ASIC(Application Specific Integrated Circuit)
412 main control units
414 signaling switch detecting units
416 grids are opened delay cell
420 power supply modules
430 VGH delay control units
Embodiment
Please refer to Fig. 4, Fig. 4 is the charging neutrality circuit arrangement synoptic diagram according to a preferred embodiment of the present invention, be applicable to the tidal phenomena of eliminating display panels system 400, be built in the utilization that a signaling switch detecting unit (signal-off detector) 414 comes the state of detection signal in the ASIC(Application Specific Integrated Circuit) (ASIC) 410.When this signaling switch detecting unit 414 detected less than main control unit 412 signals, expression liquid crystal panel system was in closed condition, and grid standard-sized sheet signal this moment (All-gate-on) is a low level, and with the total conducting of the grid of all thin film transistor (TFT)s.With reference to figure 3, Fig. 3 is that the pass through loop of expression in a preferred embodiment of the present invention makes electric charge that liquid crystal storage capacitors 310 the accumulated synoptic diagram via the source terminal neutralization of thin film transistor (TFT) 320.Wherein 301 is the source drive line, and 302 is the gate driving line; If can not controlling as method of the present invention, the source electrode of thin film transistor (TFT) 320 makes charging neutrality, also promptly the online signal of this gate driving can not make this grid be held open before charging neutrality in good time, then because technology causes the too small and uneven factor of leakage current when closing, electric charge on this transistor then must slowly discharge via the path of source drive line 301, and each regional transistor velocity of discharge is also different and produce tidal phenomena on the panel.
Referring again to Fig. 4, according to this charging neutrality control circuit that provides, adapt in the ASIC(Application Specific Integrated Circuit) (ASIC) 410 of liquid crystal panel, this charging neutrality control circuit comprises detecting signal unit 414 and grid unlatching delay cell 416, wherein this detecting signal unit 414 is coupled to main logic unit 412, and provide two low level enable signals, one of them is power supply enable signal DC-DC.ENA, the switching device shifter place that is coupled to the power input of power supply module 420 respectively turns off input voltage, and be coupled to transistor gate unblocked level (VGH) delay cell 430, make VGH that be arranged time delay before turning off power supply, open required critical voltage with the grid of keeping thin film transistor (TFT).All the other for example analog voltage source VDDA, transistor gate close other power units such as level VGL and common voltage VCOM, then set with the DC-DC.ENA signal and turn off simultaneously.This detecting signal unit 414 is sent all grids in addition and is all opened (All gate on) signal and make the grid of all thin film transistor (TFT)s open, and decision point actuation time, this time point begins action after can being controlled at the specified time interval of DC-DC.ENA by the gate delay unit.
General in the system of liquid crystal panel, normal shutdown programm is according to following order powered-down successively: backlight module, signal provide module and power module.Shutdown power supply sequential according to the present invention is by the power supply sequential operation of the following stated, as shown in Figure 5.After the DC-DC.ENA action, analog voltage source VDDA, controlling grid scan line voltage VEEG and common voltage Vcom etc. all will close notable earlier, and its voltage all is decremented to zero potential GND in time.On the other hand, in order to allow the grid of thin film transistor (TFT) open totally, delay in the time of VGH must being closed, making has enough voltage levels that grid is opened.And the mistiming after VGH and the DC-DC.ENA action is adjusted by VGH delay cell.Grid must just force all grids to open after VDDA is decremented to GND total opportunity of opening, and the path by the transistor source side reaches charging neutrality rapidly; Grid total opportunity of opening the latest must be before VGH voltage reaches the minimum voltage that can open transistorized grid.As shown in Figure 6, wherein the Origin And Destination of institute's grid start signal scope need be later than the Origin And Destination that VGH postpones range of control respectively.
Though the present invention with preferred embodiment openly as above; right its is not in order to limit the present invention; the ordinary skill of any technical field that the present invention belongs to; in thought that does not break away from the present invention and scope; when can doing a little change and improvement, so the present invention's protection domain is as the criterion when looking claims person of defining.

Claims (14)

1. charging neutrality control circuit, be applicable to liquid crystal indicator, above-mentioned liquid crystal indicator has power module, main control unit and image-display units at least, above-mentioned power module supply above-mentioned liquid crystal indicator required more than voltage level power supply, above-mentioned main control unit is controlled a plurality of gate drive signals and a plurality of source electrode drive signal of above-mentioned image-display units, it is characterized in that above-mentioned charging neutrality control circuit comprises:
Signal delay unit is coupled to above-mentioned image-display units; And detecting signal unit, be coupled to above-mentioned main control unit, wherein above-mentioned detecting signal unit learns from above-mentioned main control unit whether above-mentioned liquid crystal indicator shuts down, and provide the anergy signal to above-mentioned power module, make above-mentioned voltage level power supply anergy except that the pixel transistor unblocked level, and through making above-mentioned pixel transistor unblocked level anergy after first time delay, make within above-mentioned first time delay that the electric charge on a plurality of pixel transistors neutralizes via its source electrode in the above-mentioned image-display units, and providing grid standard-sized sheet signal to above-mentioned signal delay unit, above-mentioned grid standard-sized sheet signal exports above-mentioned image-display units to after postponing for second time delay via above-mentioned signal delay unit.
2. the charging neutrality control circuit according to claim 1, when it is characterized in that be decremented to critical grid voltage early than above-mentioned pixel transistor unblocked level above-mentioned first time delay, and the analog voltage source that be later than above-mentioned liquid crystal indicator above-mentioned second time delay is decremented to after the zero level.
3. the charging neutrality control circuit according to claim 1 is characterized in that above-mentioned main control unit, above-mentioned detecting signal unit and above-mentioned signal delay unit system are integrated on the ASIC(Application Specific Integrated Circuit) (ASIC).
4. charging neutrality control method makes the gate charge of each pixel transistor that liquid crystal indicator has effectively obtain discharging after grid is closed, and it is characterized in that comprising:
Detect above-mentioned liquid crystal indicator and stop display image;
The power module anergy that provides first signal to indicate above-mentioned liquid crystal indicator, and indication pixel transistor unblocked level was closed after first time delay; And
Provide secondary signal to indicate all above-mentioned pixel transistors after second time delay, to open its grid.
5. the charging neutrality control method according to claim 4 is characterized in that also comprising:
The total time point of opening of grid of specifying all above-mentioned pixel transistors reaches charging neutrality with the source terminal by above-mentioned pixel transistor within above-mentioned first time delay after the analog voltage source of the above-mentioned liquid crystal indicator of supply is decremented to zero level; And
The total time point of opening of grid of specifying all above-mentioned pixel transistors is before above-mentioned pixel transistor unblocked level voltage reaches the minimum voltage of the grid that can open above-mentioned pixel transistor.
6. the charging neutrality control method according to claim 4 is characterized in that above-mentioned pixel transistor is the technology formation with thin film transistor (TFT).
An ASIC(Application Specific Integrated Circuit) (Applied Specific IntegratedCircuit ASIC), is applicable to that electric capacity charges and discharge device, has a plurality of electric capacity, it is characterized in that comprising:
Main control unit;
Detecting signal unit, receive the first anergy signal of above-mentioned main control unit output, and export the second anergy signal to the power supply module of above-mentioned ASIC(Application Specific Integrated Circuit) outside, make a part of power supply while anergy of above-mentioned power supply module, and another part power supply anergy after first time delay in order to the above-mentioned electric capacity of gauge tap that above-mentioned power supply module is supplied; And
Delay cell receives the secondary signal of above-mentioned detecting signal unit output, exports above-mentioned electric capacity to after above-mentioned secondary signal was postponed for second time delay to charge and discharge device, and the switch of all above-mentioned electric capacity is opened totally.
8. a liquid crystal panel system in order to the operation liquid crystal panel, is controlled by a plurality of source electrode drive signals and a plurality of gate drive signal at least, comprising:
Control circuit is exported a plurality of data and a plurality of control signal;
Pel array, be coupled to above-mentioned control circuit, have a plurality of pixels and arrange with array way and form, wherein the corresponding transistor of each above-mentioned pixel with the above-mentioned data accepting control circuit and provide at least one of them and above-mentioned control signal at least one of them with display image;
Power module, in order to provide above-mentioned liquid crystal panel required more than voltage level power supply and receive at least a portion of the above-mentioned control signal of above-mentioned control circuit output,
It is characterized in that detecting the signal that above-mentioned liquid crystal panel stops display image when above-mentioned control circuit, then send first signal and secondary signal, above-mentioned first signal is indicated above-mentioned power module anergy, and indicate the pixel transistor unblocked level after first time delay, to close, above-mentioned secondary signal indicates the pairing above-mentioned transistor of all above-mentioned pixels to open its grid after second time delay.
9. described according to Claim 8 liquid crystal panel system is characterized in that above-mentioned crystal piping makes with the thin film transistor (TFT) film technique.
10. described according to Claim 8 liquid crystal panel system is characterized in that the method for indicating above-mentioned pixel transistor unblocked level to close comprises with first deferred mount to reach after above-mentioned first time delay.
11. described according to Claim 8 liquid crystal panel system is characterized in that the method for indicating the pairing above-mentioned thin film transistor (TFT) of all above-mentioned pixels to open its grid after above-mentioned second time delay comprises with second deferred mount to reach.
12. described according to Claim 8 liquid crystal panel system is characterized in that the above-mentioned voltage level power-off of above-mentioned first signal indication except that above-mentioned pixel transistor unblocked level.
13. described according to Claim 8 liquid crystal panel system is characterized in that above-mentioned first signal and above-mentioned secondary signal are the low level enable signal.
14. described according to Claim 8 liquid crystal panel system is characterized in that above-mentioned main control unit, above-mentioned detecting signal unit and above-mentioned delay cell system are integrated on the ASIC(Application Specific Integrated Circuit) (ASIC).
CN 200410080067 2004-09-27 2004-09-27 Electric charge neutralization control circuit for liquid crystal display device and control method thereof Pending CN1755783A (en)

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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100460939C (en) * 2007-04-11 2009-02-11 友达光电股份有限公司 Crystal-liquid display device and its pulse-wave adjusting circuit
CN101236730B (en) * 2007-01-31 2011-02-16 东芝松下显示技术有限公司 Liquid crystal display device capable of reducing irregularity in brightness
CN104036716A (en) * 2014-06-24 2014-09-10 上海中航光电子有限公司 Drive and control circuit and display device of display panel
CN105185329A (en) * 2015-09-06 2015-12-23 青岛海信电器股份有限公司 Image display method and liquid crystal display apparatus
WO2017049687A1 (en) * 2015-09-23 2017-03-30 深圳市华星光电技术有限公司 Goa circuit, display device, and driving method for goa circuit
CN107195282A (en) * 2017-07-17 2017-09-22 深圳市华星光电半导体显示技术有限公司 Discharge signal triggers circuit and display device
CN107610632A (en) * 2017-09-27 2018-01-19 京东方科技集团股份有限公司 Display driver circuit, electric power controller, display device and its driving method
CN109461412A (en) * 2018-12-26 2019-03-12 武汉天马微电子有限公司 A kind of organic light emitting display panel and organic light-emitting display device
CN112071833A (en) * 2019-11-05 2020-12-11 友达光电股份有限公司 Chip and method for manufacturing the same
CN113436587A (en) * 2021-06-22 2021-09-24 昆山龙腾光电股份有限公司 Regulating circuit

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101236730B (en) * 2007-01-31 2011-02-16 东芝松下显示技术有限公司 Liquid crystal display device capable of reducing irregularity in brightness
CN100460939C (en) * 2007-04-11 2009-02-11 友达光电股份有限公司 Crystal-liquid display device and its pulse-wave adjusting circuit
CN104036716A (en) * 2014-06-24 2014-09-10 上海中航光电子有限公司 Drive and control circuit and display device of display panel
CN105185329B (en) * 2015-09-06 2018-05-29 青岛海信电器股份有限公司 A kind of method for displaying image and liquid crystal display device
CN105185329A (en) * 2015-09-06 2015-12-23 青岛海信电器股份有限公司 Image display method and liquid crystal display apparatus
WO2017049687A1 (en) * 2015-09-23 2017-03-30 深圳市华星光电技术有限公司 Goa circuit, display device, and driving method for goa circuit
US10204579B2 (en) 2015-09-23 2019-02-12 Shenzhen China Star Optoelectronics Technology Co., Ltd GOA circuits, display devices and the driving methods of the GOA circuits
CN107195282B (en) * 2017-07-17 2018-02-16 深圳市华星光电半导体显示技术有限公司 Discharge signal triggers circuit and display device
CN107195282A (en) * 2017-07-17 2017-09-22 深圳市华星光电半导体显示技术有限公司 Discharge signal triggers circuit and display device
CN107610632A (en) * 2017-09-27 2018-01-19 京东方科技集团股份有限公司 Display driver circuit, electric power controller, display device and its driving method
CN107610632B (en) * 2017-09-27 2022-11-04 京东方科技集团股份有限公司 Display driving circuit, power management device, display apparatus and driving method thereof
CN109461412A (en) * 2018-12-26 2019-03-12 武汉天马微电子有限公司 A kind of organic light emitting display panel and organic light-emitting display device
CN112071833A (en) * 2019-11-05 2020-12-11 友达光电股份有限公司 Chip and method for manufacturing the same
CN112071833B (en) * 2019-11-05 2023-05-09 友达光电股份有限公司 Chip
CN113436587A (en) * 2021-06-22 2021-09-24 昆山龙腾光电股份有限公司 Regulating circuit
CN113436587B (en) * 2021-06-22 2022-09-23 昆山龙腾光电股份有限公司 Regulating circuit

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