CN212570354U - Liquid crystal display module discharge circuit - Google Patents
Liquid crystal display module discharge circuit Download PDFInfo
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- CN212570354U CN212570354U CN202021074280.8U CN202021074280U CN212570354U CN 212570354 U CN212570354 U CN 212570354U CN 202021074280 U CN202021074280 U CN 202021074280U CN 212570354 U CN212570354 U CN 212570354U
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Abstract
The utility model discloses a liquid crystal display module discharge circuit, including the first control signal input end of being connected with all TFT's of the TFT array of liquid crystal display module grid, the data line of each row of TFT array all is connected to first test signal input or second test signal input, first test signal input and second test signal input are through at least one electric charge release path ground connection, the break-make in at least one electric charge release path is controlled by the second control circuit, first control signal input is connected with the output of first control circuit, the output voltage of first control circuit and second control circuit responds to the mains voltage of liquid crystal display module. The utility model discloses a liquid crystal display module discharge circuit is in response to mains voltage after the liquid crystal display module shuts down, opens all TFT of TFT array to open charge release route, with the charge release of the TFT storage of TFT array after shutting down, appear scintillation or appear shutting the ghost when can effectively avoiding liquid crystal display panel to shut down.
Description
Technical Field
The utility model relates to an electronic circuit technical field, in particular to liquid crystal display module discharge circuit.
Background
In order to avoid the occurrence of shutdown ghost, an LCD (Liquid Crystal Display) needs to perform a discharging operation on all pixels inside a Display panel when the LCD is shut down, all gate lines are opened, all pixels release internal residual charges through connected data lines, and a Liquid Crystal Display module discharges by using a high resistance state output by a Source integrated circuit (Source IC) of the module when the Liquid Crystal Display module is shut down. A gate in array (gate in array) signal of a Gate In Array (GIA) model cannot be set to a high level when the GIA signal is turned off, and the GIA signal is connected to a transistor gate of an array substrate, so that a low level of a driving signal received by the gate of a transistor of the array substrate when the GIA signal is turned off cannot be in an on state when the GIA signal is turned off, and charges stored in the GIA signal cannot be timely and effectively released when a module is turned off, thereby causing a flicker phenomenon or a shutdown ghost of a liquid crystal display panel.
SUMMERY OF THE UTILITY MODEL
In view of the above problems, an object of the present invention is to provide a discharge circuit for a liquid crystal display module, so that the discharge circuit can discharge electric charges in time when the liquid crystal display module is turned off.
According to the utility model discloses an aspect provides a liquid crystal display module discharge circuit, liquid crystal display module discharge circuit is connected with the liquid crystal display module, the liquid crystal display module includes the mains voltage input to and the TFT array, wherein, liquid crystal display module discharge circuit includes:
a first control signal input terminal connected to a gate of each TFT of the TFTs of each row of the TFT array;
the test circuit comprises at least two test signal input ends, a first test signal input end and a second test signal input end, wherein a data line of each row of TFTs of the TFT array is connected to the first test signal input end or the second test signal input end;
at least one charge discharge path, each of the at least one charge discharge path including a discharge pass transistor, a discharge pass of the discharge pass transistor being disposed between the at least two test signal input terminals and ground;
the first control circuit comprises an output end connected to the first control signal input end, and the input end of the first control circuit is connected with the power supply voltage input end of the liquid crystal display module;
and the second control circuit comprises an output end connected with the grid electrode of the discharge path transistor of the at least one charge release path, and the input end of the second control circuit is connected with the power supply voltage input end of the liquid crystal display module.
Optionally, the internal signal of the liquid crystal display module includes a first gate control signal and a second gate control signal, a level of the first gate control signal is higher than a level of the second gate control signal, and the first control circuit includes:
the source electrodes of the first PMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube are connected with the first gate control signal, the source electrodes of the first NMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube are connected with the second gate control signal, the source electrodes of the first NMOS tube and the second NMOS tube are connected with the second gate control signal, the source electrodes of the third NMOS tube and the fourth NMOS tube are grounded, the drain electrode of the first PMOS tube is the output end of the first control circuit and is connected to the gate electrode of the second NMOS tube and the drain electrode of the first NMOS tube, the drain electrode of the second NMOS tube is connected with the drain electrode of the second PMOS tube and the gate electrode of the first NMOS tube, the drain electrode of the third PMOS tube is connected with the drain electrode of the third NMOS tube and is connected to the gate electrode of the second PMOS tube and the gate electrode of the fourth PMOS tube, and the drain electrode of the fourth PMOS tube is connected with the drain electrode of the third NMOS tube and the gate electrode of the fourth PMOS tube The grid electrode of the first PMOS tube, the grid electrode of the third NMOS tube are connected with the input end of the first control circuit, the input end of the phase inverter is connected with the input end of the first control circuit, and the output end of the phase inverter is connected with the grid electrode of the fourth NMOS tube.
Optionally, the data lines of the TFTs in each column of the TFT array are alternately connected to the first test signal input terminal and the second test signal input terminal.
Optionally, the at least one charge discharging path comprises a first charge discharging path and a second charge discharging path, the first charge discharging path and the second charge discharging path being connected in series between the first test signal input terminal and the second test signal input terminal, respectively, and ground.
Optionally, each of the at least one charge discharging path further comprises a discharge resistor connected in series between the discharge pass transistor and ground.
Optionally, the liquid crystal display module comprises an array substrate and a circuit board, the TFT array is disposed on the array substrate, and the first control circuit and the second control circuit are disposed on the circuit board, wherein,
the at least one charge discharging path is disposed on the array substrate.
Optionally, the discharge path transistor is a thin film transistor.
Optionally, the liquid crystal display module comprises an array substrate and a circuit board, the TFT array is disposed on the array substrate, and the first control circuit and the second control circuit are disposed on the circuit board, wherein,
the at least one charge discharging path is disposed on the circuit board.
Optionally, the number of the at least one charge discharging path is equal to the number of the test signal input terminals of the at least two test signal input terminals, and the at least one charge discharging path is connected in a one-to-one correspondence.
The utility model provides a liquid crystal display module discharge circuit includes the first control signal input end of being connected with the grid of all TFTs of the TFT array of liquid crystal display module, the data line of each row of TFT array all is connected to first test signal input end or second test signal input end, and first test signal input end and second test signal input end are through the ground connection of at least one charge release route, the break-make of at least one charge release route is responded to the output end voltage of second control circuit, first control signal input end is connected with the output of first control circuit, the output end voltage of first control circuit and second control circuit is responded to the mains voltage of liquid crystal display module, and it is responded to mains voltage after the liquid crystal display module shuts down, opens all TFTs of TFT array to open all at least one charge release route, the electric charge stored by the TFT of the TFT array is released after the liquid crystal display panel is shut down, so that the phenomenon of flicker or shutdown ghost when the liquid crystal display panel is shut down is avoided, wherein the first control signal input end and the at least two test signal input ends can be used for lighting test of the TFT array, the change of an original system is small, and the adaptability is strong.
The first control circuit and the second control circuit respond to the power voltage and output a first grid control signal or a second grid control signal, the first grid control signal or the second grid control signal is a standard grid control reference voltage signal of the liquid crystal display module, the control is accurate, no additional voltage source signal is added, and the circuit design is simple and effective.
And the data lines of each row of TFT of the TFT array are alternately connected to the first test signal input end and the second test signal input end, so that the lighting test effect is guaranteed.
Two charge releasing paths are arranged, and the stored charges of the TFT array are released in two paths, so that the discharging current can be reduced, and the possibility of damage of the large discharging current to the TFT is reduced.
Further, a discharge resistor is arranged in series on the charge release path to regulate and control discharge current and discharge speed and guarantee charge release efficiency.
The charge release path and the TFT array are arranged on the array substrate together, the demand of the extra connecting wires of the array substrate and the cost circuit board is less than that of the extra connecting wires of the charge release path arranged on the cost circuit board, the wiring difficulty is reduced, the mutual inductance influence between the current of the wires is reduced, and the normal operation of the system is guaranteed.
The charge release path is arranged on the finished circuit board, so that the extra space occupation of the array substrate provided with the TFT array can be reduced, the effective area of the array substrate is guaranteed, and the functionality of the array substrate is guaranteed.
The charge release paths and the test signal input ends are the same in number and are connected in a one-to-one correspondence mode, the design standard can be unified, the design difficulty is reduced, the fault tolerance is good, and the system stability is high.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
fig. 1 is a schematic structural diagram of a discharge circuit of a liquid crystal display module according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a first control circuit of a discharge circuit of a liquid crystal display module according to an embodiment of the present invention;
fig. 3 is a timing diagram of the level of each signal of the discharge circuit of the lcd module according to the embodiment of the present invention.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.
The following detailed description of the embodiments of the present invention is provided with reference to the accompanying drawings and examples.
Fig. 1 shows a schematic structural diagram of a discharge circuit of a liquid crystal display module according to an embodiment of the present invention.
Referring to fig. 1, the liquid crystal display module discharge circuit 100 according to an embodiment of the present invention includes a Thin Film Transistor (TFT) array 101, the TFT array 101 includes a plurality of data lines S01, the data line S01 is a column line, the data line S01 connects the source electrode of the TFT, the data line S01 connects the negative end 102 of the electrical circuit, the other end connects the positive end of the electrical circuit, the positive end of the electrical circuit includes a first test signal input terminal S1 and a second test signal input terminal S2, in this embodiment, two test signal input terminals of the first test signal input terminal S1 and the second test signal input terminal S2 are provided, and the TFT column is alternately connected to the first test signal input terminal S1 and the second test signal input terminal S2, and the gate of the T3 of each row of TFTs is connected to the first control signal input terminal ADD 1.
The first gate control signal VGH is provided to the first control signal input terminal ADD1, the TFTs in each TFT row T3 are turned on, i.e., all the TFTs of the TFT array 101 are turned on during the test, and different gray scale voltages are provided through the first test signal input terminal S1 and the second test signal input terminal S2, so that the TFT array 101 can display various gray scales and various pictures.
The liquid crystal display module discharge circuit 100 of the embodiment of the present invention further includes a first resistor R1, a second resistor R2, a first transistor T1, a second transistor T2, a first control circuit 111 and a second control circuit 112. The first resistor R1 and the second resistor R2 correspond to the two charge discharging paths respectively and can be used as discharging resistors to prevent the corresponding TFT from being damaged due to overlarge discharging current, and respective resistance values of the first resistor R1 and the second resistor R2 are selected according to the charge discharging speed and the discharging current requirements of actual requirements. In this embodiment, two charge release paths are provided, which may also reduce the discharge current of charge release, protect the device, and further provide more charge release paths, so as to increase the charge release speed, where the charge release paths and the test signal input terminals are equal in number and connected in a one-to-one correspondence manner, or unequal in number and connected in a certain proportion, for example, TFT rows are grouped and connected in a one-to-one correspondence manner to the charge release paths.
An output terminal of the first control circuit 111 is connected to the first control signal input terminal ADD1, and can provide the first gate control signal VGH or the second gate control signal VGL for output, an input terminal of the first control circuit 111 receives the first level control signal Detect1, and selects and outputs the first gate control signal VGH or the second gate control signal VGL according to the first level control signal Detect 1. In this embodiment, the level of the first gate control signal VGH is greater than the level of the second gate control signal VGL, the TFT is turned on in response to the first gate control signal VGH, the TFT is turned off in response to the second gate control signal VGL, the first control circuit 111 outputs the first gate control signal VGH when the liquid crystal display module is turned off, and the first control circuit 111 outputs the second gate control signal VHL when the liquid crystal display module is in a power-on operation state.
A source drain of the first transistor T1 and the first resistor R1 are connected in series between the first test signal input terminal S1 and ground, a source drain of the second transistor T2 and the second resistor R2 are connected in series between the second test signal input terminal S2 and ground, gates of the first transistor T1 and the second transistor T2 are connected to the second control signal input terminal ADD2, a corresponding voltage is applied to the second control signal input terminal ADD2, the first transistor T1 and the second transistor T2 are turned on, paths from the first test signal input terminal S1 and the second test signal input terminal S2 to ground are turned on, and when the first control signal input terminal ADD1 is simultaneously connected to the first gate control signal VGH, electrical paths from all TFTs of the TFT array 101 to ground are turned on to release charges. The first transistor T1 and the second transistor T2 act as discharge path transistors to control the on and off of the two discharge paths, and their on and off are controlled by the second control circuit 112.
The first transistor T1 and the second transistor T2 are turned off when the liquid crystal display module is turned on and operates normally, so that the TFTs of the TFT array 101 and the lines thereof are isolated from the ground, and the normal operation of the TFTs of the TFT array 101 is ensured.
The output end of the second control circuit 112 is connected to the second control signal input end ADD2, the input end receives a second level control signal Detect2, the first transistor T1 and the second transistor T2 are controlled to be turned on when the liquid crystal display module is turned off, all the TFTs of the TFT array 101 are turned on in cooperation with the first control circuit 111, and the second control circuit is connected to the ground to discharge charges stored in all the TFTs of the TFT array.
The first transistor T1 and the second transistor T2 can be TFTs, and are fabricated on the array substrate and fabricated together with the TFT array, thereby saving the production process.
In the present embodiment, two transistors, i.e., the first transistor T1 and the second transistor T2, are provided to correspond to two charge discharging paths, and in other embodiments, other numbers of charge discharging paths may be provided to ensure an effective path of the charge discharging paths, and the system may operate substantially normally when there is a small amount of damage.
The TFT array 101 is fabricated on an array substrate, the first control circuit 111 and the second control circuit 112 are fabricated on a finished circuit board PCBA, and the first transistor T1, the second transistor T2, the first resistor R1 and the second resistor R2 are fabricated on the array substrate and the PCBA in an alternative embodiment, respectively, wherein corresponding to the fabrication on the array substrate, the array substrate and the PCBA need to ADD a connection lead from the second control signal input terminal ADD2, i.e., the output terminal of the second control circuit 112, to the gates of the first transistor T1 and the second transistor T2, and a connection lead from the output terminal of the first control circuit 111 to the first control signal input terminal ADD 1; two connecting leads for the first transistor T1 and the second transistor T2 to the first test signal input terminal S1 and the second test signal input terminal S2, and a connecting lead from the output terminal of the first control circuit 111 to the first control signal input terminal ADD1 are added correspondingly to the manufacture on the PCBA.
Fig. 2 is a schematic structural diagram of a first control circuit of a discharge circuit of a liquid crystal display module according to an embodiment of the present invention.
In the liquid crystal display module discharging circuit 100 of the present embodiment, the first control circuit 111 and the second control circuit 112 have the same structure, and both output the second gate control signal VGL when the liquid crystal display module is turned on and normally operates, turn off the lighting test system, and output the first gate control signal VGH when the liquid crystal display module is turned off, turn on all the transistors, and turn on the charge releasing path to release the charges.
Referring to fig. 2, the first control circuit 111 is used for explanation, and the structure of the second control circuit 112 is the same as that of the first control circuit 111, and details of the second control circuit 112 are not described.
The first control circuit 111 includes a transistor P1, a transistor P2, a transistor P3, a transistor P4, a transistor N1, a transistor N2, a transistor N3, a transistor N4, and an inverter P, in this embodiment, the transistors P1, P2, P3, and P4 are PMOS (positive channel Metal Oxide Semiconductor) transistors, and the transistors N1, N2, N3, and N4 are NMOS (N-Metal-Oxide-Semiconductor) transistors.
The source of the transistor P1 is connected to the first gate control signal VGH, the drain is connected to the drain of the transistor N1, the source of the transistor N1 is connected to the second gate control signal VGL, the source of the transistor P2 is connected to the first gate control signal VGH, the drain is connected to the drain of the transistor N2, the source of the transistor N2 is connected to the second gate control signal VGL, the gate of the transistor N1 is connected to the drain of the transistor P2, the gate of the transistor N2 is connected to the drain of the transistor P1, and the drain of the transistor P1 is the output end of the first control circuit 111 and is connected to the first control signal input end ADD 1; the source of the transistor P3 is connected to the first gate control signal VGH, the drain is connected to the drain of the transistor N3, the source of the transistor N3 is connected to GND, the source of the transistor P4 is connected to the first gate control signal VGH, the drain is connected to the drain of the transistor N4, the source of the transistor N4 is connected to ground, the drain of the transistor P3 is connected to the gate of the transistor P4 and the gate of the transistor P2, the gate of the transistor P3 is connected to the drain of the transistor P4 and the gate of the transistor P1, the gate of the transistor N3 is connected to the input terminal of the first control circuit, the gate of the transistor N4 is connected to the input terminal of the first control circuit 111 through the inverter P, the input terminal of the inverter P is connected to the input terminal of the first control circuit 111, the output terminal is connected to the gate of the transistor N4, and the input terminal.
The first level control signal Detect1 includes a high level potential and a low level potential, which respectively correspond to the on and off of the transistor N4 and the transistor N3, wherein the high level is optionally 3.3V, the low level is 0V, which can be directly obtained from the original system, and the first gate control signal VGH and the second gate control signal VGL are standard transistor gate control signals in the system, which can be directly obtained from the original system, so as to reduce the setting requirement of an additional power supply of the circuit.
When the liquid crystal display template is powered on, the first level control signal Detect1 is at a high level, the transistor N3 is turned on, the transistor N4 is turned off, the drain of the transistor P3 is grounded, the transistor P4 is turned on, the drain of the transistor P4 is connected to the first gate control signal VGH, the gate of the transistor P2 is grounded and turned on, the gate of the transistor P1 is disconnected from the first gate control signal VGH, the first gate control signal VGH is connected to the gate of the transistor N1, the transistor N1 is turned on, the drain voltage of the transistor P1 is the second gate control signal VHL voltage, the disconnection of the transistor N2 is maintained, and the output end of the first control circuit 111 is maintained to output the second gate control signal VHL.
When the lcd panel is turned off, the first level control signal Detect1 is at a low level, for example, 0V, the transistor N3 is turned off, the transistor N4 is turned on, the drain potential of the transistor N4 is at a low level, the transistor P3 is turned on, the drain potential of the transistor P3 is at the first gate control signal VGH potential, the transistor P2 is turned off, the transistor P1 is turned on, the drain of the transistor P1 is connected to the first gate control signal VGH, the transistor N2 is turned on, the drain of the transistor N2 is only connected to the second gate control signal VGL, the transistor N1 is turned off, the drain of the transistor P1 is kept connected to the first gate control signal VGH only, and the output end of the first control circuit 111 is maintained to output the first gate control signal VGH.
Fig. 3 is a timing diagram of the level of each signal of the discharge circuit of the lcd module according to the embodiment of the present invention.
As shown in fig. 3, before time t1, the system power input voltage VIN is at a high level, the first level control signal Detect1 is at a high level, the first gate control signal VGH is at a high level, the level signal of the first control signal input terminal ADD1 is at a low level of the second gate control signal VHL, and the system source signal level Sout is at an operating level. Wherein the level signal of the system source signal level Sout corresponds to whether the charge in the TFT array is discharged completely.
At time t1, the lcd module is turned off, the system power input voltage VIN begins to decrease, the first level control signal Detect1 is maintained at a high level, the first gate control signal VGH is maintained at a high level, the level signal of the first control signal input terminal ADD1 is maintained at a low level of the second gate control signal VHL, and the system source signal level Sout is at a working level.
At time t2, the system power input voltage VIN continues to drop, the first level control signal Detect1 jumps to 0V after a short time delay from t1 to t2, the first gate control signal VGH is maintained at a high level, the level signal at the first control signal input terminal ADD1 becomes the high level of the first gate control signal VGH, all TFTs of the TFT array are turned on, the charge release path is turned on, and the system source signal level Sout starts to approach 0V.
At time t3, the system source signal level Sout is 0V, the TFT charges of the TFT array are completely released, and at this time, the system has not been completely shut down, the system power supply input voltage VIN continues to decrease, the first level control signal Detect1 is 0V, the first gate control signal VGH is maintained at a high level and starts to decrease, the level signal at the first control signal input end is maintained at a high level of the first gate control signal VGH and starts to decrease, the enabling of the first control circuit 111 is completed, and the system starts to release the energy of the first gate control signal VGH and the second gate control signal VGL.
And at the moment t4, the power supply is completely turned off, the input voltage VIN of the system power supply is reduced to 0V, the energy of the first gate control signal VGH is not completely released and continues to approach to 0V, and the voltage of the first control signal input end ADD1 is the output voltage of the first control circuit 111 and continues to approach to 0V along with the voltage of the first gate control signal VGH.
By time t5, the system is completely shut down and all signals are reduced to 0V.
The first control circuit 111 and the second control circuit 112 of the liquid crystal display module discharge circuit of the embodiment of the utility model stably output the second gate control signal VHL when the liquid crystal display module is started to operate, disconnect the charge release path, and ensure the normal operation of the TFT array of the liquid crystal display module; maintaining the voltage of the first gate control signal VGH during and after the shutdown of the liquid crystal display module, stably outputting the first gate control signal VGH, ensuring the opening of a charge release path, and releasing charges stored by TFTs of a TFT array; after the electric charge is released, the electric energy of the first grid control signal VGH of the system is released, and then the system is completely shut down. The charge stored by the TFT of the TFT array can be effectively ensured to be released in time after the power-off, and the phenomenon that the picture flickers or the power-off ghost shadow appears after the power-off of the liquid crystal display module is avoided.
The utility model discloses a liquid crystal display module discharge circuit utilizes the circuit basis of test system of lighting a lamp, add first control circuit and second control circuit, export first grid control signal VGH when the system shuts down, open all TFT of TFT array, and the charge release route of TFT to ground, the charge of the TFT storage of effective release TFT array when the system shuts down, can be applicable to the model separately, the phenomenon of the incomplete shadow of shutting down appears or the display frame scintillation that the electric charge in time effectively releases and brings when effectively having avoidd the system shutdown.
In accordance with the embodiments of the present invention as set forth above, these embodiments are not exhaustive and do not limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and its various embodiments with various modifications as are suited to the particular use contemplated. The present invention is limited only by the claims and their full scope and equivalents.
Claims (9)
1. The utility model provides a liquid crystal display module discharge circuit, liquid crystal display module discharge circuit is connected with the liquid crystal display module, the liquid crystal display module includes mains voltage input and TFT array, its characterized in that, liquid crystal display module discharge circuit includes:
a first control signal input terminal connected to a gate of each TFT of the TFTs of each row of the TFT array;
the test circuit comprises at least two test signal input ends, a first test signal input end and a second test signal input end, wherein a data line of each row of TFTs of the TFT array is connected to the first test signal input end or the second test signal input end;
at least one charge discharge path, each of the at least one charge discharge path including a discharge pass transistor, a discharge pass of the discharge pass transistor being disposed between the at least two test signal input terminals and ground;
the first control circuit comprises an output end connected to the first control signal input end, and the input end of the first control circuit is connected with the power supply voltage input end of the liquid crystal display module;
and the second control circuit comprises an output end connected with the grid electrode of the discharge path transistor of the at least one charge release path, and the input end of the second control circuit is connected with the power supply voltage input end of the liquid crystal display module.
2. The discharging circuit of claim 1, wherein the internal signal of the LCD module comprises a first gate control signal and a second gate control signal, the first gate control signal has a higher level than the second gate control signal, the first control circuit comprises:
the source electrodes of the first PMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube are connected with the first gate control signal, the source electrodes of the first NMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube are connected with the second gate control signal, the source electrodes of the first NMOS tube and the second NMOS tube are connected with the second gate control signal, the source electrodes of the third NMOS tube and the fourth NMOS tube are grounded, the drain electrode of the first PMOS tube is the output end of the first control circuit and is connected to the gate electrode of the second NMOS tube and the drain electrode of the first NMOS tube, the drain electrode of the second NMOS tube is connected with the drain electrode of the second PMOS tube and the gate electrode of the first NMOS tube, the drain electrode of the third PMOS tube is connected with the drain electrode of the third NMOS tube and is connected to the gate electrode of the second PMOS tube and the gate electrode of the fourth PMOS tube, and the drain electrode of the fourth PMOS tube is connected with the drain electrode of the third NMOS tube and the gate electrode of the fourth PMOS tube The grid electrode of the first PMOS tube, the grid electrode of the third NMOS tube are connected with the input end of the first control circuit, the input end of the phase inverter is connected with the input end of the first control circuit, and the output end of the phase inverter is connected with the grid electrode of the fourth NMOS tube.
3. The liquid crystal display module discharge circuit of claim 1,
and the data lines of each column of TFT of the TFT array are alternately connected to the first test signal input end and the second test signal input end.
4. The liquid crystal display module discharge circuit of claim 1 or 3,
the at least one charge discharging path includes a first charge discharging path and a second charge discharging path, which are respectively connected in series between the first test signal input terminal and the second test signal input terminal and ground.
5. The liquid crystal display module discharge circuit of claim 1,
each of the at least one charge discharge path further includes a discharge resistor connected in series between the discharge pass transistor and ground.
6. The liquid crystal display module discharge circuit of claim 1, wherein the liquid crystal display module comprises an array substrate on which the TFT array is disposed and a circuit board on which the first control circuit and the second control circuit are disposed, wherein,
the at least one charge discharging path is disposed on the array substrate.
7. The liquid crystal display module discharge circuit of claim 6,
the discharge path transistor is a thin film transistor.
8. The liquid crystal display module discharge circuit of claim 1, wherein the liquid crystal display module comprises an array substrate on which the TFT array is disposed and a circuit board on which the first control circuit and the second control circuit are disposed, wherein,
the at least one charge discharging path is disposed on the circuit board.
9. The liquid crystal display module discharge circuit of claim 1,
the number of the at least one charge release path is equal to that of the test signal input ends of the at least two test signal input ends, and the at least one charge release path is connected in a one-to-one correspondence manner.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113834992A (en) * | 2021-09-24 | 2021-12-24 | 昆山龙腾光电股份有限公司 | Test circuit and display panel |
| CN114038365A (en) * | 2021-11-29 | 2022-02-11 | 京东方科技集团股份有限公司 | Display panel detection method, device, equipment and storage medium |
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2020
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113834992A (en) * | 2021-09-24 | 2021-12-24 | 昆山龙腾光电股份有限公司 | Test circuit and display panel |
| CN114038365A (en) * | 2021-11-29 | 2022-02-11 | 京东方科技集团股份有限公司 | Display panel detection method, device, equipment and storage medium |
| CN114038365B (en) * | 2021-11-29 | 2023-12-26 | 京东方科技集团股份有限公司 | Display panel detection method, device, equipment and storage medium |
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