CN107516502B - Liquid crystal display panel driving circuit and driving method - Google Patents
Liquid crystal display panel driving circuit and driving method Download PDFInfo
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- CN107516502B CN107516502B CN201710948939.4A CN201710948939A CN107516502B CN 107516502 B CN107516502 B CN 107516502B CN 201710948939 A CN201710948939 A CN 201710948939A CN 107516502 B CN107516502 B CN 107516502B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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Abstract
The invention provides a liquid crystal display panel driving circuit and a driving method. The liquid crystal display panel driving circuit comprises a time schedule controller, a level conversion unit and a control signal generation unit, wherein the working mode of the liquid crystal display panel driving circuit comprises a reset mode, in the reset mode, the time schedule controller outputs a reset signal to the control signal generation unit, the control signal generation unit receives the reset signal and generates a corresponding control signal to be output to the level conversion unit, and the level conversion unit outputs a constant voltage high potential to a GOA circuit of the liquid crystal display panel under the control of the control signal, so that the liquid crystal display panel can rapidly discharge in the reset mode, and the phenomenon that overcurrent protection is triggered by overhigh current on a clock signal wire after the liquid crystal display panel enters the driving mode again is avoided.
Description
Technical Field
The invention relates to the technical field of liquid crystal display, in particular to a liquid crystal display panel driving circuit and a driving method.
Background
With the development of Display technology, flat panel Display devices such as Liquid Crystal Display (LCD) devices have been widely used in various consumer electronics products such as mobile phones, televisions, personal digital assistants, digital cameras, notebook computers, and desktop computers, and become the mainstream of Display devices, because of their advantages such as high image quality, power saving, thin body, and wide application range.
In the active liquid crystal display device, each pixel is electrically connected with a Thin Film Transistor (TFT), a Gate (Gate) of the TFT is connected to a horizontal scanning line, a Source (Source) is connected to a data line in a vertical direction, and a Drain (Drain) is connected to a pixel electrode. Applying sufficient voltage to the horizontal scanning lines can turn on all TFTs electrically connected to the horizontal scanning lines, so that signal voltage on the data lines can be written into the pixels, and different transmittances of liquid crystals can be controlled to achieve the effect of controlling color and brightness. Currently, the driving of the horizontal scanning lines of the active liquid crystal display panel is mainly performed by an external Integrated Circuit (IC), and the external IC can control the charging and discharging of each level of horizontal scanning lines step by step.
The GOA (Gate Driver on Array) technology is a driving method that can use the Array process of the liquid crystal display panel to fabricate the Gate driving circuit on the TFT Array substrate to scan the Gate line by line. Several clock signals are generally required to be accessed in the GOA circuit to realize the function of scanning the gate line by line. In the related art, an initial clock signal is generally output by a timing controller (Tcon) and transmitted to a level shifter (level shifter), and the level shifter boosts the clock signal and outputs the boosted clock signal to a GOA circuit of a liquid crystal display panel. Because the clock signal wiring inside the GOA is more, because of the process, short circuit easily occurs, in order to prevent the liquid crystal display panel from being burnt out, a structure with an over-current protection (OCP) function is arranged aiming at the clock signal wiring, however, in order to eliminate the brightness unevenness (mura), in the prior art, the time schedule controller can stop outputting the initial clock signal in a short time, so as to reset the clock signal, because the time for stopping outputting the initial clock signal is shorter, the liquid crystal display panel can not completely discharge in the process, at the moment, the time schedule controller can output the initial clock signal again, the current on the clock signal wiring can be overlarge, and the over-current protection is triggered, however, at the moment, the clock signal wiring is not short-circuited, and the over-current protection is triggered by mistake.
Disclosure of Invention
The present invention is directed to a liquid crystal display panel driving circuit, which can effectively avoid the false triggering of over-current protection due to the reset of a timing controller.
Another objective of the present invention is to provide a method for driving a liquid crystal display panel, which can effectively avoid the false triggering of the over-current protection due to the reset of the timing controller.
In order to achieve the above object, the present invention first provides a driving circuit for a liquid crystal display panel, including a timing controller, a level converting unit electrically connected to the timing controller, and a control signal generating unit electrically connected to both the timing controller and the level converting unit;
the working mode of the liquid crystal display panel driving circuit comprises a reset mode;
the time schedule controller is used for outputting a reset signal to the control signal generating unit in a reset mode;
the control signal generating unit is used for receiving a reset signal in a reset mode and generating a corresponding control signal to be output to the level conversion unit;
the level conversion unit is used for outputting a constant voltage high potential to a GOA circuit of the liquid crystal display panel under the control of a control signal in a reset mode.
The working mode of the liquid crystal display panel driving circuit also comprises a driving mode;
the time schedule controller outputs an initial clock signal to the level conversion unit in a driving mode and outputs a working signal to the control signal generation unit;
the control signal generating unit receives the working signal in a driving mode and generates a corresponding control signal to output to the level conversion unit;
the level conversion unit receives the initial clock signal in the driving mode to process the initial clock signal, and outputs the processed clock signal to a GOA circuit of the liquid crystal display panel under the control of the control signal.
The control signal generating unit includes: the circuit comprises a first field effect transistor, a second field effect transistor, a first resistor, a second resistor and a third resistor;
the grid electrode of the first field effect tube is electrically connected with the output end of the time sequence controller, the source electrode is grounded, and the drain electrode is electrically connected with the grid electrode of the second field effect tube;
the source electrode of the second field effect transistor is grounded, and the drain electrode is electrically connected with the control end of the level conversion unit for outputting the control signal to the level conversion unit so as to output the control signal to the level conversion unit;
the first end of the first resistor is electrically connected with the drain electrode of the second field effect transistor, and the second end of the first resistor is connected with a power supply voltage;
the first end of the second resistor is electrically connected with the drain electrode of the second field effect transistor, and the second end of the second resistor is grounded;
the first end of the third resistor is electrically connected with the drain electrode of the first field effect transistor, and the second end of the third resistor is connected with a first constant voltage.
The first field effect tube and the second field effect tube are both N-type field effect tubes.
In a driving mode, the time schedule controller outputs a working signal with high potential, and the control signal generating unit generates a control signal with high potential;
in the reset mode, the timing controller outputs a reset signal of a low potential, and the control signal generating unit generates a low potential control signal.
The first constant voltage is 3.3V.
The invention also provides a liquid crystal display panel driving method, which is applied to the liquid crystal display panel driving circuit and comprises the following steps:
step S1, the liquid crystal display panel driving circuit enters a reset mode, and the timing controller outputs a reset signal to the control signal generating unit;
step S2, the control signal generating unit receives the reset signal and generates a corresponding control signal to output to the level converting unit;
in step S3, the level shifter outputs a constant voltage high voltage to the GOA circuit of the liquid crystal display panel under the control of the control signal.
Further comprising:
step S4, the liquid crystal display panel driving circuit enters a driving mode, and the timing controller outputs a working signal to the control signal generating unit and outputs an initial clock signal to the level converting unit;
step S5, the control signal generating unit receives the working signal and generates a corresponding control signal to output to the level converting unit;
in step S6, the level shifter receives the initial clock signal and processes the initial clock signal, and outputs the processed clock signal to the GOA circuit of the liquid crystal display panel under the control of the control signal.
In the step S1, the timing controller outputs a reset signal of a low potential, and in the step S2, the control signal generating unit generates a low potential control signal;
in the step S4, the timing controller outputs a high-level operation signal, and in the step S5, the control signal generating unit generates a high-level control signal.
The invention has the beneficial effects that: the invention provides a liquid crystal display panel driving circuit, which comprises a time schedule controller, a level conversion unit and a control signal generation unit, wherein the working mode of the liquid crystal display panel driving circuit comprises a reset mode, in the reset mode, the time schedule controller outputs a reset signal to the control signal generation unit, the control signal generation unit receives the reset signal and generates a corresponding control signal to be output to the level conversion unit, and the level conversion unit outputs a constant voltage high potential to a GOA circuit of the liquid crystal display panel under the control of the control signal, so that the liquid crystal display panel can quickly discharge in the reset mode, and the phenomenon that the current on a clock signal wire in the GOA circuit is too high to trigger overcurrent protection after the liquid crystal display panel reenters the driving mode is avoided. According to the liquid crystal display panel driving method provided by the invention, the liquid crystal display panel is driven by adopting the liquid crystal display panel driving circuit, so that the phenomenon that overcurrent protection is triggered by mistake due to resetting of the time schedule controller can be effectively avoided.
Drawings
For a better understanding of the nature and technical aspects of the present invention, reference should be made to the following detailed description of the invention, taken in conjunction with the accompanying drawings, which are provided for purposes of illustration and description and are not intended to limit the invention.
In the drawings, there is shown in the drawings,
FIG. 1 is a diagram of a driving circuit of a liquid crystal display panel according to the present invention;
FIG. 2 is a flow chart of a driving method of a liquid crystal display panel according to the present invention;
FIG. 3 is a diagram illustrating steps S1-S3 of the driving method of the LCD panel according to the present invention;
fig. 4 is a schematic diagram of steps S4 to S6 of the liquid crystal display panel driving method of the present invention.
Detailed Description
To further illustrate the technical means and effects of the present invention, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.
Referring to fig. 1, the present invention provides a liquid crystal display panel driving circuit, including a timing controller 100, a level shifting unit 200 electrically connected to the timing controller 100, and a control signal generating unit 300 electrically connected to both the timing controller 100 and the level shifting unit 200;
the working mode of the liquid crystal display panel driving circuit comprises a driving mode and a resetting mode;
in the reset mode, the timing controller 100 outputs a reset signal to the control signal generating unit 300, the control signal generating unit 300 receives the reset signal and generates a corresponding control signal to output to the level shifting unit 200, and the level shifting unit 200 outputs a constant voltage high voltage VGH to the GOA circuit 21 of the liquid crystal display panel 20 under the control of the control signal;
in the driving mode, the timing controller 100 outputs a working signal to the control signal generating unit 300 and outputs an initial clock signal CK to the level shifter unit 200, the control signal generating unit 300 receives the working signal and generates a corresponding control signal to output to the level shifter unit 200, the level shifter unit 200 receives the initial clock signal CK to process the signal, and the control signal controls the signal to output a processed clock signal CK' to the GOA circuit 21 of the lcd panel 20.
Specifically, referring to fig. 1, the control signal generating unit 300 includes: the circuit comprises a first field effect transistor Q1, a second field effect transistor Q2, a first resistor R1, a second resistor R2 and a third resistor R3; the grid electrode of the first field effect transistor Q1 is electrically connected with the output end of the time schedule controller 100, the source electrode is grounded, and the drain electrode is electrically connected with the grid electrode of the second field effect transistor Q2; the source of the second field effect transistor Q2 is grounded, and the drain is electrically connected to the control terminal of the level shift unit 200 to output a control signal to the level shift unit 200; a first end of the first resistor R1 is electrically connected with the drain electrode of the second field-effect transistor Q2, and a second end is connected with a power supply voltage VCC; the first end of the second resistor R2 is electrically connected with the drain of the second field effect transistor Q2, and the second end is grounded; the first end of the third resistor R3 is electrically connected to the drain of the first FET Q1, and the second end is connected to a first constant voltage V1.
Specifically, taking the first fet Q1 and the second fet Q2 as N-type fets as an example, the operation of the liquid crystal display panel driving circuit of the present invention will be described as follows:
referring to fig. 3, in order to eliminate the brightness unevenness, the lcd panel driving circuit enters a reset mode, the timing controller 100 stops outputting the initial clock signal CK to the level shifter 200, the timing controller 100 outputs a low-potential reset signal to the gate of the first fet Q1 of the control signal generator 300, the first fet Q1 is turned off, the gate of the second fet Q2 is connected to the first constant voltage V1 having a voltage value of 3.3V, the second fet Q2 is turned on, the drain of the second fet Q2 is grounded and a low potential is written, so that the low-potential control signal output by the drain of the second fet Q2 is outputted, that is, the control signal is a low potential in the reset mode to the level shifter 200, the level shifter 200 is controlled by the low-potential control signal, and outputs a high potential VGH to the GOA circuit 21 of the lcd panel 20, the liquid crystal display panel 20 is enabled to discharge rapidly, and the current on the clock signal wiring in the GOA circuit 21 of the liquid crystal display panel 20 can be effectively prevented from being too high after the liquid crystal display panel enters the driving mode again, so that when the liquid crystal display panel is applied to driving the liquid crystal display panel with the overcurrent protection structure corresponding to the clock signal wiring, the overcurrent protection can be prevented from being triggered by mistake due to the resetting of a time schedule controller;
referring to fig. 4, the lcd panel driving circuit enters a driving mode, the timing controller 100 outputs an initial clock signal CK to the level shifter 200, the level shifter 200 processes the initial clock signal CK, and the timing controller 100 outputs a high-level working signal to the gate of the first fet Q1 of the control signal generator 300, the first fet Q1 is turned on, the gate of the second fet Q2 is grounded, and the second fet Q2 is turned off, so that the power voltage VCC is divided by the first resistor R1 and then a high level is written into the drain of the second fet Q2, and the drain of the second fet Q2 outputs a high-level control signal, i.e., the control signal is a high level and is output to the level shifter 200 in the driving mode, the level shifter 200 is controlled by the high-level control signal, and outputs the processed clock signal CK ', CK' to the GOA circuit 21 of the lcd panel 20, so as to realize the purpose of scanning the gate lines of the liquid crystal display panel 20 line by using the GOA circuit 21.
Referring to fig. 2 to 4 in combination with fig. 1, based on the same inventive concept, the present invention further provides a method for driving a liquid crystal display panel, which is applied to the liquid crystal display panel driving circuit, and includes the following steps:
in step S1, referring to fig. 3, the lcd panel driving circuit enters a reset mode, and the timing controller 100 outputs a reset signal to the control signal generating unit 300.
Specifically, in the step S1, the timing controller 100 outputs the low-level reset signal to the gate of the first fet Q1 of the control signal generating unit 300.
In step S2, please refer to fig. 3, the control signal generating unit 300 receives the reset signal and generates a corresponding control signal to output to the level shifting unit 200.
Specifically, in the step S2, after the gate of the first fet Q1 receives the low-level reset signal, the first fet Q1 is turned off, the gate of the second fet Q2 is connected to the first constant voltage V1 with the voltage value of 3.3V, and the second fet Q2 is turned on, at this time, the drain of the second fet Q2 is grounded and a low level is written in, so that the low-level control signal output by the drain of the second fet Q2, that is, the control signal is output to the level shifter 200 as a low level in the reset mode.
In step S3, referring to fig. 3, the level shifter 200 outputs a constant voltage high voltage VGH to the GOA circuit 21 of the lcd panel 20 under the control of the control signal.
Specifically, in step S3, the level conversion unit 200 is controlled by the low-level control signal to output a constant-voltage high-level VGH to the GOA circuit 21 of the liquid crystal display panel 20, so that the liquid crystal display panel 20 discharges quickly, and the current on the clock signal trace in the GOA circuit 21 of the liquid crystal display panel 20 after reentering the driving mode can be effectively prevented from being too high, so that when the level conversion unit is applied to driving the liquid crystal display panel provided with the overcurrent protection structure corresponding to the clock signal trace, the situation that the overcurrent protection is triggered by mistake due to the reset of the timing controller can be avoided.
In step S4, referring to fig. 4, the lcd panel driving circuit enters a driving mode, and the timing controller 100 outputs a working signal to the control signal generating unit 300 and outputs an initial clock signal CK to the level shifter unit 200.
Specifically, in the step S4, the timing controller 100 outputs a high-level operation signal to the gate of the first fet Q1 of the control signal generating unit 300.
In step S5, please refer to fig. 4, the control signal generating unit 300 receives the working signal and generates a corresponding control signal to output to the level shifting unit 200.
Specifically, in the step S5, after the gate of the first fet Q1 receives the high-level working signal, the first fet Q1 is turned on, the gate of the second fet Q2 is grounded, and the second fet Q2 is turned off, at this time, the power supply voltage VCC is divided by the first resistor R1, and then the high level is written into the drain of the second fet Q2, so that the drain of the second fet Q2 outputs the high-level control signal, that is, the control signal is the high level and is output to the level shifter unit 200 in the driving mode.
In step S6, referring to fig. 4, the level shifter 200 receives the initial clock signal CK, processes the initial clock signal CK, and outputs the processed clock signal CK' to the GOA circuit 21 of the lcd panel 20 under the control of the control signal.
Specifically, in step S6, the level shift unit 200 is controlled by the high-level control signal to output the processed clock signal CK' to the GOA circuit 21 of the liquid crystal display panel 20, so as to scan the gate lines of the liquid crystal display panel 20 line by using the GOA circuit 21.
In summary, the liquid crystal display panel driving circuit of the present invention includes a timing controller, a level conversion unit, and a control signal generation unit, wherein the working mode of the liquid crystal display panel driving circuit includes a reset mode, in the reset mode, the timing controller outputs a reset signal to the control signal generation unit, the control signal generation unit receives the reset signal and generates a corresponding control signal to output to the level conversion unit, and the level conversion unit outputs a constant voltage high potential to a GOA circuit of the liquid crystal display panel under the control of the control signal, so that the liquid crystal display panel can discharge rapidly in the reset mode, and the current on the clock signal trace in the GOA circuit is prevented from being too high to trigger the overcurrent protection after the liquid crystal display panel enters the driving mode again. According to the liquid crystal display panel driving method, the liquid crystal display panel driving circuit is adopted to drive the liquid crystal display panel, and the phenomenon that overcurrent protection is triggered by mistake due to resetting of the time schedule controller can be effectively avoided.
As described above, it will be apparent to those skilled in the art that various other changes and modifications can be made based on the technical solution and the technical idea of the present invention, and all such changes and modifications should fall within the protective scope of the appended claims.
Claims (8)
1. The liquid crystal display panel driving circuit is characterized by comprising a time schedule controller (100), a level conversion unit (200) electrically connected with the time schedule controller (100), and a control signal generating unit (300) electrically connected with the time schedule controller (100) and the level conversion unit (200);
the working mode of the liquid crystal display panel driving circuit comprises a reset mode;
the timing controller (100) is used for outputting a reset signal to the control signal generating unit (300) in a reset mode;
the control signal generating unit (300) is used for receiving a reset signal in a reset mode and generating a corresponding control signal to be output to the level conversion unit (200);
the level conversion unit (200) is used for outputting a constant voltage high potential (VGH) to a GOA circuit (21) of the liquid crystal display panel (20) under the control of a control signal in a reset mode;
the control signal generation unit (300) includes: the circuit comprises a first field effect transistor (Q1), a second field effect transistor (Q2), a first resistor (R1), a second resistor (R2) and a third resistor (R3);
the grid electrode of the first field effect transistor (Q1) is electrically connected with the output end of the time schedule controller (100), the source electrode is grounded, and the drain electrode is electrically connected with the grid electrode of the second field effect transistor (Q2);
the source electrode of the second field effect transistor (Q2) is grounded, and the drain electrode is electrically connected with the control end of the level conversion unit (200) so as to output a control signal to the level conversion unit (200);
the first end of the first resistor (R1) is electrically connected with the drain electrode of the second field effect transistor (Q2), and the second end is connected with a power supply Voltage (VCC);
the first end of the second resistor (R2) is electrically connected with the drain electrode of the second field effect transistor (Q2), and the second end is grounded;
the first end of the third resistor (R3) is electrically connected with the drain electrode of the first field effect transistor (Q1), and the second end is connected with a first constant voltage (V1).
2. The liquid crystal display panel drive circuit according to claim 1,
the working mode of the liquid crystal display panel driving circuit also comprises a driving mode;
the timing controller (100) outputs an initial clock signal (CK) to the level conversion unit (200) in the driving mode, and outputs a working signal to the control signal generation unit (300);
the control signal generating unit (300) receives the working signal in the driving mode and generates a corresponding control signal to output to the level converting unit (200);
the level conversion unit (200) receives and processes the initial clock signal (CK) in the driving mode, and outputs the processed clock signal (CK') to a GOA circuit (21) of the liquid crystal display panel (20) under the control of the control signal.
3. The liquid crystal display panel driving circuit according to claim 1, wherein the first field effect transistor (Q1) and the second field effect transistor (Q2) are N-type field effect transistors.
4. The liquid crystal display panel driving circuit according to claim 2, wherein in the driving mode, the timing controller (100) outputs an operation signal of a high potential, and the control signal generating unit (300) generates a control signal of the high potential;
in a reset mode, the timing controller (100) outputs a reset signal of a low potential, and the control signal generating unit (300) generates a low potential control signal.
5. The liquid crystal display panel drive circuit according to claim 3, wherein the first constant voltage (V1) is 3.3V.
6. A liquid crystal display panel driving method applied to the liquid crystal display panel driving circuit according to any one of claims 1 to 5, comprising the steps of:
step S1, the liquid crystal display panel driving circuit enters a reset mode, and the timing controller (100) outputs a reset signal to the control signal generating unit (300);
step S2, the control signal generating unit (300) receives the reset signal and generates a corresponding control signal to output to the level converting unit (200);
in step S3, the level shifter 200 outputs a constant voltage high potential VGH to the GOA circuit 21 of the liquid crystal display panel 20 under the control of the control signal.
7. The liquid crystal panel display driving method according to claim 6, further comprising:
step S4, the liquid crystal display panel driving circuit enters a driving mode, the timing controller (100) outputs a working signal to the control signal generating unit (300) and outputs an initial clock signal (CK) to the level shifting unit (200);
step S5, the control signal generating unit (300) receives the working signal and generates a corresponding control signal to output to the level converting unit (200);
in step S6, the level shifter 200 receives the initial clock signal (CK), processes the initial clock signal, and outputs the processed clock signal (CK') to the GOA circuit 21 of the liquid crystal display panel 20 under the control of the control signal.
8. The liquid crystal panel display driving method according to claim 7,
in the step S1, the timing controller (100) outputs a reset signal of a low potential, and in the step S2, the control signal generation unit (300) generates a low potential control signal;
in the step S4, the timing controller (100) outputs an operation signal of a high potential, and in the step S5, the control signal generating unit (300) generates a control signal of the high potential.
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| CN108538267B (en) * | 2018-04-20 | 2020-08-04 | 昆山龙腾光电股份有限公司 | Drive circuit and liquid crystal display device |
| CN109064982B (en) * | 2018-08-06 | 2020-04-28 | 深圳市华星光电技术有限公司 | GOA circuit driving system, GOA circuit driving method and display device |
| CN110120196B (en) * | 2019-04-04 | 2021-05-07 | 深圳市华星光电半导体显示技术有限公司 | Level conversion control circuit and array substrate driving circuit |
| CN110085188B (en) * | 2019-05-05 | 2021-10-08 | 京东方科技集团股份有限公司 | Level conversion device of display panel, control method thereof and display panel |
| CN111028756B (en) * | 2019-12-17 | 2023-10-13 | Tcl华星光电技术有限公司 | display panel |
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| CN1397060A (en) * | 2000-10-05 | 2003-02-12 | 皇家菲利浦电子有限公司 | Bistable chiral nematic liquid crystal display and method of driving the same |
| US7358685B2 (en) * | 2005-05-18 | 2008-04-15 | Samsung Electro-Mechanics Co., Ltd. | DC-DC converter having protective function of over-voltage and over-current and led driving circuit using the same |
| CN105048775A (en) * | 2015-08-13 | 2015-11-11 | 浪潮集团有限公司 | Power source device, power source system and power supply method |
| CN105448260A (en) * | 2015-12-29 | 2016-03-30 | 深圳市华星光电技术有限公司 | Overcurrent protection circuit and liquid crystal display |
| CN105551447A (en) * | 2016-02-18 | 2016-05-04 | 深圳市华星光电技术有限公司 | GOA circuit and liquid crystal display device |
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| CN107516502A (en) | 2017-12-26 |
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Address after: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Patentee after: TCL China Star Optoelectronics Technology Co.,Ltd. Address before: 9-2 Tangming Avenue, Guangming New District, Shenzhen City, Guangdong Province Patentee before: Shenzhen China Star Optoelectronics Technology Co.,Ltd. |