CN107516502A - Liquid crystal display panel drive circuit and driving method - Google Patents
Liquid crystal display panel drive circuit and driving method Download PDFInfo
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- CN107516502A CN107516502A CN201710948939.4A CN201710948939A CN107516502A CN 107516502 A CN107516502 A CN 107516502A CN 201710948939 A CN201710948939 A CN 201710948939A CN 107516502 A CN107516502 A CN 107516502A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The present invention provides a kind of liquid crystal display panel drive circuit and driving method.The liquid crystal display panel drive circuit includes time schedule controller, level conversion unit, and control signal generation unit, the mode of operation of the liquid crystal display panel drive circuit includes replacement pattern, under replacement pattern, time schedule controller exports reset signal to control signal generation unit, control signal corresponding to control signal generation unit reception reset signal and generation is exported to level conversion unit, GOA circuit output constant pressure high potential of the control of level conversion unit suspension control signal to liquid crystal display panel, enable the liquid crystal display panel repid discharge under replacement pattern, avoid reentering the too high triggering overcurrent protection of electric current on clock signal cabling after drive pattern.
Description
Technical field
The present invention relates to technical field of liquid crystal display, more particularly to a kind of liquid crystal display panel drive circuit and driving side
Method.
Background technology
With the development of Display Technique, the plane such as liquid crystal display device (Liquid Crystal Display, LCD) is shown
Device is because having the advantages that high image quality, power saving, fuselage is thin and has a wide range of application, and is widely used in mobile phone, TV, individual
The various consumption electronic products such as digital assistants, digital camera, notebook computer, desktop computer, turn into display device
Main flow.
In active liquid crystal display device, each pixel is electrically connected with a thin film transistor (TFT) (TFT), thin film transistor (TFT)
Grid (Gate) is connected to horizontal scanning line, and source electrode (Source) is connected to the data wire of vertical direction, and drain electrode (Drain) then connects
It is connected to pixel electrode.Apply enough voltage on horizontal scanning line, can be electrically connected on this horizontal scanning line
All TFT are opened, so as to the signal voltage on data wire can writing pixel, control different light transmittances and then the control of liquid crystal
Color processed and the effect of brightness.The driving of current active liquid crystal display panel horizontal scanning line is mainly by external integrated circuit
Plate (Integrated Circuit, IC) is completed, and external IC can control the charging step by step of horizontal scanning lines at different levels and put
Electricity.
It is that can use liquid crystal and GOA technologies (Gate Driver on Array) are array base palte row actuation techniques
Show that gate driving circuit is produced on tft array substrate by the array process of panel, realize the driving side to grid progressive scan
Formula.Some clock signals of access are generally required in GOA circuits, to realize the function of its grid progressive scan.In the prior art, lead to
Often initial clock signal is exported using time schedule controller (Tcon) and transmit to level conversion unit (level shifter),
In the GOA circuits that clock signal after boosting is exported to liquid crystal display panel after being boosted by level conversion unit.Due to GOA
Internal clock signal cabling is more, due to processing procedure, short circuit easily occurs, in order to prevent that liquid crystal display panel from being burnt
It is bad, clock signal cabling can be directed to the structure with overcurrent protection (OCP) function is set, however, to eliminate brightness disproportionation
(mura) time schedule controller, can be made to stop exporting initial clock signal in a short time in the prior art, to enter to clock signal
Row is reset, and because the time for stopping output initial clock signal is shorter, liquid crystal display panel can not discharge completely during being somebody's turn to do, this
Seasonal time schedule controller exports initial clock signal again, and the electric current on clock signal cabling can be made excessive, triggers over current protection
Shield, however, now not short circuit between clock signal cabling, namely false triggering overcurrent protection.
The content of the invention
It is an object of the invention to provide a kind of liquid crystal display panel drive circuit, can effectively avoid because of time schedule controller
False triggering overcurrent protection caused by replacement.
Another object of the present invention is to provide a kind of driving method for liquid crystal display panel, can effectively avoid because of sequential control
System, which is thought highly of, puts caused false triggering overcurrent protection.
To achieve the above object, present invention firstly provides a kind of liquid crystal display panel drive circuit, including time schedule controller,
The level conversion unit and electrical with the time schedule controller and level conversion unit being electrically connected with the time schedule controller
The control signal generation unit of connection；
The mode of operation of the liquid crystal display panel drive circuit includes replacement pattern；
The time schedule controller is used to export reset signal to control signal generation unit under replacement pattern；
The control signal generation unit is used to receive control signal corresponding to reset signal and generation under replacement pattern
Export to level conversion unit；
The level conversion unit is used for the control of the suspension control signal under replacement pattern to the GOA electricity of liquid crystal display panel
Road exports constant pressure high potential.
The mode of operation of the liquid crystal display panel drive circuit also includes drive pattern；
The time schedule controller exports initial clock signal to level conversion unit in the drive mode, and to control signal
Generation unit output services signal；
The control signal generation unit receives working signal, and control signal output corresponding to generation in the drive mode
To level conversion unit；
The level conversion unit receives initial clock signal and it is handled in the drive mode, and suspension control signal
GOA circuit outputs from control to liquid crystal display panel processing after clock signal.
The control signal generation unit includes：First FET, the second FET, first resistor, second resistance,
3rd resistor；
The grid of first FET is electrically connected with the output end of time schedule controller, source ground, and drain electrode electrically connects
Connect the grid of the second FET；
The source ground of second FET, drain electrode are electrically connected with level conversion unit to its output control signal
Control terminal, with to level conversion unit output control signal；
The first end of the first resistor is electrically connected with the drain electrode of the second FET, and second terminates into supply voltage；
The first end of the second resistance is electrically connected with the drain electrode of the second FET, the second end ground connection；
The first end of the 3rd resistor is electrically connected with the drain electrode of the first FET, and second terminates into the first constant electricity
Pressure.
First FET and the second FET are N-type FET.
In the drive mode, the working signal of the time schedule controller output high potential, the control signal generation unit
Produce the control signal of high potential；
Under replacement pattern, the reset signal of the time schedule controller output low potential, the control signal generation unit
Produce low potential control signal.
First constant voltage is 3.3V.
The present invention also provides a kind of driving method for liquid crystal display panel, applied to above-mentioned liquid crystal display panel drive circuit,
Comprise the following steps：
Step S1, described liquid crystal display panel drive circuit enters replacement pattern, and the time schedule controller is to control signal
Generation unit exports reset signal；
Step S2, control signal corresponding to described control signal generation unit reception reset signal and generation is exported to level
Converting unit；
Step S3, the control of described level conversion unit suspension control signal is permanent to the GOA circuit outputs of liquid crystal display panel
Press high potential.
Also include：
Step S4, described liquid crystal display panel drive circuit enters drive pattern, and the time schedule controller is to control signal
Generation unit output services signal, and export initial clock signal to level conversion unit；
Step S5, control signal corresponding to described control signal generation unit reception working signal and generation is exported to level
Converting unit；
Step S6, described level conversion unit receives initial clock signal and it is handled, and the control of suspension control signal
Make to the clock signal after the GOA circuit outputs processing of liquid crystal display panel.
In the step S1, the reset signal of time schedule controller output low potential, in the step S2, the control
Signal generation unit produces low potential control signal；
In the step S4, the working signal of time schedule controller output high potential, in the step S5, the control
Signal generation unit produces the control signal of high potential.
Beneficial effects of the present invention：A kind of liquid crystal display panel drive circuit provided by the invention, including time schedule controller,
Level conversion unit and control signal generation unit, the mode of operation of the liquid crystal display panel drive circuit include replacement pattern,
Under replacement pattern, time schedule controller exports reset signal to control signal generation unit, and control signal generation unit receives weight
Confidence number and control signal corresponding to producing is exported to level conversion unit, the control of level conversion unit suspension control signal is to liquid
The GOA circuit output constant pressure high potentials of LCD panel, enable the liquid crystal display panel repid discharge under replacement pattern, avoid
The too high triggering overcurrent protection of electric current reentered on the clock signal cabling after drive pattern in GOA circuits.The present invention carries
A kind of driving method for liquid crystal display panel supplied, is driven using above-mentioned liquid crystal display panel drive circuit to liquid crystal display panel
It is dynamic, it can effectively avoid the false triggering overcurrent protection caused by time schedule controller is reset.
Brief description of the drawings
In order to be further understood that the feature of the present invention and technology contents, refer to below in connection with the detailed of the present invention
Illustrate and accompanying drawing, however accompanying drawing only provide with reference to and explanation use, be not used for being any limitation as the present invention.
In accompanying drawing,
Fig. 1 is the structure chart of the liquid crystal display panel drive circuit of the present invention；
Fig. 2 is the flow chart of the driving method for liquid crystal display panel of the present invention；
Fig. 3 is the step S1 to S3 of the driving method for liquid crystal display panel of present invention schematic diagram；
Fig. 4 is the step S4 to S6 of the driving method for liquid crystal display panel of present invention schematic diagram.
Embodiment
Further to illustrate the technological means and its effect of the invention taken, below in conjunction with being preferable to carry out for the present invention
Example and its accompanying drawing are described in detail.
Referring to Fig. 1, the present invention provides a kind of liquid crystal display panel drive circuit, including time schedule controller 100, with it is described
Time schedule controller 100 be electrically connected with level conversion unit 200 and with the time schedule controller 100 and level conversion unit 200
The control signal generation unit 300 being electrically connected with；
Wherein, the mode of operation of the liquid crystal display panel drive circuit includes drive pattern and resets pattern；
Under replacement pattern, the time schedule controller 100 exports reset signal to control signal generation unit 300, described
Control signal corresponding to the reception reset signal of control signal generation unit 300 and generation is exported to level conversion unit 200, described
The control of the suspension control signal of level conversion unit 200 exports constant pressure high potential VGH to the GOA circuits 21 of liquid crystal display panel 20；
In the drive mode, the time schedule controller 100 is to the output services signal of control signal generation unit 300, and to
Level conversion unit 200 exports initial clock signal CK, and the control signal generation unit 300 receives working signal and generation pair
The control signal answered is exported to level conversion unit 200, and the level conversion unit 200 receives initial clock signal CK and it is entered
Row processing, and the clock signal CK ' after the output of GOA circuits 21 processing of the control of suspension control signal to liquid crystal display panel 20.
Specifically, referring to Fig. 1, the control signal generation unit 300 includes：First FET Q1, second effect
Should pipe Q2, first resistor R1, second resistance R2,3rd resistor R3；The grid of the first FET Q1 is electrically connected with sequential
The output end of controller 100, source ground, drain electrode are electrically connected with the second FET Q2 grid；Second FET
Q2 source ground, drain electrode are electrically connected with the control terminal of level conversion unit 200, with to the output control of level conversion unit 200
Signal；The first end of the first resistor R1 is electrically connected with the second FET Q2 drain electrode, and second terminates into supply voltage
VCC；The first end of the second resistance R2 is electrically connected with the second FET Q2 drain electrode, the second end ground connection；3rd electricity
The first end for hindering R3 is electrically connected with the first FET Q1 drain electrode, and second terminates into the first constant voltage V1.
Specifically, so that the first FET Q1 and the second FET Q2 are N-type FET as an example, to this
The course of work of the liquid crystal display panel drive circuit of invention is described：
Incorporated by reference to Fig. 3, in order to eliminate brightness disproportionation, the liquid crystal display panel drive circuit enters replacement pattern, described
Time schedule controller 100 stop to level conversion unit 200 export initial clock signal CK, while time schedule controller 100 export it is low
The reset signal of current potential to the first FET Q1 of control signal generation unit 300 grid, the first FET Q1 close,
The first constant voltage V1, the second FET Q2 opening that second FET Q2 grid access magnitude of voltage is 3.3V, now
Second FET Q2 grounded drains and write low potential, and make the second FET Q2 drain electrode output low potential control
Signal, namely control signal is that low potential is exported to level conversion unit 200, the level conversion unit in replacement pattern
200 are controlled by the control signal of low potential, are exported constant pressure high potential VGH to the GOA circuits 21 of liquid crystal display panel 20, are made liquid
The repid discharge of LCD panel 20, it can effectively avoid reentering the GOA circuits 21 of liquid crystal display panel 20 after drive pattern
In clock signal cabling on electric current it is too high, so as to be provided with overcurrent protection knot applied to the corresponding clock signal cabling of driving
During the liquid crystal display panel of structure, it can avoid causing false triggering overcurrent protection because time schedule controller is reset；
Referring to Fig. 4, the liquid crystal display panel drive circuit enters drive pattern, the time schedule controller 100 is to electricity
Flat converting unit 200 exports initial clock signal CK, and level conversion unit 200 is by initial clock signal CK processing, simultaneously
Time schedule controller 100 export high potential working signal to control signal generation unit 300 the first FET Q1 grid,
First FET Q1 is opened, the second FET Q2 grounded-grid, and the second FET Q2 is closed, now supply voltage
High potential is write the second FET Q2 drain electrodes by VCC after first resistor R1 partial pressures, and makes the second FET Q2 drain electrode
The control signal of high potential is exported, namely control signal is that high potential is exported to level conversion unit 200, institute in drive pattern
State level conversion unit 200 to be controlled by the control signal of high potential, the output of GOA circuits 21 processing to liquid crystal display panel 20
Clock signal CK ' afterwards, to realize the purpose progressively scanned using GOA circuits 21 to the gate line of liquid crystal display panel 20.
Fig. 2 is referred to Fig. 4, and combines Fig. 1, based on same inventive concept, the present invention also provides a kind of LCD
Plate driving method, applied to above-mentioned liquid crystal display panel drive circuit, comprise the following steps：
Step S1, referring to Fig. 3, the liquid crystal display panel drive circuit enters replacement pattern, the time schedule controller
100 export reset signal to control signal generation unit 300.
Specifically, in the step S1, reset signal to the control signal that time schedule controller 100 exports low potential produces list
First FET Q1 of member 300 grid.
Step S2, referring to Fig. 3, the control signal generation unit 300 receives reset signal and produces corresponding control
Signal output is to level conversion unit 200.
Specifically, in the step S2, the first FET Q1 grid is after the reset signal of low potential is received, and
One FET Q1 is closed, the first constant voltage V1 that the second FET Q2 grid access magnitude of voltage is 3.3V, second
Effect pipe Q2 is opened, now the second FET Q2 grounded drains and write low potential, and make the second FET Q2 drain electrode
The control signal of the low potential of output, namely control signal is that low potential is exported to level conversion unit 200 in replacement pattern.
Step S3, referring to Fig. 3, the control of the suspension control signal of the level conversion unit 200 is to liquid crystal display panel 20
GOA circuits 21 export constant pressure high potential VGH.
Specifically, in the step S3, the level conversion unit 200 is controlled by the control signal of low potential, to liquid
The GOA circuits 21 of LCD panel 20 export constant pressure high potential VGH, make the repid discharge of liquid crystal display panel 20, can effectively keep away
The electric current for exempting to reenter on the clock signal cabling after drive pattern in the GOA circuits 21 of liquid crystal display panel 20 is too high, from
And when the corresponding clock signal cabling of driving is provided with the liquid crystal display panel of over-current protection structure, it can avoid because of sequential
Controller, which is reset, causes false triggering overcurrent protection.
Step S4, referring to Fig. 4, the liquid crystal display panel drive circuit enters drive pattern, the time schedule controller
100 to the output services signal of control signal generation unit 300, and exports initial clock signal CK to level conversion unit 200.
Specifically, in the step S4, working signal to the control signal that the time schedule controller 100 exports high potential is produced
First FET Q1 of raw unit 300 grid.
Step S5, referring to Fig. 4, the control signal generation unit 300 receives working signal and produces corresponding control
Signal output is to level conversion unit 200.
Specifically, in the step S5, the first FET Q1 grid is after the working signal of high potential is received, and
One FET Q1 is opened, the second FET Q2 grounded-grid, and the second FET Q2 is closed, now supply voltage VCC
High potential is write into the second FET Q2 drain electrodes after first resistor R1 partial pressures, and exports the second FET Q2 drain electrode
The control signal of high potential, namely control signal is that high potential is exported to level conversion unit 200 in drive pattern.
Step S6, referring to Fig. 4, the reception of the level conversion unit 200 initial clock signal CK is handled it, and
Clock signal CK ' after the output of GOA circuits 21 processing of from the control of suspension control signal to liquid crystal display panel 20.
Specifically, in the step S6, the level conversion unit 200 is controlled by the control signal of high potential, to liquid
Clock signal CK ' after the output of GOA circuits 21 processing of LCD panel 20, to realize using GOA circuits 21 to liquid crystal display
The purpose of the gate line progressive scan of panel 20.
In summary, liquid crystal display panel drive circuit of the invention, including time schedule controller, level conversion unit and
Control signal generation unit, the mode of operation of the liquid crystal display panel drive circuit includes replacement pattern, under replacement pattern, when
Sequence controller exports reset signal to control signal generation unit, and control signal generation unit receives reset signal and produced correspondingly
Control signal export to level conversion unit, the GOA of the control of level conversion unit suspension control signal to liquid crystal display panel
Circuit output constant pressure high potential, enable the liquid crystal display panel repid discharge under replacement pattern, avoid reentering driving mould
The too high triggering overcurrent protection of electric current after formula in GOA circuits on clock signal cabling.The liquid crystal display panel driving of the present invention
Method, liquid crystal display panel is driven using above-mentioned liquid crystal display panel drive circuit, can effectively avoided because of sequential control
System, which is thought highly of, puts caused false triggering overcurrent protection.
It is described above, for the person of ordinary skill of the art, can be with technique according to the invention scheme and technology
Other various corresponding changes and deformation are made in design, and all these changes and deformation should all belong to the appended right of the present invention
It is required that protection domain.
Claims (9)
1. a kind of liquid crystal display panel drive circuit, it is characterised in that including time schedule controller (100) and the SECO
Device (100) be electrically connected with level conversion unit (200) and with the time schedule controller (100) and level conversion unit (200)
The control signal generation unit (300) being electrically connected with；
The mode of operation of the liquid crystal display panel drive circuit includes replacement pattern；
The time schedule controller (100) is used to export reset signal to control signal generation unit (300) under replacement pattern；
The control signal generation unit (300) is used to receive control signal corresponding to reset signal and generation under replacement pattern
Export to level conversion unit (200)；
The level conversion unit (200) is used for the control of the suspension control signal under replacement pattern to liquid crystal display panel (20)
GOA circuits (21) output constant pressure high potential (VGH).
2. liquid crystal display panel drive circuit as claimed in claim 1, it is characterised in that
The mode of operation of the liquid crystal display panel drive circuit also includes drive pattern；
The time schedule controller (100) exports initial clock signal (CK) to level conversion unit (200) in the drive mode, and
To control signal generation unit (300) output services signal；
The control signal generation unit (300) receives working signal in the drive mode, and control signal corresponding to generation is defeated
Go out to level conversion unit (200)；
The level conversion unit (200) receives initial clock signal (CK) and it is handled in the drive mode, and controlled
Clock signal (CK ') after GOA circuits (21) output processing of from the control of signal processed to liquid crystal display panel (20).
3. liquid crystal display panel drive circuit as claimed in claim 2, it is characterised in that the control signal generation unit
(300) include：First FET (Q1), the second FET (Q2), first resistor (R1), second resistance (R2), the 3rd electricity
Hinder (R3)；
The grid of first FET (Q1) is electrically connected with the output end of time schedule controller (100), source ground, drain electrode electricity
Property connection the second FET (Q2) grid；
The source ground of second FET (Q2), drain electrode be electrically connected with level conversion unit (200) control terminal, with to
Level conversion unit (200) output control signal；
The first end of the first resistor (R1) is electrically connected with the drain electrode of the second FET (Q2), and second terminates into supply voltage
(VCC)；
The first end of the second resistance (R2) is electrically connected with the drain electrode of the second FET (Q2), the second end ground connection；
The first end of the 3rd resistor (R3) is electrically connected with the drain electrode of the first FET (Q1), second terminate it is constant into first
Voltage (V1).
4. liquid crystal display panel drive circuit as claimed in claim 3, it is characterised in that first FET (Q1),
And second FET (Q2) be N-type FET.
5. liquid crystal display panel drive circuit as claimed in claim 4, it is characterised in that in the drive mode, the sequential
Controller (100) exports the working signal of high potential, and the control signal generation unit (300) produces the control letter of high potential
Number；
Under replacement pattern, the reset signal of time schedule controller (100) the output low potential, the control signal generation unit
(300) low potential control signal is produced.
6. liquid crystal display panel drive circuit as claimed in claim 4, it is characterised in that first constant voltage (V1) is
3.3V。
7. a kind of driving method for liquid crystal display panel, driven applied to the liquid crystal display panel as described in any one of claim 1 to 6
Dynamic circuit, it is characterised in that comprise the following steps：
Step S1, described liquid crystal display panel drive circuit enters replacement pattern, and the time schedule controller (100) is to control signal
Generation unit (300) exports reset signal；
Step S2, control signal corresponding to described control signal generation unit (300) reception reset signal and generation is exported to electricity
Flat converting unit (200)；
Step S3, GOA circuit of the control of described level conversion unit (200) suspension control signal to liquid crystal display panel (20)
(21) constant pressure high potential (VGH) is exported.
8. liquid crystal panel display drive method as claimed in claim 7, it is characterised in that also include：
Step S4, described liquid crystal display panel drive circuit enters drive pattern, and the time schedule controller (100) is to control signal
Generation unit (300) output services signal, and export initial clock signal (CK) to level conversion unit (200)；
Step S5, control signal corresponding to described control signal generation unit (300) reception working signal and generation is exported to electricity
Flat converting unit (200)；
Step S6, described level conversion unit (200) receives initial clock signal (CK) and it is handled, and suspension control signal
GOA circuits (21) output from control to liquid crystal display panel (20) processing after clock signal (CK ').
9. liquid crystal panel display drive method as claimed in claim 8, it is characterised in that
In the step S1, the reset signal of the time schedule controller (100) output low potential, in the step S2, the control
Signal generation unit (300) processed produces low potential control signal；
In the step S4, the working signal of the time schedule controller (100) output high potential, in the step S5, the control
Signal generation unit (300) processed produces the control signal of high potential.
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| CN201710948939.4A CN107516502B (en) | 2017-10-12 | 2017-10-12 | Liquid crystal display panel driving circuit and driving method |
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| CN201710948939.4A CN107516502B (en) | 2017-10-12 | 2017-10-12 | Liquid crystal display panel driving circuit and driving method |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108538267A (en) * | 2018-04-20 | 2018-09-14 | 昆山龙腾光电有限公司 | Driving circuit and liquid crystal display device |
| CN109064982A (en) * | 2018-08-06 | 2018-12-21 | 深圳市华星光电技术有限公司 | GOA circuit driving system and GOA circuit drive method and display device |
| CN110085188A (en) * | 2019-05-05 | 2019-08-02 | 京东方科技集团股份有限公司 | The level converter and its control method and display panel of display panel |
| CN111028756A (en) * | 2019-12-17 | 2020-04-17 | Tcl华星光电技术有限公司 | Display panel |
| WO2020199553A1 (en) * | 2019-04-04 | 2020-10-08 | 深圳市华星光电半导体显示技术有限公司 | Level shift control circuit and level shift circuit |
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| CN109064982A (en) * | 2018-08-06 | 2018-12-21 | 深圳市华星光电技术有限公司 | GOA circuit driving system and GOA circuit drive method and display device |
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| CN110085188B (en) * | 2019-05-05 | 2021-10-08 | 京东方科技集团股份有限公司 | Level conversion device of display panel, control method thereof and display panel |
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| CN111028756B (en) * | 2019-12-17 | 2023-10-13 | Tcl华星光电技术有限公司 | display panel |
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