CN110085188B - Level conversion device of display panel, control method thereof and display panel - Google Patents
Level conversion device of display panel, control method thereof and display panel Download PDFInfo
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- CN110085188B CN110085188B CN201910368633.0A CN201910368633A CN110085188B CN 110085188 B CN110085188 B CN 110085188B CN 201910368633 A CN201910368633 A CN 201910368633A CN 110085188 B CN110085188 B CN 110085188B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
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Abstract
The invention provides a level conversion device of a display panel, a control method thereof and the display panel, wherein the device comprises: a plurality of level shifting modules, wherein each level shifting module comprises: the input end of the level shifter is electrically connected with the corresponding signal output end in the time sequence control chip, and when the power supply end of the level shifter is connected with a first power supply, the level shifter receives a signal to be converted output by the corresponding signal output end and converts and amplifies the signal to be converted; and the control circuit is electrically connected with the power end of the level converter and the first power supply respectively, and is used for controlling the power end of the level converter to be connected with the first power supply when acquiring the reset completion signal of the time sequence control chip. Therefore, the phenomenon that a plurality of signals to be converted are simultaneously pulled high due to the unstable state of the GPO port before the resetting of the time sequence control chip is completed can be avoided, and the bad phenomenon of starting up and screen blacking caused by PMIC (Power management Integrated Circuit) load extraction protection is avoided.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a level shifter of a display panel, and a control method of a level shifter of a display panel.
Background
A display panel is widely used in various fields such as homes, workplaces, and the like as an output device capable of visually displaying electronic information. The display panel in the related art occasionally has a black screen phenomenon during power-on, but the related art does not provide an effective means for solving the problem of the black screen during power-on.
Disclosure of Invention
The inventor of the application finds out through research that: before the sequential control chip finishes the program downloading, some GPO (General-purpose output) ports are unknown, that is, the GPO ports may output high level or low level. When several signals are at high level, the signals may be pumped after being amplified by the level shifter, so that the Power Management IC (Power Management IC) may perform protection, thereby causing a poor black screen phenomenon during startup.
The present invention is directed to solving, at least to some extent, one of the technical problems in the related art.
Therefore, a first objective of the present invention is to provide a level shifting apparatus for a display panel to avoid the undesirable phenomenon of black screen when the display panel is turned on.
A second object of the present invention is to provide a display panel.
A third objective of the present invention is to provide a method for controlling a level shifter of a display panel.
To achieve the above object, a first embodiment of the present invention provides a level shifter for a display panel, including: a plurality of level shift modules, the level shift modules are respectively electrically connected with a plurality of signal output ends of a sequential control chip in the display panel, wherein each level shift module comprises: the input end of the level shifter is electrically connected with the corresponding signal output end in the time sequence control chip, and when the power end of the level shifter is connected with a first power supply, the level shifter receives a signal to be converted output by the corresponding signal output end and converts and amplifies the signal to be converted; and the control circuit is electrically connected with the power end of the level shifter and the first power supply respectively, and is used for controlling the power end of the level shifter to be connected with the first power supply when acquiring the reset completion signal of the sequential control chip.
According to the level conversion device of the display panel provided by the embodiment of the invention, when the control circuit acquires the reset completion signal of the time sequence control chip, the power end of the level converter is controlled to be connected with the first power supply, so that the level converter receives the signal to be converted output by the corresponding signal output end and converts and amplifies the signal to be converted. Therefore, the level conversion device of the display panel in the embodiment of the invention can prevent the phenomenon that a plurality of signals to be converted are simultaneously pulled high due to the unstable state of the GPO port before the resetting of the time sequence control chip is completed, and further can avoid the bad phenomenon of startup black screen due to PMIC (power management integrated circuit) load extraction protection.
According to an embodiment of the present invention, the control circuit is electrically connected to a reset signal terminal of the timing control chip, and generates the reset completion signal when a voltage of a reset signal at the reset signal terminal reaches a reference voltage, where the reference voltage is a voltage reached by the reset signal when the reset of the timing control chip is completed. According to one embodiment of the invention, the control circuit comprises: a first end of the controllable switch is electrically connected with the first power supply, and a second end of the controllable switch is electrically connected with a power supply end of the level shifter; the output end of the comparison sub-circuit is electrically connected with the control end of the controllable switch, the first input end of the comparison sub-circuit is electrically connected with the reset signal end of the time sequence control chip to receive the reset signal of the time sequence control chip, the second input end of the comparison sub-circuit is used for receiving the reference voltage, and the comparison sub-circuit is used for comparing the voltage of the reset signal with the reference voltage and controlling the controllable switch to be switched on when the voltage of the reset signal reaches the reference voltage.
According to one embodiment of the invention, the comparison sub-circuit comprises: the output end of the comparator is electrically connected with the control end of the controllable switch; one end of the first resistor is electrically connected with the positive input end of the comparator, the other end of the first resistor is electrically connected with one end of the second resistor, the other end of the first resistor is used for receiving a reset signal of the time sequence control chip, and the other end of the second resistor is grounded; the voltage regulator comprises a third resistor and a fourth resistor, wherein one end of the third resistor is electrically connected with one end of the fourth resistor, one end of the third resistor is also electrically connected with the negative input end of the comparator, the other end of the third resistor is electrically connected with the reference voltage setting end, and the other end of the fourth resistor is grounded.
According to an embodiment of the present invention, the number of the second resistor is one, wherein the plurality of level shift modules are electrically connected to one end of the second resistor, and the other end of the second resistor is grounded.
To achieve the above object, a second embodiment of the present invention provides a display panel, including the level shifting apparatus of the display panel according to the first embodiment of the present invention.
According to the display panel provided by the embodiment of the invention, the phenomenon that a plurality of signals to be converted are simultaneously pulled up due to the unstable state of the GPO port before the resetting of the time sequence control chip is completed can be prevented through the level conversion device of the display panel, and the bad phenomenon of starting up a black screen can be further avoided.
According to one embodiment of the invention, the level shifter is electrically connected with the timing control chip, and the level shifter is also electrically connected with the gate driving circuit.
In order to achieve the above object, a third embodiment of the present invention provides a method for controlling a level shifter of a display panel, where the level shifter includes a plurality of level shifting modules, the level shifting modules are electrically connected to a plurality of signal output terminals of a timing control chip in the display panel, each level shifting module includes a level shifter, an input terminal of the level shifter is electrically connected to a corresponding signal output terminal in the timing control chip, and when a power terminal of the level shifter is powered on by a first power supply, the level shifter receives a signal to be converted output from the corresponding signal output terminal and performs conversion amplification on the signal to be converted, and the method includes: acquiring a reset completion signal of the time sequence control chip; and controlling a power supply end of the level shifter to be connected with the first power supply.
According to the control method of the level shifter of the display panel provided by the embodiment of the invention, when the reset completion signal of the time sequence control chip is acquired, the power end of the level shifter is controlled to be connected with the first power supply. Therefore, the control method of the level conversion device of the display panel can prevent the phenomenon that a plurality of signals to be converted are simultaneously pulled up due to the unstable state of the GPO port before the resetting of the time sequence control chip is completed, and further can avoid the bad phenomenon of starting up a black screen.
According to an embodiment of the present invention, the acquiring the reset completion signal of the timing control chip includes: receiving a reset signal of a reset signal end of the time sequence control chip; generating the reset completion signal when a voltage of a reset signal of the reset signal terminal reaches a reference voltage; the reference voltage is the voltage reached by the reset signal when the time sequence control chip is reset.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The foregoing and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a block diagram of a level shifter of a display panel according to an embodiment of the present invention;
FIG. 2 is a schematic diagram illustrating an abnormal waveform of a level shifter of a display panel according to the related art;
FIG. 3 is a block diagram of a level shifting apparatus of a display panel according to an embodiment of the present invention;
FIG. 4 is a schematic circuit diagram of a level shifter of a display panel according to an embodiment of the present invention;
FIG. 5 is a waveform diagram illustrating a level shifting apparatus of a display panel according to an embodiment of the present invention;
FIG. 6 is a block diagram of a level shifter of a display panel according to another embodiment of the present invention;
FIG. 7 is a flowchart illustrating a method for controlling a level shifter of a display panel according to an embodiment of the present invention;
fig. 8 is a flowchart illustrating a method for controlling a level shifter of a display panel according to an embodiment of the invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
Before describing a level shifter of a display panel, a control method thereof, and a display panel according to an embodiment of the present invention with reference to the accompanying drawings, a level shifter of a display panel in the related art will be described with reference to fig. 2.
In the related art, the display panel occasionally has a black screen phenomenon during power-on. The inventor of the application finds out through research that: before the program downloading of the time sequence control chip is completed, and before the resetting of the time sequence control chip is completed, some GPO ports are in an unknown state, and high level and low level can be output possibly. When signals output by a plurality of GPO ports are at high level, the signals are possibly unloaded after being converted and amplified by a level converter, so that the PMIC is protected, and the poor phenomenon of starting up and screen blacking is caused.
Specifically, as shown in fig. 2, VGH1 ' is the voltage of the second power supply electrically connected to the power supply terminal of the level shifter, CLKX _ T ' is the signal to be converted output by the timing control chip, and CLKX _ L ' is the signal converted by the level shifter.
When the voltage VGH1 'of the second power supply reaches the threshold value k', for example, 15V, the level shifter converts and amplifies the front-end signal, i.e., the signal to be converted output by the timing control chip, that is, when the voltage VGH1 'of the second power supply is greater than or equal to the threshold value k', i.e., VGH1 '≧ k', the level shifter can convert and amplify the received front-end signal for output.
As shown in fig. 2, before the program downloading of the timing control chip is completed, i.e. in the time period 101 ' in the figure, the voltage VGH1 ' of the second power supply reaches the threshold value k ', and then in the time period from when the voltage VGH1 ' of the second power supply reaches the threshold value k ' to when the program downloading of the timing control chip is completed, i.e. in the time period 102 ' in the figure, the level shifter may perform the conversion amplification output on the signal CLKX _ T ', i.e. the high level, output from the timing control chip, to obtain the signal CLKX _ L ' which is converted and amplified by the level shifter, i.e. the abnormal waveform shown by 103 ' in the figure, thereby protecting the PMIC and causing the undesirable phenomenon of black screen during the boot.
Based on this, the invention provides a level conversion device of a display panel, a control method thereof and the display panel.
Hereinafter, a level conversion apparatus of a display panel according to an embodiment of the present application will be described in detail with reference to the accompanying drawings.
Fig. 1 is a block diagram of a level shifter of a display panel according to an embodiment of the invention. As shown in fig. 1, a level shift apparatus 1 of a display panel according to an embodiment of the present invention includes a plurality of level shift modules 100, wherein the plurality of level shift modules 100 are electrically connected to a plurality of signal output terminals of a timing control chip 30 in the display panel, respectively, and each of the level shift modules 100 includes: a level shifter 10 and a control circuit 20.
The input terminal IN of the level shifter 10 is electrically connected to a corresponding signal output terminal IN the timing control chip 30, and when the power supply terminal VIN of the level shifter 10 is connected to the first power supply VGH, the level shifter 10 receives the signal to be converted output by the corresponding signal output terminal and converts and amplifies the signal to be converted.
For example, as shown IN fig. 1, the level shifter 1 of the display panel according to the embodiment of the present invention may include, for example, N level shift modules 100, wherein an input terminal IN of a level shifter 10 IN the 1 st level shift module 100 is connected to a signal Output terminal Output1 IN the timing control chip 30, an input terminal IN of a level shifter 10 IN the 2 nd level shift module 100 is connected to a signal Output terminal Output2 IN the timing control chip 30, and an input terminal IN of a level shifter 10 IN the nth level shift module 100 is connected to a signal Output terminal Output N IN the timing control chip 30.
The control circuit 20 is electrically connected to the power source terminal VIN of the level shifter 10 and the first power source VGH, respectively, and the control circuit 20 is configured to control the power source terminal VIN of the level shifter 10 to switch on the first power source VGH when acquiring the reset completion signal of the timing control chip 30.
It is understood that the TCON IC (timing control chip 30) is reset, for example, Code Download, after the display panel is powered on, and performs normal display output after the reset is completed.
It should be noted that the level shifter 1 of the embodiment of the present invention can be disposed between the gate driving circuit 40, such as a GOA (gate Driver On Array) circuit, and the timing control chip 30, the GOA circuit utilizes the Array (Array) process of the existing liquid crystal display to fabricate the gate scanning driving circuit On the Array substrate, the GOA circuit is used to load the gate scanning signal to each gate line in the display panel, and the level shifter 10 is used to convert the input small-amplitude level signal into a large-amplitude level signal capable of driving the GOA circuit. Specifically, the timing control chip 30 may output the signal to be converted to the level shifter 10 through the signal output terminal, and the level shifter 10 converts the input signal to be converted with a low amplitude voltage (e.g., 3.3V) into a signal with a high amplitude voltage (e.g., about 30V) to drive the GOA circuit.
According to an embodiment of the present invention, as shown in fig. 3, the control circuit 20 is electrically connected to the Reset signal terminal RS of the timing control chip 30, and generates a Reset completion signal, i.e., Code Download completion, when the voltage Uset of the Reset signal Reset of the Reset signal terminal RS reaches the reference voltage Uref.
The reference voltage is a voltage reached by the Reset signal Reset when the timing control chip 30 completes the Reset. That is, when the Reset of the timing control chip 30 is completed, the voltage Uset of the Reset signal Reset reaches the reference voltage Uref.
It can be understood that the voltage of the first power supply VGH has reached the critical value k that can bring the level shifter 10 into the level shift state before the voltage Uset of the Reset signal Reset reaches the reference voltage Uref, so that the level shifter 10 can be brought into the level shift state when the voltage Uset of the Reset signal Reset reaches the reference voltage Uref, i.e., the control circuit 20 controls the power supply terminal VIN of the level shifter 10 to turn on the first power supply VGH.
Among them, the reference voltage Uref may be determined based on the model of the timing control chip 30.
It can be understood that, since the voltage Uset of the Reset signal Reset may be inconsistent when the Reset of the timing control chips 30 of different models is completed, the reference voltage Uref may be set according to the actual conditions of the timing control chips 30, thereby improving the versatility.
In some embodiments, the reference voltage Uref may be set by a programming procedure of I2C, or the like.
Further, according to an embodiment of the present invention, as shown in fig. 4, the control circuit 20 includes: a controllable switch 21 and a comparison sub-circuit 22, wherein a first terminal 21a of the controllable switch 21 is electrically connected to the first power supply VGH, and a second terminal 21b of the controllable switch 21 is electrically connected to the power supply terminal VIN of the level shifter 10; the output terminal of the comparison sub-circuit 22 is electrically connected to the control terminal 21c of the controllable switch 21, the first input terminal of the comparison sub-circuit 22 is electrically connected to the Reset signal terminal RS of the timing control chip 30 to receive the Reset signal Reset of the timing control chip 30, the second input terminal of the comparison sub-circuit 22 is configured to receive the reference voltage Uref, and the comparison sub-circuit 22 is configured to compare the voltage Uset of the Reset signal Reset with the reference voltage Uref and control the controllable switch 21 to be turned on when the voltage Uset of the Reset signal Reset reaches the reference voltage Uref.
It should be noted that the controllable switch 21 can be a MOSFET transistor, an IGBT transistor, or a triode.
It can be understood that, when the voltage Uset of the Reset signal Reset is greater than or equal to the reference voltage Uref, i.e. Uset ≧ Uref, the comparison sub-circuit 22 controls the controllable switch 21 to turn on, so that the power source terminal VIN of the level shifter 10 turns on the first power supply VGH, the level shifter 10 enters a level shifting state, and performs shifting amplification on the signal to be shifted output by the timing control chip 30 received by the input terminal IN.
When the voltage Uset of the Reset signal Reset is smaller than the reference voltage Uref, i.e. Uset < Uref, the comparison sub-circuit 22 controls the controllable switch 21 to turn off, so that the power source terminal VIN of the level shifter 10 fails to turn on the first power source VGH, and the level shifter 10 does not enter a level shifting state, at this time, the level shifter 10 always outputs a low level no matter whether the signal to be shifted output by the timing control chip 30 is a high level or a low level.
Specifically, in the embodiment of the present invention, by providing the comparison sub-circuit 22 and the controllable switch 21, the voltage Uset of the Reset signal Reset at the Reset signal end RS of the timing control chip 30 is detected at the same time, when the voltage Uset of the Reset signal Reset is smaller than the reference voltage Uref, the comparison sub-circuit 22 outputs a low level, the controllable switch 21 is turned off, the level shifter 10 cannot enter the level shift state, that is, outputs a low level, when the voltage Uset of the Reset signal Reset exceeds the reference voltage Uref, the comparison sub-circuit 22 outputs a high level, the controllable switch 21 is turned on, the level shifter 10 enters the level shift state, and the received signal to be shifted output by the timing control chip 30 is shifted and amplified.
Therefore, the phenomenon that a plurality of signals to be converted are pulled up simultaneously when the mobile terminal is started can be prevented on the premise of not increasing other protective measures, and the phenomenon of black screen caused by PMIC (Power management Integrated Circuit) load-pulling protection is prevented.
Specifically, according to an embodiment of the present invention, as shown in fig. 4, the comparison sub-circuit 22 includes: the output end of the comparator B is electrically connected with the control end 21c of the controllable switch 21; one end of the first resistor R1 is electrically connected to the positive input end of the comparator B, the other end of the first resistor R1 is electrically connected to one end of the second resistor R2, the other end of the first resistor R1 is used for receiving a Reset signal Reset of the timing control chip 30, and the other end of the second resistor R2 is grounded; one end of the third resistor R3 is electrically connected to one end of the fourth resistor R4, one end of the third resistor R3 is also electrically connected to the negative input terminal of the comparator B, the other end of the third resistor R3 is electrically connected to the reference voltage setting terminal ref, and the other end of the fourth resistor R4 is grounded.
It can be understood that, when the voltage V + at the positive input end of the comparator B is greater than or equal to the voltage V-at the negative input end, i.e. V + is greater than or equal to V-, the output end of the comparator B outputs a high level, the controllable switch 21 is turned on, the power supply end VIN of the level shifter 10 is connected to the first power supply VGH and enters a level shifting state, so as to shift and amplify the signal to be shifted, which is received by the input end IN and output by the timing control chip 30. When the voltage V + at the positive input end of the comparator B is less than the voltage V-at the negative input end, i.e. V + < V-, the output end of the comparator B outputs a low level, the controllable switch 21 is turned off, and the power supply terminal VIN of the level shifter 10 is not connected to the first power supply VGH, so that the level shifter 10 cannot enter a level shifting state, and at this time, the level shifter 10 always outputs a low level no matter whether the signal to be shifted output by the timing control chip 30 is a high level or a low level.
In an embodiment of the invention, as shown in fig. 4, there is one second resistor R2, wherein each of the level shift modules 100 is electrically connected to one end of the second resistor R2, and the other end of the second resistor R2 is grounded.
That is, the other end of the first resistor R1 in the plurality of level shift modules 100 is electrically connected to one end of the second resistor R2.
The operation principle of the level shifter of the display panel of the embodiment of fig. 4 is further described in conjunction with fig. 5. VGH1 is the voltage of the first power VGH electrically connected to the power supply terminal VIN of the level shifter, CLKX _ T is the signal to be converted output by the timing control chip 30, and CLKX _ L is the output signal of the level shifter 10.
When the voltage Uset of the Reset signal Reset of the timing control chip 30 does not reach the reference voltage Uref, i.e. Uset < Uref, that is, when the timing control chip 30 has not completed the program download, i.e. has not completed the Reset, as shown in the time period 101 in fig. 5, the voltage V + at the positive input terminal of the comparator B is less than the voltage V-at the negative input terminal of the comparator B, and the output terminal of the comparator B outputs a low level, so that the controllable switch 21 is turned off, and the power source terminal VIN of the level shifter 10 cannot turn on the first power source VGH, so that the output signal of the level shifter 10 is always a low level during the time period from the time when the voltage of the first power source VGH reaches the critical value k to the time when the program download is completed, i.e. the time period 102 in the figure, no matter whether the signal to be converted output by the timing control chip 30 is a high level or a low level, as shown in 103.
When the voltage Uset of the Reset signal Reset of the timing control chip 30 reaches the reference voltage Uref, i.e., Uset ≧ Uref, i.e., after the timing control chip 30 completes the reset, i.e., the program download, as shown in fig. 5 after time period 101, the voltage V + at the positive input terminal of the comparator B is greater than or equal to the voltage V at the negative input terminal of the comparator B, the output terminal of the comparator B outputs a high level, thereby, the controllable switch 21 is turned on, the power source terminal VIN of the level shifter 10 is turned on the first power source VGH, the level shifter 10 enters a level shifting state, and performs shifting amplification on the signal to be shifted output by the timing control chip 30, specifically, when the signal to be converted, which is output from the timing control chip 30, is at a high level, the level shifter 10 outputs a high level, when the signal to be converted output by the timing control chip 30 is at a low level, the level shifter 10 outputs a low level.
Therefore, the voltage Uset of the Reset signal Reset is compared with the reference voltage Uref by the voltage comparator B, and the on-off of the controllable switch 21 is controlled according to the comparison result, so that the on-off of the first power supply VGH input to the level shifter 10 can be controlled, the phenomenon that a plurality of signals to be converted are pulled up simultaneously when the power is started is effectively prevented, and the phenomenon of black screen caused by PMIC load-pumping protection is prevented.
In summary, according to the level shifter of the display panel provided in the embodiment of the present invention, when the control circuit obtains the reset completion signal of the timing control chip, the control circuit controls the power end of the level shifter to switch on the first power supply, so that the level shifter receives the signal to be converted output by the corresponding signal output end and converts and amplifies the signal to be converted. Therefore, the level conversion device of the display panel can prevent the phenomenon that a plurality of signals to be converted are simultaneously pulled high due to the unstable state of the GPO port before the resetting of the time sequence control chip is completed, and further can avoid the bad phenomenon of starting up a black screen due to the PMIC load extraction protection.
Based on the level shift device of the display panel in the above embodiment, an embodiment of the present invention further provides a display panel including the level shift device of the display panel.
According to an embodiment of the present invention, as shown in fig. 6, the level shifter 1 is electrically connected to the timing control chip 30, and the level shifter 1 is further electrically connected to the gate driving circuit 40.
According to the display panel provided by the embodiment of the invention, the phenomenon that a plurality of signals to be converted are simultaneously pulled up due to the unstable state of the GPO port before the resetting of the time sequence control chip is completed can be prevented through the level conversion device of the display panel, and the bad phenomenon of starting up a black screen due to PMIC (power management integrated circuit) load extraction protection can be further avoided.
Based on the level shift device of the display panel in the above embodiments, the embodiment of the present invention further provides a control method of the level shift device of the display panel.
Fig. 7 is a flowchart illustrating a method for controlling a level shifter of a display panel according to an embodiment of the invention.
The level conversion device comprises a plurality of level conversion modules, the level conversion modules are respectively electrically connected with a plurality of signal output ends of a time sequence control chip in the display panel, each level conversion module comprises a level converter, the input end of each level converter is electrically connected with the corresponding signal output end in the time sequence control chip, and when the power end of each level converter is connected with a first power supply, each level converter receives a signal to be converted output by the corresponding signal output end and converts and amplifies the signal to be converted.
As shown in fig. 7, the method for controlling a level shifter of a display panel according to an embodiment of the present invention includes the following steps:
and S1, acquiring a reset completion signal of the time sequence control chip.
In an embodiment of the present invention, as shown in fig. 8, acquiring the reset completion signal of the timing control chip further includes the following steps:
s10, receiving a reset signal from the reset signal terminal of the timing control chip.
S11, when the voltage of the reset signal at the reset signal terminal reaches the reference voltage, a reset completion signal is generated.
The reference voltage is the voltage reached by the reset signal when the time sequence control chip is reset.
Wherein, the reference voltage can be determined based on the model of the time sequence control chip.
And S2, controlling the power supply end of the level shifter to switch on the first power supply.
It should be noted that the foregoing explanation of the embodiment of the level shift apparatus of the display panel is also applicable to the control method of the level shift apparatus of the display panel of this embodiment, and is not repeated herein.
In summary, according to the control method of the level shifter of the display panel provided in the embodiment of the invention, when the reset completion signal of the timing control chip is acquired, the power end of the level shifter is controlled to turn on the first power. Therefore, the control method of the level conversion device of the display panel can prevent the phenomenon that a plurality of signals to be converted are simultaneously pulled up due to the unstable state of the GPO port before the resetting of the time sequence control chip is completed, and further can avoid the bad phenomenon of starting up a black screen due to the PMIC load extraction protection.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing steps of a custom logic function or process, and alternate implementations are included within the scope of the preferred embodiment of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present invention.
The logic and/or steps represented in the flowcharts or otherwise described herein, e.g., an ordered listing of executable instructions that can be considered to implement logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.
It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and when the program is executed, the program includes one or a combination of the steps of the method embodiments.
In addition, functional units in the embodiments of the present invention may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.
The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc. Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (9)
1. The level conversion device of the display panel is characterized by comprising a plurality of level conversion modules, wherein the level conversion modules are respectively and electrically connected with a plurality of signal output ends of a time sequence control chip in the display panel, and each level conversion module comprises:
the input end of the level shifter is electrically connected with the corresponding signal output end in the time sequence control chip, and when the power end of the level shifter is connected with a first power supply, the level shifter receives a signal to be converted output by the corresponding signal output end and converts and amplifies the signal to be converted; and
the control circuit is electrically connected with the power end of the level shifter and the first power supply respectively, and is used for controlling the power end of the level shifter to be connected with the first power supply when the reset completion signal of the sequential control chip is acquired.
2. The device of claim 1, wherein the control circuit is electrically connected to a reset signal terminal of the timing control chip, and generates the reset completion signal when a voltage of a reset signal of the reset signal terminal reaches a reference voltage, wherein the reference voltage is a voltage reached by the reset signal when the timing control chip completes resetting.
3. The apparatus of claim 2, wherein the control circuit comprises:
a first end of the controllable switch is electrically connected with the first power supply, and a second end of the controllable switch is electrically connected with a power supply end of the level shifter;
the output end of the comparison sub-circuit is electrically connected with the control end of the controllable switch, the first input end of the comparison sub-circuit is electrically connected with the reset signal end of the time sequence control chip to receive the reset signal of the time sequence control chip, the second input end of the comparison sub-circuit is used for receiving the reference voltage, and the comparison sub-circuit is used for comparing the voltage of the reset signal with the reference voltage and controlling the controllable switch to be switched on when the voltage of the reset signal reaches the reference voltage.
4. The device according to claim 3, wherein the comparison sub-circuit comprises:
the output end of the comparator is electrically connected with the control end of the controllable switch;
one end of the first resistor is electrically connected with the positive input end of the comparator, the other end of the first resistor is electrically connected with one end of the second resistor, the other end of the first resistor is used for receiving a reset signal of the time sequence control chip, and the other end of the second resistor is grounded;
the voltage regulator comprises a third resistor and a fourth resistor, wherein one end of the third resistor is electrically connected with one end of the fourth resistor, one end of the third resistor is also electrically connected with the negative input end of the comparator, the other end of the third resistor is electrically connected with the reference voltage setting end, and the other end of the fourth resistor is grounded.
5. The apparatus of claim 4, wherein the second resistor is one, and wherein the plurality of level shift modules are electrically connected to one end of the second resistor, and the other end of the second resistor is grounded.
6. A display panel comprising the level conversion apparatus of the display panel according to any one of claims 1 to 5.
7. The display panel of claim 6, wherein the level shifter is electrically connected to the timing control chip, and the level shifter is further electrically connected to a gate driving circuit.
8. A control method for a level shifter of a display panel, wherein the level shifter includes a plurality of level shifting modules, the level shifting modules are electrically connected to a plurality of signal output terminals of a sequential control chip in the display panel, each level shifting module includes a level shifter, an input terminal of the level shifter is electrically connected to a corresponding signal output terminal of the sequential control chip, and when a power terminal of the level shifter is connected to a first power supply, the level shifter receives a signal to be converted output from the corresponding signal output terminal and converts and amplifies the signal to be converted, the method includes the following steps:
acquiring a reset completion signal of the time sequence control chip;
and controlling a power supply end of the level shifter to be connected with the first power supply according to the reset completion signal so that the level shifter receives a signal to be converted output by a corresponding signal output end in the time sequence control chip according to the first power supply and converts and amplifies the signal to be converted.
9. The method as claimed in claim 8, wherein the obtaining the reset completion signal of the timing control chip comprises:
receiving a reset signal of a reset signal end of the time sequence control chip;
generating the reset completion signal when a voltage of a reset signal of the reset signal terminal reaches a reference voltage;
the reference voltage is the voltage reached by the reset signal when the time sequence control chip is reset.
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| CN111599299B (en) * | 2020-06-18 | 2023-12-12 | 京东方科技集团股份有限公司 | Level conversion circuit and display panel |
| CN112951134B (en) * | 2021-04-20 | 2022-09-20 | 合肥京东方显示技术有限公司 | Clock recovery device, source electrode driving circuit, display panel and equipment |
| CN113450727B (en) * | 2021-06-25 | 2022-11-11 | 京东方科技集团股份有限公司 | Driving circuit and driving method of display device |
| CN114038434B (en) * | 2021-11-09 | 2023-03-07 | 深圳创维－Rgb电子有限公司 | Power sequence control circuit and method for liquid crystal panel, liquid crystal panel and display device |
| CN114495797B (en) * | 2022-02-23 | 2023-07-28 | 合肥京东方显示技术有限公司 | Display device, driving module and initializing module thereof |
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