CN112951134B - Clock recovery device, source electrode driving circuit, display panel and equipment - Google Patents
Clock recovery device, source electrode driving circuit, display panel and equipment Download PDFInfo
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- CN112951134B CN112951134B CN202110427042.3A CN202110427042A CN112951134B CN 112951134 B CN112951134 B CN 112951134B CN 202110427042 A CN202110427042 A CN 202110427042A CN 112951134 B CN112951134 B CN 112951134B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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Abstract
The invention discloses a clock recovery device, a source electrode driving circuit, a display panel and equipment, wherein the clock recovery device comprises: a clock generator; the frequency detector is connected with a power supply, and the control voltage output by the frequency detector is used for controlling the clock generator to work; after the source electrode driving circuit is powered on, the control voltage output by the frequency detector is pulled to a high potential by the power supply, and the clock generator is used for analyzing the received target data signal according to the control voltage of the high potential to obtain a clock signal. The invention can effectively generate clock signals and improve the problem of black screen of the display panel.
Description
Technical Field
The invention relates to the technical field of electronics, in particular to a clock recovery device, a source electrode driving circuit, a display panel and equipment.
Background
The display panel has certain probability of poor black screen in detection, and the poor phenomenon can disappear after the temperature is reduced. This is because the driving data signal output to the source driving circuit by the timing controller (TCON IC) is later than the power-on time of the source driving circuit after the power-on start of the display panel. In a high temperature state, a leakage current inside the source driver circuit is large, and after the large leakage current continues for a certain time, a control voltage V output by a Frequency Detector (FD) inside the clock recovery apparatus CTRL Will be pulled low. Once the voltage V is controlled CTRL The driving data signal output by the time schedule controller is sent to the source electrode driving circuit, the source electrode driving circuit can not generate a clock signal again, and therefore the source electrode driving circuit enters an abnormal working state and a black screen appears.
Disclosure of Invention
In view of the above problems, the present invention has been made to provide a clock recovery device, a source driving circuit, a display panel, and an apparatus that overcome or at least partially solve the above problems.
In a first aspect, a clock recovery apparatus disposed in a source driving circuit of a display panel includes:
a clock generator;
the frequency detector is connected with a power supply, and the control voltage output by the frequency detector is used for controlling the clock generator to work;
after the source electrode driving circuit is powered on, the control voltage output by the frequency detector is pulled to a high potential by the power supply, and the clock generator is used for analyzing the received target data signal according to the control voltage of the high potential to obtain a clock signal.
Optionally, the control voltage is output through a target port of the frequency detector, and the apparatus further includes:
a first switch circuit connected between the target port and the power supply;
the first switch circuit is used for connecting the target port and the power supply when a target data signal received by the clock generator is in a floating state so as to enable the power supply to pull up a control voltage, and disconnecting the connected target port and the power supply when the target data signal received by the clock generator is in a normal state.
Optionally, the first switching circuit includes:
a gate of the first field effect transistor is connected with a first output port of a lock detector in the source drive circuit, a source of the first field effect transistor is connected with the power supply, and a drain of the first field effect transistor is connected with the target port;
wherein the first output port of the lock detector outputs a low potential voltage when the target data signal is in a floating state and outputs a high potential voltage when the target data signal is in a normal state.
Optionally, the control voltage is output through a target port of the frequency detector, and the apparatus further includes:
a voltage detection circuit and a second switch circuit;
the voltage detection circuit is connected between the target port and the second switch circuit and is used for detecting the control voltage;
the second switch circuit is connected between the voltage detection circuit and the power supply, and is used for connecting the power supply and the target port when the detection result of the control voltage is a low potential, and disconnecting the power supply and the target port when the detection result of the control voltage is a high potential.
Optionally, the voltage detection circuit includes:
and a first input end of the comparator is connected with the target port, a second input end of the comparator is connected with a reference power supply, and an output end of the comparator is connected with the second switch circuit.
Optionally, the second switch circuit includes:
and the grid electrode of the second field effect transistor is connected with the output end of the comparator, the source electrode of the second field effect transistor is connected with the power supply, and the drain electrode of the second field effect transistor is connected with the target port.
Optionally, the source driving circuit includes a lock detector, and the apparatus further includes:
and the error locking detector is connected between the frequency detector and the locking detector and used for resetting the frequency detector to pull up the control voltage output by the frequency detector when the target data is in a normal state and a low-potential signal output by a second output port of the locking detector is received.
In a second aspect, a source driving circuit is provided, which includes the clock recovery apparatus of the first aspect.
In a third aspect, a display panel is provided, which includes the clock recovery apparatus of the first aspect.
In a fourth aspect, a display device is provided, which includes the clock recovery apparatus of the first aspect.
The technical scheme provided by the embodiment of the invention at least has the following technical effects or advantages:
according to the clock recovery device, the source electrode driving circuit, the display panel and the device, the frequency detector is connected with the power supply, and the control voltage output by the frequency detector is used for controlling the clock generator to work. The problem that the display panel is blacked due to the fact that the clock generator cannot generate effective clock signals after the control voltage is abnormally pulled down in a high-temperature state is effectively solved, and the blacked screen problem of the display panel is effectively improved.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 is a diagram of a source driver circuit according to the prior art;
FIG. 2 is a circuit diagram of a clock recovery apparatus according to an embodiment of the present invention;
FIG. 3 is a timing diagram illustrating the normal operation of the source driving circuit according to the embodiment of the present invention;
FIG. 4 is a schematic diagram of a first switch circuit according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of the connection between the voltage detection circuit and the second switch circuit according to the embodiment of the present invention;
FIG. 6 is a timing diagram illustrating the abnormal operation of a source driver circuit at high temperature in the prior art;
FIG. 7 is a timing diagram at an elevated temperature in a scheme provided by an embodiment of the present invention;
FIG. 8 is a diagram illustrating a source driver circuit according to an embodiment of the present invention;
FIG. 9 is a diagram of a display panel according to an embodiment of the present invention;
fig. 10 is a schematic diagram of a display device in an embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The reason why the display panel is blacked at a high temperature is that after the display panel is powered on and started, the driving data signal output from the timing controller to the source driving circuit is later than the power-on time of the source driving circuit, and since the target data signal input to the Clock Generator (Clock Generator) is obtained by changing the driving data signal, the Clock Generator cannot generate a normal Clock signal during the period of time after the source driving circuit is powered on and before the driving data signal is input to the source driving circuit. Further, since the data Sampler (Sampler), the Lock Detector (Lock Detector) and the frequency Detector in the source driving circuit all operate normally depending on the clock signal, the control voltage V output from the frequency Detector during the period of time when the normal clock signal is not generated CTRL Leakage may occur, leaking to ground GND. And once V CTRL The potential becomes low, and even if the target data signal is generated after the driving data signal is supplied to the source driver circuit, the clock generator cannot generate the clock signal, thereby causing the source driver circuit to enter an abnormal operating state.
To prevent the control voltage output by the frequency Detector from being pulled low, a False Lock Detector (FLD) may be added to the Clock Recovery device (Clock Recovery), as shown in fig. 1. FLD is used to characterize the signal at the internal clock of the Lock detector output (Lock in FIG. 1) i ) At low voltage, a reset signal (POR _ FD in FIG. 1) is output to reset the frequency detector to raise V CTRL Such that the clock generator is able to normally generate a clock signal when the driving data signal arrives, the data sequence output by the data sampler shown in fig. 1 is 28 bits, denoted D [27:0 ]]Thus, the clock signal sequence generated by the clock generator corresponds to the data sequence direction, denoted CK [27:0 ]]And the clock signal is output to the data sampler, the lock detector and the frequency detector so that the source electrode driving circuit can work normally, thereby solving the problem of black screen of the display panel.
But instead of the other end of the tubeUnder high temperature, the data sampler will generate leakage current to cause Lock i Becomes high potential so that FLD cannot normally operate and the frequency detector cannot be reset, therefore, V CTRL Continuously low, the clock generator cannot normally generate a clock signal. And no clock generates signals, the source electrode driving circuit cannot work normally, and finally, the screen blacking is caused. Embodiments of the present invention provide a clock recovery apparatus, a source driving circuit, a display panel, and a device, so as to ensure that a control voltage output by a frequency detector is at a high potential during a period after a source driving circuit is powered on and before a driving data signal is input to the source driving circuit, so that a clock generator can normally generate a clock signal, and the source driving circuit can normally operate.
As shown in fig. 2, a clock recovery apparatus according to an embodiment of the present invention is a circuit structure diagram of a clock recovery apparatus according to an embodiment of the present invention, including:
a clock generator 10; the frequency detector 20, the frequency detector 20 is connected with the power supply 30, and the control voltage output by the frequency detector 20 is used for controlling the clock generator 10 to work; after the source driving circuit is powered on, the control voltage output by the frequency detector 20 is pulled up to a high potential by the power supply 30, and the clock generator 10 is configured to analyze the received target data signal according to the control voltage of the high potential to obtain a clock signal.
In the embodiment of the present invention, the clock generator 10 is used for generating the target data signal (D in fig. 2) when the control voltage is high IN ) The analysis is performed to generate a clock signal. The target data Signal is obtained by amplifying, modulating and demodulating a driving data Signal through an Analog front-end (AFE), and the driving data Signal may specifically be a CEDS (Clock Embedded Differential Signal) Signal. The clock signal output from the clock generator 10 is output to the frequency detector 20, the data sampler in the source drive circuit, the lock detector, and the like.
The control voltage output by the frequency detector 20 is used to control the operation of the clock generator 10, wherein when the control voltage is high potential, the clock generator 10 can normally analyze the clock signal after receiving the target data signal; when the control voltage is low, the clock generator 10 cannot normally analyze the target data signal.
In order to avoid the above-mentioned problems and ensure that the potential of the control voltage is pulled up when the target data signal arrives, in the embodiment of the present invention, the frequency detector 20 is connected to the power supply 30, and after the source driving circuit is powered on, the power supply 30 outputs a high potential voltage to the frequency detector 20, so that the output control voltage is forced to be pulled up, that is, after the source driving circuit is powered on, the control voltage can be ensured to be a high potential, thereby effectively avoiding that the clock signal cannot be generated due to the pulling down of the control voltage. Of course, the power supply 30 may pull up the control voltage after the source driving circuit is powered on, or may pull up the control voltage after a period of time after the source driving circuit is powered on, as long as it is ensured that the clock generator 10 pulls up the control voltage before receiving the target data signal. The power supply 30 may be a power supply of the source driving circuit, may also be a power supply separately added to the frequency detector 20, and may also be another external power supply, which is not limited herein.
In addition, since the control voltage is pulled up by the power supply 30, it is not necessary to use the FLD to control the control voltage, and therefore, in some embodiments, the FLD may be omitted from the clock recovery generator, which on one hand avoids the FLD from failing due to high-temperature leakage, and on the other hand, can reduce the cost.
As shown in fig. 3, a timing diagram of a source driving circuit during normal operation according to an embodiment of the present invention includes a clock recovery device, a data sampler, and a lock detector, wherein the clock recovery device includes a clock generator and a frequency detector. Next, the change of each signal in the normal operation state will be described by taking the drive data signal as an example of the CEDS.
Since the CEDS signal is powered up later than the AVDD (power-up signal of the source driver circuit), the CEDS is in a Floating state during a period from power-up of the AVDD to power-up of the CEDS.
D IN Is a target data signal due to D IN Is generated by AFE from CEDS, so that it is in floating state in the period from AVDD power-on to CEDS power-on, and D is in floating state after CEDS power-on IN And is in a normal working state.
AVDD is a power-on signal of the source electrode driving circuit, and a constant potential is always kept after power-on.
CK is clock signal, before CEDS is powered on, D IN In the floating state, the clock generator 10 cannot analyze the CK signal, i.e. CK is at a low potential; after the CEDS is powered on, the clock generator 10 normally resolves the CK signal.
D [0] For data identification bit signal output by data sampler, before CEDS is powered on, D IN In a floating state, D [0] Following D IN ，D [0] In a floating state; after CEDS is powered on, D [0] And is in a normal working state.
Lock i For the internal clock-characterizing signal output by the Lock detector, Lock before CEDS is powered on i Is at a low potential; after CEDS is powered on, Lock i In normal working state, the voltage is high potential.
The Lock _ Pad is a cascade clock characterization signal between source drive circuits output by the Lock detector, and before the CEDS is electrified, the Lock _ Pad is at a low potential; after the CEDS is electrified, high potential is normally output.
V CTRL After the AVDD is powered on, the power supply 30 will supply the control voltage V output by the frequency detector 20 CTRL Drawing high, V CTRL The high potential is maintained.
In the embodiment of the present invention, after the source driving circuit is powered on, the control voltage can be pulled up by the power supply 30, and the high potential is kept unchanged in the whole working process of the source driving circuit. Or the control voltage may be pulled up by the power supply 30 before the CEDS is powered on, after the CEDS is powered on, the AFE processes the CEDS to obtain the target data signal, and after the frequency detector 20 can normally work to generate the high-potential control voltage, the pulling up of the power supply 30 to the control voltage may be cancelled, and the control voltage is automatically generated by the frequency detector 20.
In a specific implementation, the power supply 30 can be switched on and off by: the control voltage is output through a target port of the frequency detector 20, and the apparatus further includes: a first switch circuit connected between the target port and the power supply 30; the first switch circuit is used for connecting the target port and the power supply 30 when the target data signal received by the clock generator 10 is in a floating state, so that the power supply 30 pulls up the control voltage, and disconnecting the connected target port and the power supply 30 when the target data signal received by the clock generator 10 is in a normal state. Of course, the first switch circuit may be disposed inside the clock recovery device, or may be disposed outside the clock recovery device, which is not limited herein.
The first switch circuit may be provided as needed, for example, the first switch circuit may include a transistor, a field effect transistor, or other switching devices.
As shown in fig. 4, a schematic diagram of a first switch circuit provided in this specification is shown, where the first switch circuit includes: a grid electrode of the first field effect transistor is connected with a first output port of the locking detector in the source electrode driving circuit, a source electrode of the first field effect transistor is connected with the power supply 30, and a drain electrode of the first field effect transistor is connected with a target port; the first output port of the lock detector outputs a low potential voltage when the target data signal is in a floating state, and outputs a high potential voltage when the target data signal is at a high potential.
In the first switch circuit shown in fig. 4, the switching function is realized by the first fet, which may be a PMOS transistor, and the first output port of the Lock detector is a port for outputting a Lock _ pad signal, and the gate of the first fet is connected to the first output port, and the on/off of the first fet is controlled by the Lock _ pad signal. Specifically, since Lock _ pad is at a low voltage level before the CEDS is powered on, and the PMOS transistor is in a conducting state, the power supply 30 provides a voltage to the frequency detector 20 to pull up the control voltage. After the CEDS is powered on, a target data signal is generated, the clock generator 10 can normally analyze the clock signal, the Lock _ pad signal becomes a high potential, at this time, the PMOS transistor is turned off, the connection between the power supply 30 and the frequency detector 20 is cut off, and the frequency detector 20 outputs a high-potential control voltage by itself.
In order to avoid that the control voltage is pulled down again due to other faults when the frequency detector 20 outputs the control voltage with a high potential by itself, the following embodiments are provided in the embodiment of the present invention: a voltage detection circuit and a second switch circuit; the voltage detection circuit is connected between the target port and the second switch circuit and is used for detecting the control voltage; and the second switch circuit is connected between the voltage detection circuit and the power supply and used for connecting the power supply and the target port when the detection result of the control voltage is a low potential and disconnecting the power supply and the target port when the detection result of the control voltage is a high potential.
By adding the voltage detection circuit, the output control voltage can be monitored during the operation of the frequency detector 20, if the control voltage is detected to be at a high potential, the control voltage is continuously output through the frequency detector 20, and if the control voltage is detected to be at a low potential, the power supply 30 is connected to the target port through the second switch circuit again, so that the power supply 30 pulls the control voltage high.
In an alternative embodiment, a voltage detection circuit includes: and a first input end of the comparator is connected with the target port, a second input end of the comparator is connected with the reference power supply, and an output end of the comparator is connected with the second switch circuit. The second switching circuit includes: and the grid electrode of the second field effect transistor is connected with the output end of the comparator, the source electrode of the second field effect transistor is connected with the power supply, and the drain electrode of the second field effect transistor is connected with the target port.
Fig. 5 is a schematic diagram of connection between the voltage detection circuit and the second switch circuit provided in the embodiments of the present disclosure. As shown in fig. 5, the inverting input terminal of the comparator is a first input terminal, the forward input terminal is a second input terminal, and the inverting input terminal is connected to the target port of the frequency detector 20 through a resistor R3 to input the control voltage V to the inverting input terminal CTRL The positive input end is connected with a reference power supply, the reference voltage provided by the reference power supply can be set according to actual needs,such as reference voltages of 1.1V, 1.2V, etc. The comparator is connected to the power supply VDD1v8 of the source driver circuit through a resistor R1, and is grounded through a resistor R2.
The second switch circuit includes a second field effect transistor, which may be an NMOS transistor, an output of the comparator is connected to a gate of the NMOS transistor, a source of the NMOS transistor is connected to the power supply 30, and a drain of the NMOS transistor is connected to a target port of the frequency detector 20.
V output when frequency detector 20 is in normal operation CTRL If the voltage is high, the output of the comparison amplifier is low, and the NMOS transistor is in the cut-off state, i.e. V CTRL No pull-up by power supply 30 is required. V at the output of frequency detector 20 CTRL The voltage is low, the output of the comparator is high, the NMOS transistor is in a conducting state, and at the moment, the power supply 30 is connected and the voltage V is pulled high by the power supply 30 CTRL . By the mode, the control voltage can be monitored in real time, and the normal generation of the clock signal is ensured even if the power supply 30 is connected to pull up the potential of the control voltage under the condition that the control voltage is pulled down.
In an alternative embodiment, the control voltage may be pulled up by the power supply 30 before the CEDS is powered up, and the frequency detector may be reset by the error lock detector to pull up the control voltage after the CEDS is powered up. The specific implementation process is as follows: and the error locking detector is connected between the frequency detector and the locking detector and is used for resetting the frequency detector to pull up the control voltage output by the frequency detector when the target data signal is in a normal state and receives a low-potential signal output by a second output port of the locking detector.
Specifically, the second output port of the Lock detector outputs an internal clock characterization signal Lock i Port of, through Lock i To control the false lock detector to reset the frequency detector.
To better explain the control voltage being pulled up by the clock recovery apparatus in the high temperature state according to the embodiment of the present invention, please refer to fig. 6 and fig. 7, in which fig. 6 is a timing diagram of the source driving circuit in the abnormal operation at the high temperature in the prior art, and fig. 7 is a timing diagram at the high temperature in the scheme according to the embodiment of the present invention.
As shown in fig. 6, in the prior art, taking the FLD as an example to pull up the control voltage before powering on the CEDS, the FLD fails due to internal leakage of the data sampler in a high temperature state, so that the control voltage cannot be pulled up. Next, changes in the respective signals in fig. 6 will be described.
D IN Is a target data signal due to D IN CEDS is generated by AFE, so that the AVDD is in a floating state in the period from power-on to power-on of CEDS; after powering up the CEDS, D IN And is in a normal working state.
AVDD is a power-on signal of the source electrode driving circuit, and a constant potential is always kept after power-on.
CK is clock signal, before CEDS is powered on, D IN In the floating state, the clock generator 10 cannot analyze the CK signal, i.e. CK is at a low potential; after the CEDS is powered on, the control voltage is still at the low potential due to the FLD failure, so the clock generator 10 cannot analyze the CK signal, i.e. CK is at the low potential.
D [0] Identifying bit signal for data output by data sampler, before CEDS is powered on, electric leakage in data sampler due to high temperature, D [0] Is forced high; after CEDS is powered on, D is no clock input [0] In a floating state.
Lock i For the internal clock-characterizing signal output by the lock detector, the clock signal is at low potential before the CEDS is powered on, D [0] Is forced high, resulting in Lock i Is at a high potential; after CEDS is powered on, V CTRL At a low potential, CK and Lock cannot be generated normally i Still at a high potential.
The Lock _ Pad is a cascade clock characterization signal between source drive circuits output by the Lock detector, and before the CEDS is electrified, CK is low potential, and the Lock _ Pad is low potential; after CEDS is powered on, V CTRL At the low potential, CK cannot be normally generated, and Lock _ Pad is still at the low potential.
V CTRL For the control voltage output by the frequency detector 20, CEDS is powered upFront, due to Lock i At high potential, FLD can not work, and after a period of time, the voltage leaks to GND, V CTRL Is at a low potential; when CEDS is powered on, CK cannot be generated, frequency detector 20 cannot work normally, and V CTRL Is at a low potential.
As shown in fig. 7, to adopt the solution provided by the embodiment of the present invention, the control voltage is pulled up by the power supply 30 before the CEDS is powered up. Next, changes in the respective signals in fig. 7 will be described.
D IN Is a target data signal due to D IN CEDS is generated by AFE, so that the AVDD is in a floating state in the period from power-on to power-on of CEDS; after powering up the CEDS, D IN And is in a normal working state.
AVDD is a power-on signal of the source electrode driving circuit, and a constant potential is always kept after power-on.
D [0] Identifying bit signal for data output by data sampler, before CEDS is powered on, electric leakage in data sampler due to high temperature, D [0] Is forced high; after CEDS is powered on, D [0] Is in a normal working state.
Lock i For the internal clock-characterizing signal output by the lock detector, the clock signal is at low potential before the CEDS is powered on, D [0] Is forced high, resulting in Lock i Is at a high potential; after CEDS is powered on, Lock i The voltage is high potential in normal working state.
The Lock _ Pad is a cascade clock characterization signal between source drive circuits output by the Lock detector, and before the CEDS is electrified, CK is low potential, and the Lock _ Pad is low potential; after the CEDS is electrified, the Lock _ Pad is in a normal working state, and the voltage is high potential.
V CTRL The control voltage output by the frequency detector 20 is forced high by the power supply 30 before the CEDS is powered on; the CEDS is still high after being electrified.
Based on the same inventive concept, an embodiment of the present invention further provides a source driving circuit, as shown in fig. 8, including the aforementioned clock recovery apparatus. The same structure and advantageous effects as those of the clock recovery apparatus provided in the foregoing are also obtained.
As shown in fig. 8, the source driver circuit includes an analog front end 81, a clock recovery device 82, a data sampler 83, and a lock detector 84. Wherein the analog front end 81 is used to convert the CEDS into a target data signal D IN Clock recovery means 82 for use at D IN The data sampler 83 is used for outputting a data sequence D, the Lock detector 84 is used for outputting an internal clock characterization signal Lock i And a cascade clock characterization signal Lock _ Pad.
The clock recovery device 82 comprises a clock generator and a frequency detector, wherein the frequency detector is connected with a power supply, and the control voltage V output by the frequency detector can be pulled up by the power supply CTRL 。
Based on the same inventive concept, the embodiment of the present invention further provides a display panel, as shown in fig. 9, the display panel 90 includes the clock recovery apparatus 91 described above. The same structure and advantageous effects as those of the clock recovery apparatus provided in the foregoing are also obtained.
Based on the same inventive concept, an embodiment of the present invention further provides a display apparatus, as shown in fig. 10, the display apparatus 100 includes the aforementioned clock recovery device 101. The same structure and advantageous effects as those of the clock recovery apparatus provided in the foregoing are also obtained.
It should be noted that the display device may be: any product or component with a display function, such as a mobile phone, electronic paper, a tablet computer, a television, a display, a notebook computer, a digital photo frame or a navigator, etc.
Since the clock recovery devices included in the source driving circuit, the display panel, and the display device according to the embodiments of the present invention have been described in the foregoing, based on the clock recovery devices described in the embodiments of the present invention, those skilled in the art can understand specific structures and effect principles of the source driving circuit, the display panel, and the display device, and thus details are not described herein again. All the source driving circuit, the display panel and the display device including the clock recovery apparatus of the embodiment of the invention belong to the intended protection scope of the invention.
The technical scheme provided by the embodiment of the invention at least has the following technical effects or advantages: by connecting the frequency detector with the power supply, the control voltage output by the frequency detector is pulled high before the driving data is input into the source electrode driving circuit, so that the clock generator can analyze an accurate clock signal after receiving a target data signal under the control voltage of high potential. The problem that the clock generator cannot generate effective clock signals after the control voltage is abnormally pulled down at a high temperature is effectively avoided, and the black screen problem of the display panel is obviously improved.
In the description provided herein, numerous specific details are set forth. It is understood, however, that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be interpreted as reflecting an intention that: that the invention as claimed requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.
Those skilled in the art will appreciate that the modules in the apparatus of an embodiment may be adaptively changed and disposed in one or more apparatuses other than the embodiment. The modules or units or components of the embodiments may be combined into one module or unit or component, and furthermore they may be divided into a plurality of sub-modules or sub-units or sub-components. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where at least some of such features and/or processes or elements are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
Moreover, those of skill in the art will appreciate that while some embodiments herein include some features included in other embodiments, not others, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, in the following claims, any of the claimed embodiments may be used in any combination.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.
Claims (10)
1. A clock recovery apparatus provided in a source driving circuit of a display panel, comprising:
a clock generator;
the frequency detector is connected with a power supply, and the control voltage output by the frequency detector is used for controlling the clock generator to work;
after the source electrode driving circuit is powered on, the control voltage output by the frequency detector is pulled to a high potential by the power supply, and the clock generator is used for analyzing the received target data signal according to the control voltage of the high potential to obtain a clock signal.
2. The clock recovery apparatus of claim 1, wherein the control voltage is output through a target port of a frequency detector, the apparatus further comprising:
a first switch circuit connected between the target port and the power supply;
the first switch circuit is used for connecting the target port and the power supply when a target data signal received by the clock generator is in a floating state so as to enable the power supply to pull up a control voltage, and disconnecting the connected target port and the power supply when the target data signal received by the clock generator is in a normal state.
3. The clock recovery apparatus of claim 2, wherein the first switching circuit comprises:
a gate of the first field effect transistor is connected with a first output port of a lock detector in the source drive circuit, a source of the first field effect transistor is connected with the power supply, and a drain of the first field effect transistor is connected with the target port;
wherein the first output port of the lock detector outputs a low potential voltage when the target data signal is in a floating state and outputs a high potential voltage when the target data signal is in a normal state.
4. The clock recovery apparatus of claim 1, wherein the control voltage is output through a target port of a frequency detector, the apparatus further comprising:
a voltage detection circuit and a second switch circuit;
the voltage detection circuit is connected between the target port and the second switch circuit and is used for detecting the control voltage;
the second switch circuit is connected between the voltage detection circuit and the power supply, and is used for connecting the power supply and the target port when the detection result of the control voltage is a low potential, and disconnecting the power supply and the target port when the detection result of the control voltage is a high potential.
5. The clock recovery apparatus of claim 4, wherein the voltage detection circuit comprises:
and a first input end of the comparator is connected with the target port, a second input end of the comparator is connected with a reference power supply, and an output end of the comparator is connected with the second switch circuit.
6. The clock recovery apparatus of claim 5, wherein the second switching circuit comprises:
and the grid electrode of the second field effect transistor is connected with the output end of the comparator, the source electrode of the second field effect transistor is connected with the power supply, and the drain electrode of the second field effect transistor is connected with the target port.
7. The clock recovery apparatus of claim 2, wherein the source driver circuit comprises a lock detector, the apparatus further comprising:
and the error locking detector is connected between the frequency detector and the locking detector and used for resetting the frequency detector to pull up the control voltage output by the frequency detector when the target data signal is in a normal state and a low-potential signal output by a second output port of the locking detector is received, wherein the second output port of the locking detector is a port for outputting an internal clock representation signal.
8. A source driver circuit comprising the clock recovery apparatus of any one of claims 1 to 7.
9. A display panel comprising the clock recovery apparatus of any one of claims 1 to 7.
10. A display device characterized by comprising the clock recovery apparatus of any one of claims 1 to 7.
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| CN202110427042.3A CN112951134B (en) | 2021-04-20 | 2021-04-20 | Clock recovery device, source electrode driving circuit, display panel and equipment |
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