JP2842840B2 - Semiconductor device burn-in test equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a burn-in test (hereinafter referred to as "BT") for a semiconductor device, and more particularly to a test supplied externally due to a contact failure of a BT test board on which a semiconductor device under test is mounted. The present invention relates to a BT device of a semiconductor device which prevents a state in which a signal is not supplied to a semiconductor device under test and an initial failure is not removed, and a normal test is determined to have been performed.

[0002]

2. Description of the Related Art Generally, a BT device is used to remove an initial failure of a semiconductor device in a manufacturing process. This B
The T device mounts a plurality of semiconductor devices under test on a BT test board, accommodates these test board groups in a constant temperature test chamber, and all the signal input terminals of the semiconductor devices in the constant temperature test chamber are within the test board. The semiconductor device under test is subjected to an electrical characteristic test after accelerating a defective state by being continuously operated for a predetermined time in an atmosphere in which a high temperature test chamber is maintained at a predetermined high temperature in a state where the semiconductor device is connected to a power supply potential. This is an apparatus for removing initial failures.

At this time, since the input terminal of the semiconductor device under test is fixed at the power supply potential, the internal circuit of the semiconductor device is a BT test in a static state in which the operation is fixed at a certain operation. On the other hand, performing a test with the semiconductor device under test operating by repeatedly supplying a specific test signal to the input terminal of the semiconductor device under test is called dynamic BT.

FIG. 4 is a block diagram showing an example of the configuration of a dynamic BT device of this type. Referring to FIG. 4, this dynamic BT device has a driver circuit unit built in a BT test device 1 prepared outside a constant temperature test tank. 2 and a BT test board 3 set in a constant temperature test tank. A plurality of semiconductor devices 4 to be tested are mounted on the BT test board 3, and a signal input terminal of these semiconductor devices 4 to be tested has a driver. The test signal A output from the circuit unit 2 is distributed to each input terminal of each semiconductor device 4 in the test board 3 by the signal line 101. The test board 3 wired in this way is set in a constant temperature test tank, and the test board 3 is energized and a test signal A is supplied. Further, the temperature in the constant temperature test chamber is raised to the test temperature, and the temperature is maintained, and the apparatus is left for a period specified for the test. After this test period has elapsed, the test substrate 3 is taken out of the constant temperature test tank, the semiconductor device 4 is taken out of the socket of the test substrate 3 and the L
An electrical characteristic test is performed using an SI tester or the like.

In the above-described configuration of the dynamic BT device, since the driver circuit section 2 only supplies the test signal A to the semiconductor device 4 under test, the signal flows from the driver circuit 2 to the test substrate 3 in one direction. Only. Therefore, it is not confirmed whether or not the test signal A has been reliably transmitted. For example, when the wiring 101 of the test board 3 is cut, or when the test board 3 is inserted incorrectly, etc. In a state where the test signal A that should have been supplied to the BT is not actually input, the BT may end and the acceleration of the initial failure may not be performed.

[0006]

However, as described above, in the conventional dynamic BT device, the driver circuit unit 2
Only supplies the test signal A to the semiconductor device 4 under test, the signal line 101 for supplying the test signal A to the BT test substrate 3 is disconnected, or the test device 3 Even if the signal input terminal is fixed to the low level of the logic level, it does not have a function to detect the abnormal state. Therefore, even though the initial failure is not actually accelerated by the dynamic BT, the electrical characteristic test after the BT is performed assuming that the dynamic BT is normally completed. In some cases, the manufactured semiconductor device is shipped with a possibility of initial failure.

Although the above-mentioned BT device has a detection circuit for detecting an abnormality of a clock supplied to the test board, it does not exist in the test board.

SUMMARY OF THE INVENTION An object of the present invention is to provide a dynamic BT device for detecting whether or not a test signal supplied to a semiconductor device under test is normally supplied. In the test board, if it is not supplied normally, it outputs a signal to interrupt the test and shuts off the output of the test signal, thereby preventing the shipment of semiconductor devices that do not accelerate with initial failure And to improve reliability.

[0009]

A feature of the semiconductor device burn-in test apparatus according to the present invention is that a test board group on which a plurality of the semiconductor devices are mounted is housed in a constant temperature test tank in order to detect an initial failure of the semiconductor device. A burn-in test apparatus for a semiconductor device, in which a predetermined test signal is supplied to the semiconductor device in the constant temperature test chamber and continuously operated in a predetermined high temperature atmosphere for a predetermined time to accelerate a failure state, A driver circuit for generating a control signal whose phase is delayed by a predetermined time longer than a test signal and supplying these signals to the test board group; the control signal output from the driver circuit and the test signal; The test signal at the end of the test signal wiring wired to the signal input terminal of the semiconductor device in the substrate group is input, and the test The high-level period of the logical level of the signal is compared at the rising timing of the control signal from a low level to a high level, and the low-level period of the test signal is compared at the falling timing of the control signal from a high level to a low level. If the comparison results in a mismatch, the test signal is fixed at a high level or a low level. The clock abnormality detection circuit unit and the abnormality notification unit are respectively built in the test board.

Further, the abnormality detecting means includes a first pulse synchronized with a rising timing of the control signal from a low level to a high level and a second pulse synchronized with a falling timing of the control signal from a high level to a low level. Generating a first test signal by generating a pulse and latching the test signal in synchronization with successive pulses of the first and second pulses; A second test signal is generated by further latching in synchronization with the inverted pulse of the second control pulse, and the first and second test signals are compared to output a match / mismatch signal output from the first and second test signals. The latch is latched in synchronization with the continuous pulse of the second pulse, and the latch output becomes constant at a low level if the match / mismatch signal is a mismatch signal. Configured to be a high level constant of said alarm signal if Re.

Further, the abnormality notifying means includes an n-channel MOS transistor having the driving capability increased by inputting the alarm signal to the gate electrode, connecting the drain electrode to the power supply potential and the source electrode to the ground potential. When the alarm signal is at the high level, it conducts to short-circuit the power supply potential and the ground potential.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described first with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. Referring to FIG. 1, dynamic B
A dynamic BT test apparatus 1 installed outside a constant temperature test tank for performing T, a driver circuit unit 2 built in the BT test apparatus 1 for generating a test signal A and a control signal B, and a semiconductor device 4 to be tested The control signal B output from the driver circuit unit 2 and the test signal A at the terminal end of the test signal wiring 101 respectively wired to the group of test substrates 3 are compared with each other, and A clock abnormality detection circuit section 5 having abnormality detection means for generating an alarm signal using the mismatch signal of the comparison result, and n of abnormality notification means for notifying abnormality in response to the alarm signal supplied from the abnormality detection circuit 5 An output terminal OU of the driver circuit unit 2.
T1 is connected to each signal input terminal of the semiconductor device 4 by a signal line 101 of a test signal A wired so as to go around in the test substrate 3.

After the signal line 101 goes around the inside of the BT test board 3 and is connected to the signal input terminal of each semiconductor device 4, the terminal thereof is terminated at the input terminal IN of the clock abnormality detection circuit section 5.
3 is connected.

The input terminal IN4 of the clock abnormality detection circuit 5
Is connected to a signal line 102 of a control signal B supplied from the driver circuit unit 2 through an input terminal IN2, and an output terminal OUT3 of the signal line 103 is connected to a gate electrode of an n-channel MOS transistor 6 by an alarm signal C. Connected and configured.

Referring to FIG. 2 showing an example of a circuit diagram of the clock abnormality detection circuit section 5, a test signal A is input to a data input terminal D of a latch circuit 51 having a set terminal, and an output terminal Q of the latch circuit 51 is provided. Is connected to the data input terminal D of the next-stage latch circuit 52 and one input terminal of the EX-NOR circuit 56, and the other input terminal of the EX-NOR circuit is connected to the output terminal Q of the latch circuit 52. . EX-NOR
The output terminal of the circuit is connected to the data input terminal D of the latch circuit 57. The output terminals of the EX-OR circuit 54 are directly connected to the clock input terminals G of these latch circuits 51 and 57, connected to the latch circuit 52 via an inverter 55, and the input terminals of the EX-OR circuit 54 are A control signal B and a signal obtained by passing this signal through a delay circuit 53 are input.

Further, a power-on reset signal P-ON is inputted to set terminals of the latch circuits 51, 52 and 57, and an alarm signal C is outputted from an output terminal Q of the latch path 57.

FIG. 2 shows an example of a circuit diagram of a latch circuit.
Referring to (b), the data input terminal D is a p-channel type M
The input terminal of the inverter 513 is connected to the input terminal of the inverter 513 via the transfer gate including the OS transistor 511 and the n-channel type MOS transistor 512, and the output terminal is NO.
The set terminal S is connected to one input terminal of the R circuit 514 and the other input terminal. An output terminal of the NOR circuit 514 is connected to the output terminal Q and a p-channel type MO.
It is connected to the input terminal of inverter 513 via a transfer gate composed of S transistor 515 and n-channel MOS transistor 516. Control signal input terminal G
Is directly connected to the gate terminals of a p-channel MOS transistor 515 and an n-channel MOS transistor 516,
It is connected to the gate electrodes of the transistor 511 and the n-channel MOS transistor 516, and inputs and latches data when the control signal is at a high level.

FIG. 2 shows an example of a circuit diagram of the delay circuit.
Referring to (c), a plurality of inverters 531 are connected in cascade, and a capacitor 532 is connected between each output terminal and the ground potential.

In the BT device having the above configuration,
The test signal A output from the driver circuit section 2 circulates in the test substrate 3 and is supplied to the input terminal of each semiconductor device 4, thereby performing a test while dynamically operating these semiconductor devices.

That is, as described above, the test substrate 3 is set in the constant temperature test tank, and the test substrate 3 is energized and the test signal A is also supplied. Further, the temperature in the constant temperature test chamber is raised to the test temperature, and the temperature is maintained, and the apparatus is left for a period specified for the test. After this test period has elapsed, the test substrate 3 is taken out of the constant temperature test tank, and
The semiconductor device 4 is taken out of the socket and an electrical characteristic test is performed by an LSI tester or the like within a short time.

Referring to FIG. 2 and FIG. 3 showing a timing chart for explaining the operation during normal operation, the control signal B supplied to the clock abnormality detection circuit 5 is a test signal A.
The rising timing from the low level to the high level is a signal delayed by a predetermined time phase from the test signal A, and is set to have a period in which the high level and the low level periods always overlap each other. ing.

The control signal B is compared with the signal B0 delayed by the delay circuit 53 by the EX-OR circuit 54, and the pulse B11 synchronized with the rising timing of the control signal B and the falling timing of the control signal B are compared. The control signal B1 is composed of a pulse B12 synchronized with the control signal B1.
Latched to 1. That is, the high level of the test signal A is detected by the pulse B11, the low level of the test signal A is detected by the pulse B12, and the signal A1 synchronized with the control signal B is output from the output terminal Q of the latch circuit 51. .

The signal A1 is further latched by the latch circuit 52 with an inverted signal of the control signal B1, whereby
The signal A2 synchronized with the control signal B is output from the output terminal Q of the latch circuit 52 with the phases delayed by the pulse widths of the pulses B11 and B12.

These synchronized signals A1 and A2
Is compared by the EX-NOR circuit 56 to obtain a detection signal C0 including a pulse C01 synchronized with the rising timing of the signal A1 and a pulse C02 synchronized with the falling timing of the control signal A1. That is, C0 is composed of a pulse C01 that detects the high level period of the test signal A and a pulse C02 that detects the low level period.

The detection signal C0 is latched again by the control signal B1. At this time, the pulse C0 of the detection signal C0
1 and C02 correspond to the inverter 3 with respect to the control signal B1.
5, the detection signal C01 is still at the low level during the high level period of the pulse B11 of the control signal B because the phase is reliably delayed by the delay of the circuit elements of the latch circuit 52 and the EX-NOR circuit 56. During the high level period of the pulse B12 of the control signal B, the detection signal C0
Since 2 is still in the low level period, the low level is latched by the latch circuit 57 and the low level is continuously output.

That is, if the test signal A is normally supplied to each semiconductor device 4, the alarm signal C output from the latch circuit 57 is maintained at a low level, and n
The channel type MOS transistor 6 does not conduct.

Referring to FIG. 2 and FIG. 4 showing a timing chart for explaining the operation when the supply of the test signal A is abnormal, if the signal line 101 is disconnected in the test board 3, When the potential of the test signal A output from the driver circuit unit 2 is fixed at the low level due to the insertion error of the test signal A, the rising timing of the test signal A from the low level to the high level is higher than the test signal A as described above. Is also a signal delayed in phase by a predetermined time, and is set to have a period in which the high-level period and the low-level period always overlap each other.

However, if the potential is fixed at a low level due to an abnormality such as a disconnection, the control signal B is equal to the signal B0 delayed by the delay circuit 53 similarly to the above-described normal state regardless of the abnormality of the test signal A. Is compared by the EX-OR circuit 54 to obtain a control signal B composed of a pulse B11 synchronized with the rising timing of the control signal B and a pulse B12 synchronized with the falling timing of the control signal B.
The test signal A is first latched in the latch circuit 51 by the control signal B1.

That is, the high level of the test signal A is detected by the pulse B11, the low level of the test signal A is detected by the pulse B12, and the signal A1 synchronized with the control signal B is output from the output terminal Q of the latch circuit 51. Is output. At this time, since the test signal A in the drawing is fixed at the low level after the second high level, the output signal A1 of the latch circuit 51 is at the low level during the period corresponding to the second and subsequent test signals A. Output.

The signal A1 is further latched in the latch circuit 52 by an inverted signal of the control signal B1, so that the test signal A is synchronized with the control signal B in a state where the phases are delayed by the pulse widths of the pulses B11 and B12.
, The detection signal A2 latched at the low level by the control signals B13 and B14 is output from the output terminal Q of the latch circuit 52.

These synchronized signals A1 and A2
Are compared by the EX-NOR circuit 56, and the pulse C01 synchronized with the rising timing of the signal A11 and the pulse C0 synchronized with the falling timing of the control signal A11 are compared.
2 and the period after C02 is a high-level detection signal C0.

That is, the signal C0 includes a detection signal A1 in which the high level period of the test signal A is detected at the rising timing of the control signal B11 and the low level of the test signal A is detected at the rising timing of the control signal B12. The detection signal A, which detects the high level period of the signal A1 at the falling timing of the control signal B11 and detects the low level of the detection signal A1 at the falling timing of the control signal B12.
Since the output is compared with 2, the pulses corresponding to C01 and C02 do not appear during the period when the low level is fixed.

The detection signal C0 is latched again by the control signal B1, but during the period when the test signal A is abnormal and fixed at the low level, the output of the latch circuit 57 is the control signal because the detection signal C0 is at the high level. At the rising timing of B13, the high level is latched and the high level is output.

That is, in an abnormal state where the test signal A is not supplied to each semiconductor device 4, the alarm signal C output from the latch circuit 57 is maintained at a high level, the n-channel MOS transistor 6 is turned on, A large through current flows from the power supply potential to the ground potential. Therefore, it is necessary to set a large driving capability of this transistor so as not to be destroyed by this through current.

A large current caused by the above-mentioned abnormal condition is detected by an overcurrent detection circuit built in the BT test apparatus 1 arranged outside the constant temperature test tank, and the power supply to the test board 3 is stopped.

The case where the test signal A is fixed at a high level in the test board 3 due to some mistake will be described. With reference to FIG. 2 and FIG. 5 showing a timing chart for explaining the operation of fixing the high level, if the potential of the test signal A is fixed to the high level due to the abnormality,
The control signal B becomes a control signal B1 including a pulse B11 synchronized with the rising timing of the control signal B and a pulse B12 synchronized with the falling timing of the control signal B. 51, the high level of the test signal A is detected by the pulse B11, the low level of the test signal A is detected by the pulse B12, and the signal A1 is output from the output terminal Q of the latch circuit 51.

At this time, for example, if the test signal A is fixed at the high level after the second high level after the initialization, the output signal A1 of the latch circuit 51 also becomes the second or higher level of the test signal A. The corresponding period is a high level output. The signal A1 is further latched by the latch circuit 52 with an inverted signal of the control signal B1, whereby
From the second end of the test signal A synchronized with the control signal B, the detection signal A2 whose high level is latched by the control signals B13 and B14 is output from the output terminal Q of the latch circuit 52.

These synchronized signals A1 and A2
Are compared by the EX-NOR circuit 56, and the pulse C synchronized with the rising timing of the signals A12 and A21 is
The period after the pulses C02 and C03 synchronized with the falling timings of the control signals A12 and A21 and the control signals A12 and A21 becomes the detection signal C0 which becomes the high level. That is, no pulses corresponding to C01, C02 and C03 appear during the period in which the high level is fixed.

The detection signal C0 is latched again by the control signal B1, but during the period when the test signal A is abnormal and fixed at the high level, the output of the latch circuit 57 is controlled because the detection signal C0 is at the high level. At the rising timing of the signal B14, the high level is latched and the high level is output.

That is, even during the period when the test signal A is fixed at the high level, the alarm signal C output from the latch circuit 57 is maintained at the high level, the n-channel MOS transistor 6 is turned on, and the power supply potential is changed. A large through current flows to the ground potential.

As is apparent from the above description of the present embodiment, when the wiring of the test signal is broken in the test board, when the test signal is fixed to the low level due to the board insertion error, If an abnormal state occurs, such as when the test signal is fixed at the high level, the abnormal state is detected in the test board and the power supply to the test board is stopped, so that the normal BT test is not performed. The semiconductor device can be prevented from being shipped in the state.

[0043]

As described above, the BT device of the semiconductor device according to the present invention generates a test signal and a control signal whose phase is delayed by a predetermined time from the test signal, and tests these signals. A driver circuit section to be supplied to the board group, a control signal output from the driver circuit section, and a test signal at a terminal end of a test signal wiring wired to a signal input terminal of a semiconductor device in the test board group are input. The high level period of the logic level of the test signal is compared at the rising timing of the control signal from the low level to the high level, and the low level period of the test signal is compared at the timing of the falling of the control signal from the high level to the low level. If the comparison result does not match, an alarm signal indicating an abnormal state in which the test signal is fixed at high level or low level is generated. A clock abnormality detection circuit unit having an abnormality detection unit, and an abnormality notification unit for notifying an abnormality in response to the abnormality detection unit, wherein the clock abnormality detection circuit unit and the abnormality notification unit are respectively incorporated in a test board. With such a configuration, normal BT can be performed, and therefore, a semiconductor device whose initial failure is not accelerated can be prevented from being shipped, and reliability can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating an example of a clock abnormality detection circuit unit in FIG. 1;

FIG. 3 is a timing chart for explaining an operation when a test signal is normally distributed.

FIG. 4 is a timing chart for explaining an operation when a test signal is fixed at a low level.

FIG. 5 is a timing chart for explaining the operation when the test signal is fixed at a low level.

FIG. 6 is a block diagram illustrating a configuration of an example of a conventional burn-in device.

[Description of Signs] 1 BT test apparatus 2 driver circuit 3 test board 4 semiconductor device 5 clock abnormality detection circuit unit 6 n-channel MOS transistor 51, 52, 57 latch circuit 53 delay circuit 511, 515 p-channel MOS transistor 512, 516 n-channel MOS transistor 513, 517, 531 inverter 514 NOR circuit 532 capacitance element A test signal B control signal C alarm signal IN1 input terminal of test signal A of test board IN2 input terminal of control signal B of test board IN3 clock abnormality Input terminal of test signal A of detection circuit unit IN4 Input terminal of control signal B of clock abnormality detection circuit unit OUT1 Output terminal of test signal A of driver circuit unit OUT2 Output terminal of control signal B of driver circuit unit OUT3 Clock abnormality detection circuit Alarm signal C
Output end of

Claims (3)

(57) [Claims] 1. A test board group on which a plurality of semiconductor devices are mounted is housed in a constant temperature test tank for detecting an initial failure of the semiconductor device, and a predetermined test signal is supplied to the semiconductor device in the constant temperature test tank. In a burn-in test apparatus for a semiconductor device in which a defective state is accelerated by continuously operating in a predetermined high temperature atmosphere for a predetermined time, the test signal and a control signal whose phase is delayed by a predetermined time from the test signal are compared. A driver circuit unit that generates and supplies these signals to the test board group; a test signal that is output from the driver circuit unit; and a test that is wired to a signal input terminal of the semiconductor device in the test board group. The test signal at the end of the signal wiring is input, and a high level period of the logic level of the test signal is changed from a low level of the control signal to a low level. The control signal is compared at the rising timing to the high level, and the low level period of the test signal is compared at the falling timing from the high level to the low level of the control signal. If the comparison result is inconsistent, the test signal is at the high level. Or a clock abnormality detection circuit unit having abnormality detection means for generating an alarm signal of an abnormal state fixed to a low level, and abnormality notification means for notifying an abnormality in response to the abnormality detection means, A burn-in test apparatus for a semiconductor device, wherein the clock abnormality detection circuit unit and the abnormality notification unit are respectively incorporated. 2. The abnormality detecting means includes: a first pulse synchronized with a rise timing of the control signal from a low level to a high level; and a second pulse synchronized with a fall timing of the control signal from a high level to a low level. Generating a first pulse and latching the test signal in synchronization with a continuous pulse of the first and second pulses.
The second test signal is generated by further latching the first test signal in synchronization with the inverted pulse of the first and second control pulses, thereby generating the first and second test signals. 2 is latched in synchronization with the continuous pulse of the first and second pulses, and the latch output is at a low level if the match / mismatch signal is a mismatch signal. 2. The semiconductor burn-in test apparatus according to claim 1, wherein the alarm signal is constant, and if it is a coincidence signal, the alarm signal is constant at a high level. 3. The abnormality notification means comprises an n-channel MOS transistor having a driving capability increased by inputting the alarm signal to a gate electrode, connecting a drain electrode to a power supply potential and a source electrode to a ground potential. 2. The burn-in test apparatus for a semiconductor device according to claim 1, wherein said alarm signal is turned on when said alarm signal is at a high level to short-circuit between a power supply potential and a ground potential.