CN113205763B - Start control module, start control method and display device - Google Patents
Start control module, start control method and display device Download PDFInfo
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- CN113205763B CN113205763B CN202110552585.8A CN202110552585A CN113205763B CN 113205763 B CN113205763 B CN 113205763B CN 202110552585 A CN202110552585 A CN 202110552585A CN 113205763 B CN113205763 B CN 113205763B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0271—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping
- G09G2320/0276—Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/06—Adjustment of display parameters
- G09G2320/0673—Adjustment of display parameters for control of gamma adjustment, e.g. selecting another gamma curve
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Abstract
The invention provides a start control module, a start control method and a display device. The starting control module is applied to a display device, and the display device comprises a power management integrated circuit, a time schedule controller and a source electrode driving integrated circuit; the starting control module comprises a control circuit; the control circuit is used for controlling the power management integrated circuit to provide gamma main voltage to the source electrode driving integrated circuit after the time schedule controller provides input signals to the source electrode driving integrated circuit; the input signals include an input data signal and a data sampling clock signal. The invention solves the problem of black screen caused by abnormal output of the source electrode driving integrated circuit due to the condition that the gamma main voltage reaches the source electrode driving integrated circuit before the input signal in the prior art.
Description
Technical Field
The invention relates to the technical field of display, in particular to a start control module, a start control method and a display device.
Background
In the prior art, transistors in a source drive integrated circuit have the problem of leakage current inevitably, and the existence of the leakage current is often a cause of many defects.
The conventional source driver ic generally indicates that the power supply voltage is required to be powered up no later than the input Signal (e.g., a CEDS (Clock Embedded Differential Signal), and the power-up timing of the gamma main voltage AVDD and the input Signal is not required. Therefore, the conventional power-on sequence (the power-on sequence refers to the sequence in which voltages are provided to the source driver integrated circuit) generally includes first supplying a power voltage, then supplying the AVDD, and then supplying the input signal, so that the input signal is in a floating state during the period from the AVDD power-on to the input signal power-on. At this time, the transistor in the sampling module inside the source driver ic may output abnormal logic due to the existence of the leakage current, which may cause the source driver ic to operate abnormally. In a high-temperature environment, an abnormality in the generation of a leakage current is more likely to occur. And because the display screen with the CEDS interface has a Lock (locking) cascade mechanism among the source driver integrated point circuits, the abnormality of a certain COF (chip on film, on which the source driver integrated circuit is disposed) in the cascade mechanism can cause that all COFs can not normally receive CEDS signals sent by a TCON (timing controller), and the display screen with the CEDS interface is represented as a black screen defect.
Disclosure of Invention
The invention mainly aims to provide a start control module, a start control method and a display device, which solve the problem of black screen caused by abnormal output of a source drive integrated circuit due to the fact that gamma main voltage AVDD reaches the source drive integrated circuit before an input signal in the prior art.
The embodiment of the invention provides a starting control module which is applied to a display device, wherein the display device comprises a power management integrated circuit, a time schedule controller and a source electrode driving integrated circuit; the starting control module comprises a control circuit;
the control circuit is used for controlling the power management integrated circuit to provide gamma main voltage to the source electrode driving integrated circuit after the time schedule controller provides input signals to the source electrode driving integrated circuit;
the input signals include an input data signal and a data sampling clock signal.
Optionally, the input signal is a clock-embedded differential CEDS signal.
Optionally, the control circuit comprises a signal correlation circuit and an output adjustment circuit, wherein,
the signal correlation circuit is used for generating a control signal after the time schedule controller provides an input signal to the source electrode driving integrated circuit, and providing the control signal to the output adjusting circuit through a control signal end;
the output adjusting circuit is electrically connected with the control signal terminal and is used for controlling the gamma main voltage to be supplied to the source electrode driving integrated circuit under the control of the control signal.
Optionally, the timing controller includes a V-By-One signal receiving interface, a conversion circuit and a CEDS signal sending interface;
the V-By-One signal receiving interface is used for receiving a V-By-One signal;
the conversion circuit is respectively electrically connected with the V-By-One signal receiving interface and the CEDS signal sending interface, and is used for converting the V-By-One signal into a CEDS signal and outputting the CEDS signal;
the CEDS signal transmitting interface is electrically connected with the source electrode driving integrated circuit and used for outputting the CEDS signal to the source electrode driving integrated circuit;
the signal correlation circuit is electrically connected with the conversion circuit and used for generating the control signal after the conversion circuit outputs the CEDS signal; or, the signal correlation circuit is electrically connected to the CEDS signal transmission interface, and is configured to generate the control signal after the CEDS signal transmission interface outputs the CEDS signal to the source driver integrated circuit.
Optionally, the output adjusting circuit is disposed outside the power management integrated circuit.
Optionally, the output adjusting circuit includes an output control transistor;
a control electrode of the output control transistor is electrically connected with the control signal end, a first electrode of the output control transistor is electrically connected with a gamma main voltage output end of the power management integrated circuit, and a second electrode of the output control transistor is electrically connected with the source electrode driving integrated circuit;
the power management integrated circuit outputs the gamma main voltage through the gamma main voltage output terminal.
Optionally, the control circuit includes a signal generation control circuit and an output adjustment circuit;
the signal generation control circuit is used for controlling the generation of a control signal to the output adjusting circuit through a level conversion circuit included in the timing controller or the display device after the timing controller provides an input signal to the source drive integrated circuit;
the output adjusting circuit is used for controlling the gamma main voltage to be supplied to the source electrode driving integrated circuit under the control of the control signal.
Optionally, the power management integrated circuit includes an analog positive voltage generating circuit;
the control circuit is used for providing an enabling signal for the analog positive voltage generating circuit after the time schedule controller provides an input signal to the source electrode driving integrated circuit;
the analog positive voltage generating circuit is used for generating the gamma main voltage after receiving the enabling signal and providing the gamma main voltage to the source electrode driving integrated circuit.
The embodiment of the present invention further provides a start control method, which is applied to the start control module, and the start control method includes:
after the timing controller provides the input signal to the source driving integrated circuit, the control circuit controls the power management integrated circuit to provide the gamma main voltage to the source driving integrated circuit.
The embodiment of the invention also provides a display device which comprises the starting control module.
According to the start control module, the start control method and the display device, the time schedule controller controls the power management integrated circuit to provide the gamma main voltage AVDD to the source driving integrated circuit after providing the input signal to the source driving integrated circuit through the control circuit, the power-on time of the AVDD received by the source driving integrated circuit can be guaranteed to be later than that of the input signal received by the source driving integrated circuit, the situation that the AVDD reaches the source driving integrated circuit before the input signal is avoided, and the black screen caused by abnormal output of the source driving integrated circuit is avoided.
Drawings
Fig. 1 is a structural diagram of a control circuit in a start control module according to an embodiment of the present invention;
fig. 2 is a structural diagram of a control circuit in the start control module according to an embodiment of the present invention;
fig. 3 is a schematic diagram illustrating a connection relationship among a timing controller, a power management integrated circuit, and a source driver integrated circuit in a display device to which the start control module according to an embodiment of the present invention is applied;
FIG. 4 shows a power-up sequence of the relevant signals of FIG. 3;
FIG. 5 is a circuit diagram of one embodiment of an output adjust circuit;
FIG. 6 is a diagram of a DVDD1V8 signal D1, a gamma main voltage AVDD, a CEDS signal S1, and a Lockout signal L1 after the control module is activated according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a receiving terminal of a source driver IC;
fig. 8 is a schematic diagram of the internal logic of the sampling module.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The transistors used in all embodiments of the present invention may be transistors, thin film transistors, or field effect transistors or other devices with the same characteristics. In the embodiment of the present invention, in order to distinguish two poles of the transistor except the control pole, one pole is called a first pole, and the other pole is called a second pole.
In practical operation, when the transistor is a triode, the control electrode may be a base electrode, the first electrode may be a collector electrode, and the second electrode may be an emitter electrode; alternatively, the control electrode may be a base electrode, the first electrode may be an emitter electrode, and the second electrode may be a collector electrode.
In practical operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode; alternatively, the control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
The start control module is applied to a display device, and the display device comprises a power management integrated circuit, a time schedule controller and a source electrode driving integrated circuit; the starting control module comprises a control circuit;
the control circuit is used for controlling the power management integrated circuit to provide gamma main voltage to the source electrode driving integrated circuit after the time schedule controller provides input signals to the source electrode driving integrated circuit;
the input signals include an input data signal and a data sampling clock signal.
According to the start control module, the time schedule controller is used for controlling the power management integrated circuit to provide the gamma main voltage AVDD to the source electrode driving integrated circuit after providing the input signal to the source electrode driving integrated circuit through the control circuit, so that the power-on time of the AVDD received by the source electrode driving integrated circuit is ensured to be later than that of the input signal received by the source electrode driving integrated circuit, the situation that the AVDD reaches the source electrode driving integrated circuit before the input signal is avoided, and the black screen caused by abnormal output of the source electrode driving integrated circuit is avoided.
Optionally, the input Signal is a CEDS (Clock Embedded Differential Signal) Signal, but not limited thereto.
As shown in fig. 1, the control circuit may include a signal correlation circuit 11 and an output adjustment circuit 12, wherein,
the signal correlation circuit 11 is configured to generate a control signal after the timing controller provides an input signal to the source driver integrated circuit, and provide the control signal AVDD _ EN to the output adjustment circuit 12 through a control signal terminal;
the output adjusting circuit 12 is electrically connected to the control signal terminal, and is configured to control to provide the gamma main voltage to the source driver integrated circuit 10 under the control of the control signal AVDD _ EN.
Alternatively, as shown in fig. 2, the signal correlation circuit 11 may be integrated in the timing controller 21, and the output adjustment circuit 12 may be integrated in the power management integrated circuit 22;
the timing controller 21 supplies the input signal, which may be a CEDS signal, to the source driving integrated circuit 10.
In at least One embodiment of the present invention, the timing controller may include a V-By-One signal receiving interface, a converting circuit, and a CEDS signal transmitting interface;
the V-By-One signal receiving interface is used for receiving a V-By-One signal;
the conversion circuit is respectively electrically connected with the V-By-One signal receiving interface and the CEDS signal sending interface, and is used for converting the V-By-One signal into a CEDS signal and outputting the CEDS signal;
the CEDS signal transmitting interface is electrically connected with the source electrode driving integrated circuit and used for outputting the CEDS signal to the source electrode driving integrated circuit;
the signal correlation circuit is electrically connected with the conversion circuit and used for generating the control signal after the conversion circuit outputs the CEDS signal; or, the signal correlation circuit is electrically connected to the CEDS signal transmission interface, and is configured to generate the control signal after the CEDS signal transmission interface outputs the CEDS signal to the source driver integrated circuit.
The V-by-One is a digital interface standard developed specially for image transmission.
In a specific implementation, the timing controller may receive the V-By-One signal, and then the conversion circuit converts the V-By-One signal into a CEDS signal, and outputs the CEDS signal to the source driver through the CEDS signal transmission interface. In this case, the signal correlation circuit may be disposed at the rear end of the conversion circuit, or the signal correlation circuit may be disposed at the rear end of the CEDS signal transmission interface, and both cases may enable the signal correlation circuit to output the control signal AVDD _ EN by taking the CEDS signal as an input.
As shown in fig. 3, the timing controller 21 includes a V-By-One signal receiving interface Rx, a converting circuit 30, and a CEDS signal transmitting interface Tx;
the conversion circuit 30 is electrically connected to Rx and Tx, respectively, for converting the V-By-One signal from Rx into a CEDS signal and outputting the CEDS signal to the source driver integrated circuit 10 through Tx;
the control circuit comprises a signal correlation circuit 11 and an output adjusting circuit 12;
the signal correlation circuit 11 is disposed in the timing controller 21, and the output adjustment circuit 12 is disposed in the power management integrated circuit 22;
in the power management integrated circuit 22, an output adjusting circuit 12 is disposed at the rear end of an AVDD generating circuit 221 (the AVDD generating circuit 221 is configured to generate a gamma main voltage), and the output adjusting circuit 12 adjusts the time when the gamma main voltage AVDD reaches the source driver integrated circuit 10 according to a control signal AVDD _ EN provided by the signal relating circuit 11, so that the AVDD received by the source driver integrated circuit 10 is powered on no earlier than the time when the CEDS signal is powered on;
the signal correlation circuit 11 is arranged in the timing controller 21; the signal correlation circuit 11 is added at the rear end of the conversion circuit 30; the signal correlation circuit 11 generates the control signal AVDD _ EN (in at least one embodiment shown in fig. 3, AVDD _ EN may be a high voltage signal), and the AVDD _ EN generated by the signal correlation circuit 11 is controlled by the CEDS signal output by the conversion circuit 30, so that the generation time of AVDD _ EN can be conveniently controlled after the CEDS signal is powered on;
when the output adjusting circuit 12 receives AVDD _ EN, the gamma main voltage AVDD can be output to the rear-end source driver ic 10, that is, the time when the source driver ic 10 receives AVDD is not earlier than the time when the source driver ic 10 receives the CEDS signal, and at this time, after the AVDD inside the source driver ic 10 is powered on, the CEDS signal floating state does not exist, so that the internal logic state of the source driver ic 10 is clear, and the black screen phenomenon caused by leakage current does not occur.
When the start control module according to at least one embodiment of the present invention shown in fig. 3 is operated, the Tx signal is delayed after sending the CEDS signal S1 to the source driver ic 10 by the code setting in the timing controller 21, and the control signal AVDD _ EN is regenerated after a certain time.
In a specific implementation, the period of time may be controlled to be less than or equal to 1000ms in order to avoid the delay time of the start-up.
In at least one embodiment shown in fig. 3, the power management integrated circuit 22 may further include a first voltage generation module 31, a second voltage generation module 32, and a third voltage generation module 33;
the first voltage generating module 31 is configured to generate a DVDD3V3 signal and provide the DVDD3V3 signal to the timing controller 21; DVDD3V3 is the supply voltage for the timing controller;
the second voltage generating module 32 is configured to generate a DVDD1V8 signal and provide the DVDD1V8 signal to the timing controller 21; DVDD1V8 is the supply voltage for the timing controller and the source driver integrated circuit;
the third voltage generating module 33 is used for generating other voltage signals such as HAVDD, VGH, VGL, and the like.
The HAVDD is a supply voltage of a negative OP (operational amplifier) in the source driver integrated circuit. VGH is a high voltage signal and VGL is a low voltage signal.
Fig. 4 shows a power-up timing of the relevant signals in fig. 3.
In fig. 4, reference numeral AVDD _ int denotes a gamma main voltage generated by the AVDD generation circuit 221, S1 denotes a CEDS signal transmitted from the CEDS signal transmission interface Tx to the source driver ic 10, AVDD _ EN denotes a control signal, and AVDD denotes a gamma main voltage supplied from the power management ic 22 to the source driver ic 10; POR is power-on reset signal, D1 is DVDD1V8 signal, L1 is Lockout signal.
In fig. 4, the CEDS signal S1 is powered on for a period of time indicated by oblique lines.
As shown in fig. 4, the power management integrated circuit 22 supplies the gamma main voltage AVDD to the source drive integrated circuit 10 after Tx sends the CEDS signal S1 to the source drive integrated circuit 10; the power-on reset signal POR is powered on along with AVDD.
In fig. 4, the Lockout signal is an output signal of the Source Driver IC, in the Lock cascade mechanism, the Lockout signal of the Source Driver IC is a Lockin signal of the next Source Driver IC, the Lockin signal of the first Source Driver IC is provided by a front end input, the Lockout signal of the last Source Driver IC is fed back to the timing controller, and only when the timing controller receives the Lockout signal of the last Source Driver IC, the cascade mechanism Ready is considered and the next operation can be performed.
In specific implementation, the signal correlation circuit 11 may be disposed outside the timing controller 21, and may be inputted with one or some of the CEDS signals outputted from the timing controller to generate the required AVDD _ EN, so that the timing controller does not need to be modified by hardware.
Preferably, the output regulation circuit may be disposed outside the power management integrated circuit, so that the power management integrated circuit does not need to be modified in hardware.
When the output regulation circuit is disposed outside the power management integrated circuit, the output regulation circuit may include an output control transistor;
the control electrode of the output control transistor is electrically connected with the control signal end, the first electrode of the output control transistor is electrically connected with the gamma main voltage output end of the power management integrated circuit, and the second electrode of the output control transistor is electrically connected with the source electrode driving integrated circuit;
the power management integrated circuit outputs the gamma main voltage through the gamma main voltage output terminal.
As shown in fig. 5, the output adjustment circuit includes an output control transistor T0;
a grid electrode of the T0 is connected to a control signal AVDD _ EN, a first pole of the T0 is electrically connected with a terminal of the power management integrated circuit 22 for outputting a gamma main voltage, and a second pole of the T0 provides the gamma main voltage AVDD for the source electrode driving integrated circuit;
when the signal correlation circuit provides AVDD _ EN, T0 is turned on to provide the gamma main voltage to the source driver integrated circuit 10.
In fig. 5, D1 is a DVDD1V8 signal, and D2 is a DVDD3V3 signal.
In the embodiment shown in fig. 5, T0 may be a transistor, a thin film transistor, or a field effect transistor, but is not limited thereto.
In actual operation, the Gamma main voltage AVDD may also enter a P-Gamma IC (programmable Gamma voltage generation integrated circuit) or other circuits. When the AVDD has a plurality of flow directions, only one path from the AVDD to the source driving integrated circuit can be adjusted. For the P-Gamma IC, AVDD is used as input to generate a plurality of Gamma reference voltages, and the generated Gamma reference voltages are also input to the source drive integrated circuit, so that the Gamma reference voltages can not reach the source drive integrated circuit earlier than CEDS, that is, the AVDD used as the input of the P-Gamma IC is also preferably adjusted together with the AVDD entering the source drive integrated circuit.
In a specific implementation, the power management integrated circuit may provide AVDD to the source driver integrated circuit at the same time as providing AVDD to the source driver integrated circuit, but the invention is not limited thereto.
In specific implementation, the power management integrated circuit comprises an analog positive voltage generating circuit;
the control circuit is used for providing an enabling signal for the analog positive voltage generating circuit after the time schedule controller provides an input signal to the source electrode driving integrated circuit;
the analog positive voltage generating circuit is used for generating the gamma main voltage after receiving the enabling signal and providing the gamma main voltage to the source electrode driving integrated circuit.
Inside the PMIC (power management integrated circuit), the generated analog positive voltage includes AVDD, HAVDD, and VGH. These signals have a certain correlation with the power-on timing when the display device is turned on. The generation circuit of these voltages has a uniform enable signal, and these signals can be generated only when the enable signal is set high. When the output timing of AVDD is adjusted inside the PMIC, AVDD _ EN may be used as an enable signal of the entire analog positive voltage generation circuit to control the analog positive voltage generation circuit to generate AVDD, HAVDD, and VGH.
In particular implementations, the control circuit may include a signal generation control circuit and an output adjustment circuit;
the signal generation control circuit is used for controlling the generation of a control signal to the output adjusting circuit through a level conversion circuit included in the timing controller or the display device after the timing controller provides an input signal to the source drive integrated circuit;
the output adjusting circuit is used for controlling the gamma main voltage to be supplied to the source electrode driving integrated circuit under the control of the control signal.
In specific implementation, in order to solve the problem of black screen starting of the display device caused by the leakage current of the internal transistor of the Source Driver IC, it is required to meet the requirement that the time for supplying the AVDD to the Source Driver IC is not earlier than the time for supplying the CEDS signal to the Source Driver IC. In order to conveniently use an idle pin inside a TCON (time schedule controller) to realize the function, through debugging of TCON codes, after the time schedule controller provides a CEDS signal to the source electrode driving integrated circuit, a pin of the time schedule controller provides a control signal to an output adjusting circuit, so that the time schedule controller does not need to make any hardware change.
Alternatively, the control signal may be generated by a Level Shift (Level Shift circuit) or other module included in the display device.
For the poor high-temperature starting black screen of the B9 65 full screen, the following scheme is proved to be effective and practical (change is minimum): through adjusting TCON (time sequence controller) Code, make to produce suitable control signal AVDD _ EN on CLK10pin (pin) of TCON, connect AVDD _ EN to the enable signal end of PMIC (power management integrated circuit)'s whole analog circuit voltage generation module, replace original enable signal, unify the regulation analog circuit signal to make the bad phenomenon of high temperature start-up black screen no longer take place. The DVDD1V8 signal D1, the gamma main voltage AVDD, the CEDS signal S1 and the Lockout signal L1 after the scheme is used are shown in FIG. 6; the CEDS signal S1 and the Lockout signal L1 both correspond to the first source driver integrated circuit in the cascade.
In fig. 6, the CEDS signal S1 is powered on for a period of time indicated by oblique lines.
In the related art, since a Lock cascade mechanism exists between source driver integrated circuits in a display screen having a CEDS structure, and a certain COF (chip on film) in the cascade mechanism is provided with the source driver integrated circuits, an abnormality of the certain COF in the cascade mechanism may cause that all COFs cannot normally receive CEDS signals sent by TCON, which may be represented as a black screen defect. After the power supply voltage DVDD1V8 of the source driver integrated circuit is powered on, the source driver integrated circuit starts to operate. During the power-up of AVDD to CEDS, the CEDS signal is in Floating state. In the power-on period, the source driver ic cannot analyze the internal clock signal according to the CEDS signal, so that the internal logic of the driver ic defaults that the potential of the clock signal is low.
Fig. 7 is a schematic diagram of a receiving terminal of the source driver ic. In fig. 7, vinp is a positive input signal of the CEDS differential signal, vinn is a negative input signal of the CEDS differential signal, vinp and Vinn are resolved into a digital input signal Din by an AFE (analog front end) module 71, a sampling module 72 converts Din into a digital data signal, a clock recovery module 73 converts Din into a digital clock signal (the digital clock signal may be a digital data sampling clock signal), a LOCK detect module 74 converts the digital data signal and the digital clock signal into a first LOCK signal lockki and a second LOCK signal lockpad, LOCK PAD is a Lockout signal generated by the source driver integrated circuit, the Lockout signal is used as a cascade among a plurality of source driver integrated circuits, and LOCK PAD may be regarded as an appearance of LOCK PAD inside the source driver integrated circuit. When the source driving integrated circuit works normally, the LOCKi and the LOCK _ PAD are required to be consistent.
Fig. 8 is a schematic diagram of the internal logic of the sampling module, which is illustrated by the 0 th bit of each digital signal. In normal operation, the 0 th bit digital clock signal CK [0 ]]Will change, the 0 th bit digital data signal D [0 ]]Follow Din. When CK [0 ]]When the voltage level of (d) is low, it can be known from the logic of the sampling module that MP2 and MN4 are both in the closed state, and the Db point is in the floating state. If CK [0 ]]The voltage of Db is in a floating state for a long time, and the leakage current of MP2 and the leakage current of MP4 influence the state of MP 3. When leakage current I of MP2 UP Leakage current I less than MN4 UN There will be a current at Db flowing from the gate of MP3 to the node of IUP and IDN. When the current is greater than a certain value, the MP3 tube will be opened, D0]Will be abnormally high (H).
In fig. 8, a first transistor denoted by MP0, a second transistor denoted by MP1, a third transistor denoted by MP2, a fourth transistor denoted by MP3, a fifth transistor denoted by MN0, a sixth transistor denoted by MN1, a seventh transistor denoted by MN2, an eighth transistor denoted by MN3, a ninth transistor denoted by MN4, and a tenth transistor denoted by MN 5;
MP0, MP1, MP2, and MP3 are all p-type transistors, and MN0, MN1, MN2, MN3, MN4, and MN5 are all n-type transistors.
As described above, during the period from the power-up of AVDD to the power-up of CEDS signal, the CEDS signal is in a floating state, and the potential of the default clock signal of the internal logic of the source driver ic is low. The longer the CEDS signal is in a floating state, the longer the clock signal is in a floating state, I UP And I UN The more pronounced the effect of (a), the more likely it is that the digital data signal is abnormally set high, and the influence of the leakage current increases with increasing temperature.
In fig. 7, LOCK ki and LOCK _ PAD are determined by a digital data signal and a digital clock signal, but the logic for generating LOCK ki and LOCK _ PAD is different. When the potential of the digital clock signal is low, the potential of LOCK _ PAD is low, and the potential of the Lockout signal remains low at this time. When the potential of the digital clock signal is a low voltage and the potential of the digital data signal is a high voltage, the potential of LOCKi is a high voltage. That is, at this time, when the potential of the digital data signal is abnormally set high, the mismatch between loci and LOCK _ PAD occurs. At this time, the source driver integrated circuit is in an abnormal operation as a whole, and the whole operation is represented as a black screen defect.
In order to solve the above problem, an embodiment of the present invention provides the above start control module.
The start control method according to the embodiment of the present invention is applied to the start control module described above, and the start control method includes:
after the timing controller provides the input signal to the source driving integrated circuit, the control circuit controls the power management integrated circuit to provide the gamma main voltage to the source driving integrated circuit.
In the start control method according to the embodiment of the invention, the timing controller controls the power management integrated circuit to provide the gamma main voltage AVDD to the source driving integrated circuit after providing the input signal to the source driving integrated circuit through the control circuit, so that the power-on time of the AVDD received by the source driving integrated circuit is ensured to be later than that of the input signal received by the source driving integrated circuit, the situation that the AVDD reaches the source driving integrated circuit before the input signal is avoided, and the black screen caused by abnormal output of the source driving integrated circuit is avoided.
The display device according to the embodiment of the invention comprises the start control module.
The display device provided by the embodiment of the invention can be any product or component with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
While the foregoing is directed to the preferred embodiment of the present invention, it will be appreciated by those skilled in the art that various changes and modifications may be made therein without departing from the principles of the invention as set forth in the appended claims.
Claims (10)
1. A starting control module is applied to a display device, and the display device comprises a power management integrated circuit, a time schedule controller and a source electrode driving integrated circuit; the starting control module is characterized by comprising a control circuit;
the control circuit is used for controlling the power management integrated circuit to provide gamma main voltage to the source electrode driving integrated circuit after the time schedule controller provides input signals to the source electrode driving integrated circuit;
the input signals include an input data signal and a data sampling clock signal.
2. The activation control module of claim 1, wherein the input signal is a clock-embedded differential CEDS signal.
3. The start-up control module of claim 1 or 2, characterized in that the control circuit comprises a signal correlation circuit and an output adjustment circuit, wherein,
the signal correlation circuit is used for generating a control signal after the time schedule controller provides an input signal to the source electrode driving integrated circuit, and providing the control signal to the output adjusting circuit through a control signal end;
the output adjusting circuit is electrically connected with the control signal terminal and is used for controlling the gamma main voltage to be supplied to the source electrode driving integrated circuit under the control of the control signal.
4. The start control module set forth in claim 3, wherein the timing controller comprises a V-By-One signal receiving interface, a converting circuit and a CEDS signal transmitting interface;
the V-By-One signal receiving interface is used for receiving a V-By-One signal;
the conversion circuit is respectively electrically connected with the V-By-One signal receiving interface and the CEDS signal sending interface, and is used for converting the V-By-One signal into a CEDS signal and outputting the CEDS signal;
the CEDS signal transmitting interface is electrically connected with the source electrode driving integrated circuit and used for outputting the CEDS signal to the source electrode driving integrated circuit;
the signal correlation circuit is electrically connected with the conversion circuit and used for generating the control signal after the conversion circuit outputs the CEDS signal; or, the signal correlation circuit is electrically connected to the CEDS signal transmission interface, and is configured to generate the control signal after the CEDS signal transmission interface outputs the CEDS signal to the source driver integrated circuit.
5. The start-up control module of claim 3 wherein the output adjust circuit is disposed external to the power management integrated circuit.
6. The start-up control module of claim 5 wherein the output adjust circuit comprises an output control transistor;
the control electrode of the output control transistor is electrically connected with the control signal end, the first electrode of the output control transistor is electrically connected with the gamma main voltage output end of the power management integrated circuit, and the second electrode of the output control transistor is electrically connected with the source electrode driving integrated circuit;
the power management integrated circuit outputs the gamma main voltage through the gamma main voltage output terminal.
7. The start-up control module of claim 1 or 2, wherein the control circuit comprises a signal generation control circuit and an output adjustment circuit;
the signal generation control circuit is used for controlling the generation of a control signal to the output adjusting circuit through a level conversion circuit included in the timing controller or the display device after the timing controller provides an input signal to the source drive integrated circuit;
the output adjusting circuit is used for controlling the gamma main voltage to be supplied to the source electrode driving integrated circuit under the control of the control signal.
8. The start-up control module of claim 1 or 2, wherein the power management integrated circuit includes an analog positive voltage generation circuit;
the control circuit is used for providing an enabling signal for the analog positive voltage generating circuit after the time sequence controller provides an input signal to the source electrode driving integrated circuit;
the analog positive voltage generating circuit is used for generating the gamma main voltage after receiving the enabling signal and providing the gamma main voltage to the source electrode driving integrated circuit.
9. A start control method applied to the start control module according to any one of claims 1 to 8, characterized by comprising:
after the timing controller provides the input signal to the source driving integrated circuit, the control circuit controls the power management integrated circuit to provide the gamma main voltage to the source driving integrated circuit.
10. A display device comprising the activation control module according to any one of claims 1 to 8.
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| CN101093304A (en) * | 2006-06-19 | 2007-12-26 | Lg.菲利浦Lcd株式会社 | Flat-panel display member and driving method thereof |
| CN112735348A (en) * | 2020-12-31 | 2021-04-30 | Tcl华星光电技术有限公司 | Driving circuit, driving method and display device |
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| JP4626408B2 (en) * | 2005-06-03 | 2011-02-09 | エプソンイメージングデバイス株式会社 | Liquid crystal display device |
| US9240160B2 (en) * | 2013-02-18 | 2016-01-19 | Au Optronics Corporation | Driving circuit and display device of using same |
| CN104867469B (en) * | 2015-06-08 | 2017-12-08 | 深圳市华星光电技术有限公司 | The display device of black plug can be carried out |
| CN106601207A (en) * | 2017-01-13 | 2017-04-26 | 京东方科技集团股份有限公司 | Control circuit, source control circuit, driving method, and display device |
| CN109036256B (en) * | 2018-09-30 | 2020-07-07 | 重庆惠科金渝光电科技有限公司 | Gamma voltage regulating circuit and display device |
| CN110728961A (en) * | 2019-10-22 | 2020-01-24 | 南京熊猫电子制造有限公司 | Delay control circuit and control method on liquid crystal display |
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| CN101093304A (en) * | 2006-06-19 | 2007-12-26 | Lg.菲利浦Lcd株式会社 | Flat-panel display member and driving method thereof |
| CN112735348A (en) * | 2020-12-31 | 2021-04-30 | Tcl华星光电技术有限公司 | Driving circuit, driving method and display device |
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