JP2009283602A - Nonvolatile semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory of a small size which incorporates an anti-fuse element, with high operation reliability. <P>SOLUTION: The nonvolatile semiconductor memory comprises an irreversible memory element, of which a first voltage is applied to one end and data is written by the destruction of an insulating fil; a barrier transistor whose one end is connected to the other end side of the irreversible memory element; a memory cell array comprising a plurality of memory cells, each comprising a selective transistor of which one end is connected to the other end of the barrier transistor, while the other end is connected to a ground; a first power source terminal to which the first voltage is supplied, a detection circuit which outputs a first signal if it is found that the first voltage has exceeded the first value; a second power source terminal to which a second voltage is supplied; and a step-up circuit, which when the first signal is outputted from the detection circuit, steps up the second voltage to generate a third voltage which is outputted to the gate of the barrier transistor. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory, and more particularly to a semiconductor memory using an irreversible memory element.

  An electrically writable nonvolatile semiconductor memory is indispensable for redundancy use of a large-capacity memory such as DRAM and SRAM, analog circuit tuning use, and chip ID use.

  In order to reduce the manufacturing cost and provide an inexpensive nonvolatile semiconductor memory, a memory element that can be mounted only by a CMOS standard process is required. As a memory element that satisfies such requirements, there is a gate oxide dielectric breakdown type antifuse. This is an irreversible memory element (hereinafter referred to as an antifuse element) that uses a gate oxide film of a MOS transistor as an antifuse, and stores a state before dielectric breakdown as “0” and a state after dielectric breakdown as “1”.

  For dielectric breakdown of the anti-fuse element, an anti-fuse element power source (hereinafter referred to as VBP) capable of supplying a high voltage of about 6 V, for example, is required. In addition, a barrier transistor is necessary to protect the transistor around the antifuse element from the high voltage supplied by VBP. In order to prevent the dielectric breakdown of the barrier transistor, it is necessary to apply a voltage lower than VBP, for example, about 3 V, to the gate of the barrier transistor. Therefore, a barrier transistor gate power supply (hereinafter referred to as VBT) that supplies this low voltage of about 3V is required. Further, a control logic circuit power supply (hereinafter referred to as VDD) that supplies a voltage of about 1.5 V is also required.

  As described above, a nonvolatile semiconductor memory using an antifuse element requires three power supplies, VDD, VBP, and VBT. Therefore, the nonvolatile semiconductor memory using the anti-fuse element is inconvenient because it is necessary to prepare power supplies of three different voltages in order to use them.

  As countermeasures, a method of incorporating a booster circuit for generating VBT and VBP from VDD, and a method of supplying only a VDD and supplying a VBT voltage and a VBP voltage from the outside have been proposed.

  However, the method incorporating the booster circuit has a problem that the area of the booster circuit increases when the voltage boost ratio is high or when the supplied current amount is large. In addition, in the method of supplying the VBT voltage and the VBP voltage from the outside, in addition to the problem that the number of external power supplies to be prepared is large and difficult to use, there is a problem that the power-on sequence is severely limited. For example, if VBP or VBT is input before VDD is input, there is a risk of erroneous writing. Also, if VBP is turned on before the barrier transistor functions, there is a risk of causing destruction of the internal elements.

  Further, the method (Patent Document 1) in which the VBP circuit and the VBT circuit are built in has a problem that the area of the entire memory circuit becomes too large. In addition, the logic circuit may become indefinite when the power is turned on, and there is a risk that the internal boosting power supply malfunctions due to the influence, thereby causing erroneous writing or destruction of internal elements.

Therefore, it has been difficult to provide a highly reliable non-volatile semiconductor memory using an antifuse element with the conventional technology.
JP 2005-038544 A

  An object of the present invention is to provide a small non-volatile semiconductor memory having an antifuse element and high operational reliability.

  A nonvolatile semiconductor memory according to an aspect of the present invention includes an irreversible memory element in which a first voltage is applied to one end and data is written by breaking an insulating film, and one end is on the other end side of the irreversible memory element. A memory cell array comprising a plurality of memory cells each including a barrier transistor to be connected and a selection transistor having one end connected to the other end of the barrier transistor and the other end connected to the ground; In order to select the memory cell, a word line connected to the gate of the selection transistor, a first power supply terminal to which the first voltage is supplied, and the first power supply terminal are connected to the first power supply terminal. A detection circuit that outputs a first signal when it is detected that the voltage of the first voltage exceeds a first value, a second power supply terminal to which a second voltage is supplied, and the second power supply terminal And when the first signal is output from the detection circuit connected to the detection circuit, the second voltage is boosted to generate a third voltage, and the third voltage is output to the gate of the barrier transistor. And a booster circuit.

  ADVANTAGE OF THE INVENTION According to this invention, the small non-volatile semiconductor memory with a built-in antifuse element and high operation reliability can be provided.

  Next, a nonvolatile semiconductor memory according to an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a schematic diagram showing a nonvolatile semiconductor memory 10 according to an embodiment of the present invention. As shown in FIG. 1, the nonvolatile semiconductor memory 10 according to the present embodiment includes an antifuse element power supply terminal (hereinafter referred to as VBP terminal) 20, a control logic circuit power supply terminal (hereinafter referred to as VDD terminal) 21, and a control signal terminal 22. , VBP detection circuit 30, barrier transistor gate power supply booster circuit (hereinafter referred to as VBT booster circuit) 40, control logic circuit 50, memory cell array 70 to which eight memory cells 60 are connected, and sense connected to each memory cell 60. An amplifier 64 is included. In this embodiment, a memory cell array 70 formed by connecting eight memory cells 60 is shown, but the present invention is not limited to this number and shape.

  The VBP terminal 20 and the VDD terminal 21 are connected to an external power source (not shown), the voltage VBP is supplied to the VBP terminal 20, and the voltage VDD is supplied to the VDD terminal 21.

  As shown in FIG. 1, a power supply line 100 extends from the VBP terminal 20, and a VBP detection circuit 30 and a memory cell array 70 are connected to the power supply line 100. When the voltage VBP supplied from the VBP terminal 20 to the power supply line 100 exceeds a specified value, the VBP detection circuit 30 outputs a start signal 31 for operating the VBT boost circuit 40 to the VBT boost circuit 40. A power supply line 101 extends from the VBT terminal 21, and a VBT booster circuit 40 and a control logic circuit 50 are connected to the power supply line 101. The power supply line 101 is connected to the input side of the VBT booster circuit 40, the power supply line 102 extends from the output side of the VBT booster circuit 40, and all the memory cells 60 forming the memory cell array 70 are connected to the power supply line 102. Is done. When the start signal 31 is input, the VBT booster circuit 40 starts boosting the voltage VDD and generates the voltage VBT. Then, the voltage VBT is output to the power supply line 102 to which the gates of the barrier transistors 62 of all the memory cells 60 forming the memory cell array 70 are connected. A signal line 106 extends from the control terminal 22, and the control logic circuit 50 is connected to the signal line 106. The signal line 106 is connected to the input side of the control logic circuit 50, the signal line 103 extends from the output side, and a sense amplifier 64 connected to all the memory cells 60 is connected to the signal line 103. When the control signal 23 is supplied from the control terminal 22, the control logic circuit 50 outputs a signal 51 for controlling the sense amplifier 64 to the signal line 103.

  The eight memory cells 60 forming the memory cell array 70 are commonly connected to the power supply lines 100 and 102 and the signal line 103.

  The memory cell 60 includes an irreversible storage element 61, a barrier transistor 62, and a selection transistor 63. For example, the irreversible memory element 61 uses a gate oxide film of a MOS transistor as an antifuse, stores a state before dielectric breakdown as “0”, and stores a state after dielectric breakdown as “1”. A fuse (hereinafter referred to as an antifuse element) is used.

  The gate terminal of the antifuse element 61 is connected to the drain terminal of the barrier transistor 62, and the other terminal is connected to the power supply line 100. The other terminal of the antifuse element 61 is, for example, a terminal in which a source terminal, a drain terminal, and a back gate terminal of a pMOS transistor are connected in common. A node connecting the gate terminal of the antifuse element 61 and the drain terminal of the barrier transistor 62 is hereinafter referred to as PG. The anti-fuse element 61 is a fuse element composed of a capacitor. When an excessive voltage is applied, the insulating layer in the anti-fuse element 61 is broken and becomes conductive. The insulating layer of the antifuse element 61 is made of, for example, ONO (oxide layer / nitride layer / oxide layer), an amorphous silicon semiconductor, or the like. However, the present invention is not limited to this.

  The source terminal of the barrier transistor 62 is connected to the drain terminal of the selection transistor 63, and the gate terminal of the barrier transistor 62 is connected to the power supply line 102. A node connecting the source terminal of the barrier transistor 62 and the drain terminal of the selection transistor 63 is hereinafter referred to as VF. A sense amplifier 64 is connected to the node VF of each memory cell 60. Note that a terminal connected to the node VF is an input terminal of the sense amplifier 64.

  The barrier transistor 62 and the selection transistor 63 are formed by nMOS transistors. The barrier transistor 62 is controlled by the voltage VBT, and is shut off when the gate-source voltage becomes equal to or lower than the operation threshold voltage Vth. In other words, when the potential of the node VF of the source terminal of the barrier transistor 62 becomes equal to or higher than the voltage VBT applied to the gate terminal minus the operation threshold voltage Vth, the barrier transistor 62 is cut off. That is, the barrier transistor 62 limits the potential of its source terminal and protects the selection transistor 63 and the sense amplifier 64 connected to the source terminal. In addition, the voltage VBT is connected to the gate terminal of the barrier transistor 62, and the potential difference generated between the gate terminal and the drain terminal of the barrier transistor 62 is relaxed to prevent the barrier transistor 62 from being destroyed.

  The selection transistor 63 is formed between the barrier transistor 62 and the ground VSS. When selection signals DI <A> to <H> are applied to a signal line 104 connected to the gate terminal from a decoder (not shown), the selection transistor 63 becomes conductive and the node VF becomes the ground battery VSS. The output terminal of the sense amplifier 64 is connected to a signal line 105 to which output signals DO <A> to <H> are applied, and an output buffer (not shown) is connected to the signal line 105.

  Next, the write / read operation of the first embodiment will be described with reference to FIGS. FIG. 2 is a timing chart at the time of writing, and FIG. 3 is a timing chart at the time of reading.

  The antifuse element 61 has a high resistance before dielectric breakdown and a low resistance after dielectric breakdown. The high resistance state is defined as “0”, and the low resistance state is defined as “1”. Here, the writing of “1” to the antifuse element 61, that is, the dielectric breakdown of the antifuse element 61 will be described.

  As shown in FIG. 2, application of voltage VBP (6 V) to the VBP terminal 20 is started from an external power source (not shown) at time t0. When the voltage VBP supplied to the VBP terminal 20 and the power supply line 100 exceeds a specified value, the VBP detection circuit 30 outputs a start signal 31 for operating the VBT booster circuit 40. The specified value is, for example, 1V, and exceeds 1V at time t1. Next, when the start signal 31 is input at time t2, the VBT booster circuit 40 starts boosting the voltage VDD and generates the voltage VBT. Then, the barrier transistor 62 is turned on by applying the voltage VBT to the gate. In this state, when the input signals DI <A> to <H> are activated at time t3, the selection transistor 63 becomes conductive at time t4, and the potential of the node PG drops to about VSS potential at time t5. Then, a voltage of about 6 V is applied to the gate oxide film of the PMOS transistor forming the antifuse element 61, and the gate oxide film is broken down to store “1”.

  Next, the reading operation will be described. Reading of the antifuse element 60 is performed as follows.

  As shown in FIG. 3, at time t0, application of voltage VBP (1.5 V) to the VBP terminal 20 from an external power source (not shown) is started. When the voltage VBP supplied to the VBP terminal 20 and the power supply line 100 exceeds a specified value, the VBP detection circuit 30 outputs a start signal 31 for operating the VBT booster circuit 40. The specified value is, for example, 1V, and exceeds 1V at time t1. Next, at time t2, when the start signal 31 is input, the VBT booster circuit 40 starts boosting the voltage VDD and generates the voltage VBT. Then, at time t3, the barrier transistor 62 is turned on by applying the voltage VBT to the gate. Then, charging to the node VF is started by the current flowing through the anti-fuse element 61. At time t4, the charging ends and the determination is made by the sense amplifier 64. Note that the reading is determined by comparing the potential of the node VF and the reference potential VREF by the sense amplifier 64. If the resistance of the anti-fuse element 61 is high, the current flowing through the anti-fuse element is small and the node VF is not charged, so the determination is “0”. On the contrary, if the resistance of the antifuse element 61 is low, a large amount of current is generated in the antifuse element, and VF is charged, so the determination is “1”.

  In addition, since the barrier transistor 62 and the selection transistor 63 are designed with substantially the same size, the leakage currents of both are substantially equal. Therefore, the potential of the node VF other than at the time of writing and at the time of reading becomes a potential substantially intermediate between the VBP potential and the VSS potential.

  In the present embodiment, by incorporating the VBT booster circuit 40, the number of power supplies supplied from the outside can be reduced by one. Since there is no current path from the voltage VBT to the voltage VSS, the VBT boost circuit 40 does not need to have a high current supply capability. Furthermore, since the voltage VBT is half of the voltage VBP, the VBT booster circuit 40 can be formed with an area less than half that of the VBP booster circuit. Further, the voltage VBP is externally supplied, thereby suppressing an increase in area due to the incorporation of the VBP. That is, it is possible to reduce the size of the nonvolatile semiconductor memory.

  In addition, since the voltage VBP is not generated internally, a high voltage is not applied to the antifuse element 61 unless a high voltage is applied to the VBP terminal 20 from the outside, so that there is no risk of erroneous writing. Further, the VBT booster circuit 40 receives the start signal 31 generated from the voltage VBP and generates the voltage VBT. Therefore, since the barrier transistor 62 always operates when a high voltage is applied to the VBP terminal 20, there is no danger of destroying the internal elements of the memory cell 60 without controlling the power-on sequence.

  In summary, in this embodiment, a small nonvolatile semiconductor memory with high operation reliability can be provided.

  The invention of the present application is not limited to the general-purpose memory as in the present embodiment, but includes a form in which it is mixed with a memory such as a DRAM or SRAM as shown in FIG.

1 is a schematic diagram showing a configuration of a nonvolatile semiconductor memory according to an embodiment of the present invention. It is a timing chart at the time of writing of the nonvolatile semiconductor memory. 4 is a timing chart at the time of reading from the nonvolatile semiconductor memory. 2 is a layout diagram showing an embedded LSI including the same nonvolatile semiconductor memory. FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Nonvolatile semiconductor memory, 20 ... VBP terminal, 21 ... VDD terminal, 22 ... Control signal terminal, 23 ... Control signal, 30 ... VBP detection circuit, 31 ... Start signal, 40 ... VBT booster circuit, 50 ... Control logic circuit , 51 ... sense amplifier control signal, 60 ... memory cell, 61 ... anti-fuse element, 62 ... barrier transistor, 63 ... selection transistor, 64 ... sense amplifier, 70 ... memory cell array, 100 to 102 ... power supply line, 103 to 106 ... Signal line.

Claims (5)

An irreversible memory element in which a first voltage is applied to one end and data is written by breaking the insulating film, a barrier transistor having one end connected to the other end of the irreversible memory element, and one end being the barrier transistor A memory cell array configured by arranging a plurality of memory cells each including a selection transistor connected to the other end of the memory and connected to the ground at the other end;
A word line connected to the gate of the selection transistor to select the memory cell when writing data;
A first power supply terminal to which the first voltage is supplied;
A detection circuit that is connected to the first power supply terminal and outputs a first signal when detecting that the first voltage exceeds a first value;
A second power supply terminal to which a second voltage is supplied;
When the first signal is connected to the second power supply terminal and the detection circuit and the first signal is output from the detection circuit, the second voltage is boosted to generate a third voltage to be used as the gate of the barrier transistor. And a booster circuit that outputs a third voltage. The first voltage is:
At the time of writing, the second value is higher than the first value,
The nonvolatile semiconductor memory according to claim 1, wherein at the time of reading, the third value is higher than the first value and lower than the second value. The irreversible memory element is
The nonvolatile semiconductor memory according to claim 1, wherein the nonvolatile semiconductor memory is programmed by dielectric breakdown. In a node where the other end of the barrier transistor and one end of the selection transistor are connected,
The nonvolatile semiconductor memory according to claim 1, wherein a sense amplifier is connected. The nonvolatile semiconductor memory according to claim 1, wherein a sense amplifier is connected to each memory cell.

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