JP2009170016A - Semiconductor storage device and data transfer method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device capable of normally carrying out a data transfer operation to a volatile latch circuit from a nonvolatile memory section even in an area where a voltage of a control terminal for controlling the operation of the nonvolatile memory section is high. <P>SOLUTION: In a control circuit CNT, a readout voltage Vw1 is applied to word lines WL1, WL2, and first switching elements Qn2, Qn3 and a second switching element Qn4 are turned into a conductive state, and then a first presensing operation is carried out for discharging data nodes by each current amount of nonvolatile memory sections M1, M2 after the data nodes SD, SDB are precharged by precharge circuit Qp1, Qp2, and after that, the word line voltages are partially or gradually lowered, and a second presensing operation is carried out for preparatorily amplifying a voltage difference between the data nodes by activating the volatile latch circuit LC. After that, a main sensing operation is started by performing either of turning off the first switching element or perfectly stopping the voltage application to the word lines, or by performing both of these operations. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention is composed of a nonvolatile memory unit and a volatile latch circuit, and holds data in the nonvolatile memory unit in the power-off state and latches data held in the nonvolatile memory unit in the power-on state. More specifically, a semiconductor memory device that is transferred to a circuit and stores the semiconductor memory device, more specifically, a semiconductor memory device having a differential configuration having a floating gate type nonvolatile memory unit using one-layer polysilicon suitable for a logic CMOS process, and The present invention also relates to a data transfer method (recall method) from the nonvolatile memory portion to the volatile latch circuit.

  In recent years, process core program storage integrated in SOC (System On Chip), RFID tag and ID storage for LSI chip management in the market, gamma correction data storage for LCD driver LSI, trimming of various LSI output For this reason, there is an increasing demand for a small-capacity logic embedded nonvolatile memory using a CMOS process. This is because a small-capacity logic embedded nonvolatile memory using a CMOS process is more advantageous in terms of performance and cost than a conventional external EEPROM, fuse technology, and logic embedded flash memory. It is. For example, in terms of cost, the number of masks can be reduced by nearly 10 compared to a logic-embedded flash memory. In addition, the chip area can be reduced compared to the fuse technology. Among them, Impinj, Virage, etc. have commercialized non-volatile memories that are fully compatible with the CMOS process.

  FIG. 1 includes nonvolatile memory units M1 and M2 and a volatile latch circuit LC. The nonvolatile memory units M1 and M2 hold data in the power-off state, and the nonvolatile memory units M1 and M1 in the power-on state. An example of a circuit configuration of a semiconductor memory device that transfers and stores data held in M2 to a volatile latch circuit LC is shown. In the circuit configuration shown in FIG. 1, a pair of nonvolatile memory portions M1 and M2 are provided, each of which is a floating gate type nonvolatile memory using one-layer polysilicon suitable for a logic CMOS process. A differential configuration with high noise resistance in which 1-bit data is complementarily held in the pair of nonvolatile memory units M1 and M2. The volatile latch circuit LC transfers the complementary data held in the pair of nonvolatile memory units M1 and M2 to the pair of data nodes SD and SDB, and amplifies the voltage difference between the pair of data nodes SD and SDB. A latch circuit in which one output and the other input of the two inverter circuits IN1 and IN2 are connected to each other, and an NMOS transistor Qn1 that activates the latch circuit is connected to the two inverter circuits IN1, The configuration is provided between IN2 and the ground voltage line. A control signal SEN for activating the volatile latch circuit LC is input to the gate of the NMOS transistor Qn1.

  Further, in the circuit configuration, a pair of precharge circuits composed of PMOS transistors Qp1 and Qp2 for precharging the pair of data nodes SD and SDB to the power supply voltage Vcc, respectively, and a pair of data nodes SD and SDB and 1 A pair of NMOS transistors Qn2 and Qn3 that connect the pair of nonvolatile memory units M1 and M2 so as to be electrically conductive and cut-off respectively, and a pair of nonvolatile memory units M1 and M2 and the ground voltage line are electrically connected to each other. In addition, an NMOS transistor Qn4 is provided which is connected so as to be able to be turned on and off. A control signal PRE for controlling the precharge operation to the pair of data nodes SD and SDB is input to the gates of the PMOS transistors Qp1 and Qp2. A control signal RG for controlling the electrical connection between the pair of data nodes SD and SDB and the pair of nonvolatile memory units M1 and M2 is input to the gates of the NMOS transistors Qn2 and Qn3. A control signal SRC for controlling the electrical connection between the pair of nonvolatile memory portions and the ground voltage line is input to the gate of the NMOS transistor Qn4.

  As shown in the cross-sectional view of FIG. 2A, the equivalent circuit diagram of FIG. 2B, and the symbol diagram of FIG. 2C, the nonvolatile memory units M1 and M2 include a source SR, a drain DN, a source and a drain. The floating gate FG can be controlled by the amount of accumulated charge, and two control terminals CG1 and CG2 that are capacitively coupled to the floating gate FG. A pair of nonvolatile memory portions M1 and M2 is provided, and complementary data, that is, “0” and “1” of 1-bit data is determined by the amount of charge stored in the floating gate FG, the source SR and the drain DN The threshold voltage of the MOSFET composed of the floating gate FG is stored with a difference. For example, the threshold voltage of the nonvolatile memory unit M1 on the data node SD side is set low (the current amount is large), and the threshold voltage of the nonvolatile memory unit M2 on the data node SDB side is set high (the current amount is small). Further, the first control terminal CG1 of the pair of nonvolatile memory units M1 and M2 is commonly connected to the first word line WL1, and the second control terminal CG2 is commonly connected to the second word line WL2. ing.

  Further, as shown in FIG. 2A, the nonvolatile memory units M1 and M2 are configured to include a first memory unit and a second memory unit, and are formed using a single layer polysilicon suitable for a logic CMOS process. A first floating gate FG1 of one memory unit and a second floating gate FG2 of a second memory unit are formed, and the first floating gate FG1 and the second floating gate FG2 are electrically connected to form a floating gate FG. .

Specifically, the first memory unit includes a source SR and a drain DN of an N ⁺ diffusion layer formed on the surface of the semiconductor substrate 1 and a first channel region between the N ⁺ diffusion layers of the source SR and the drain DN. And an N-type MOSFET structure including a first floating gate FG1 formed on the gate insulating film 3 using one-layer polysilicon. The second memory unit includes two P ⁺ diffusion layers formed on the surface of the N-type well 2 electrically isolated from the formation region of the first memory unit formed in the semiconductor substrate 1, and the two P ⁺ A P-type MOSFET structure having an insulating film 4 on the second channel region between the ⁺ diffusion layers and a second floating gate FG2 formed on the insulating film 4 is provided. In the second memory unit, the N ⁺ contact diffusion layer formed on the surface of the N-type well 2 functions as the first control terminal CG1, and one or both of the two P ⁺ diffusion layers serve as the second control terminal CG2. Function. The first control terminal CG1 and the second control terminal CG2 are capacitively coupled to the second floating gate FG2 via the insulating film 4, respectively.

  During the read operation, the first memory unit functions as an NMOS transistor for reading, and the second memory cell unit receives the first and second control terminals CG1, CG2 via the two word lines WL1, WL2. By applying a voltage to the second memory cell unit, the potential of the second floating gate FG2 on the second memory cell unit side is controlled, and as a result, the potential of the first floating gate FG1 on the first memory unit side is controlled.

  FIG. 3 shows input voltage waveforms of the control signals PRE, SEN, RG, SRC and the word lines WL1, WL2 in the recall operation (data transfer operation from the nonvolatile memory units M1, M2 to the volatile latch circuit LC). The voltage waveforms of the floating gate FG and the pair of data nodes SD and SDB are shown.

  The recall operation is composed of three operation steps of precharge, presense, and main sense that are executed in sequence. First, from the initial state in which the control signal PRE for the precharge operation is at a high level and the other control signals SEN, RG, SRC and the word lines WL1, WL2 are at a low level, the control signals RG, SRC are prior to the precharge operation. And the word lines WL1 and WL2 are transited to a high level. Subsequently, the control signal PRE is changed from a high level to a low level during the precharge period, the PMOS transistors Qp1 and Qp2 are turned on, and the potential of the pair of data nodes SD and SDB is precharged toward the power supply voltage Vcc. To do. During the precharge period, since the control signals RG and SRC and the word lines WL1 and WL2 are at a high level, the pair of nonvolatile memory units M1 and M2 generates a current corresponding to the accumulated charge amount of each floating gate FG. Shed. Here, as an example, the threshold voltage of the nonvolatile memory unit M1 on the data node SD side is set low (large amount of current), and the threshold voltage of the nonvolatile memory unit M2 on the data node SDB side is set high (small amount of current). Therefore, the potential of the data node SD is slightly lower than that of the data node SDB. Also, in terms of DC, the potentials of the pair of data nodes SD and SDB are automatically adjusted to potentials at which the currents of the PMOS transistors Qp1 and Qp2 and the currents of the corresponding nonvolatile memory units M1 and M2 are balanced. The When the control signal PRE is returned to a high level, the PMOS transistors Qp1 and Qp2 are turned off, and the pre-sense operation is automatically started, and a pair of data nodes SD are generated according to the currents of the pair of nonvolatile memory units M1 and M2. , The potential of SDB decreases. In the example of FIG. 3, since the threshold voltage of the nonvolatile memory portion on the data node SDB side is high, the potential of the data node SDB maintains a high potential, and only the potential of the data node SD decreases. Subsequently, the control signal RG is changed to a low level to turn off the NMOS transistors Qn2 and Qn3, thereby electrically separating the pair of data nodes SD and SDB and the pair of nonvolatile memory portions M1 and M2, and at the same time, the control signal When SEN is transitioned to a high level and the NMOS transistor Qn1 is turned on to activate the volatile latch circuit LC, the main sense operation is started, and complementary data corresponding to the potentials of the pair of data nodes SD and SDB is It is held in the volatile latch circuit LC.

JP 2005-532654 A JP 2005-533372 A J. et al. Raszka et al., “Embedded Flash Memory for Security Application in a 0.13 μm CMOS Logic Process”, ISSCC 2004 Technical Digest, Session 2, 2.4, 2004.

  FIG. 4 shows the voltage dependence of the operation result of the recall operation of the semiconductor memory device shown in FIG. 4 shows the dependence of the recall operation result on the power supply voltage Vcc and the word line voltage Vwl. The horizontal axis represents the power supply voltage Vcc, and the vertical axis represents the voltages Vwl of the word lines WL1 and WL2. . In FIG. 4, when the recall operation is passed under each voltage condition (the data stored in the non-volatile memory units M1 and M2 is normally transferred and held in the volatile latch circuit LC), the recall operation is “P”. “F” is displayed when “Fail” has failed. In FIG. 4, the boundary line is indicated by a bold line in order to make it easier to see the boundary between the pass area and the fail area. As apparent from FIG. 4, the recall operation fails in a region where the word line voltage Vwl is high.

  FIG. 5 illustrates the above control signals PRE, SEN, RG similar to those in FIG. 3 in the recall operation when the word line voltage Vwl is high in order to explain the cause of the recall operation failing in the region where the word line voltage Vwl is high. , SRC and input voltage waveforms of the word lines WL1 and WL2, and voltage waveforms of the floating gate FG and the pair of data nodes SD and SDB. When the word line voltage Vwl is high, the current of the nonvolatile memory cell portion M2 on the data node SDB side having a high threshold voltage is larger than the current of the PMOS transistor that constitutes the inverter circuit IN1 of the volatile latch circuit LC, and the data node SDB The potential of the two data nodes SD and SDB drops to substantially the ground potential during the pre-sense operation period, and the potential difference between the data nodes SD and SDB cannot be secured, and erroneous reading occurs in the main sense operation. ing. As described above, the conventional recall operation shown in FIG. 3 has a problem that the operation range becomes narrow on the higher side of the word line voltage Vwl.

  The present invention has been made in view of the above-described problems, and its purpose is composed of a nonvolatile memory portion and a volatile latch circuit. In the power cutoff state, the nonvolatile memory portion holds data and In the semiconductor memory device in which the data held in the nonvolatile memory unit is transferred to the volatile latch circuit and stored in the on state, the data transfer operation from the nonvolatile memory unit to the volatile latch circuit performs the operation of the nonvolatile memory unit. The object is to provide a semiconductor memory device that can operate normally even in a region where the voltage of a control terminal to be controlled is high, and a data transfer method.

  In order to achieve the above object, a semiconductor memory device according to the present invention includes a source, a drain, a floating gate capable of controlling a conduction state between the source and the drain according to the amount of stored charge, and capacitive coupling with the floating gate. A volatile latch circuit capable of amplifying and holding a voltage difference between a pair of nonvolatile memory units having one or two control terminals, a pair of data nodes, and a predetermined power source for the pair of data nodes A precharge circuit for precharging toward a voltage; between one of the pair of data nodes and one of the drains of the pair of nonvolatile memory units; and the other of the pair of data nodes and the pair A pair of first switching elements that connect the other drains of the non-volatile memory unit so as to be electrically conductive and cut-off, respectively, and the pair of non-volatile memory units A second switching element for electrically connecting and disconnecting a source and a predetermined reference voltage, a precharge operation of the precharge circuit, and voltage control of each control terminal of the pair of nonvolatile memory units A control circuit for individually controlling a latch operation of the volatile latch circuit, an on / off operation of the pair of first switching elements, and an on / off operation of the second switching element, the control circuit comprising: , Applying a predetermined read voltage to the control terminal, setting the first switching element and the second switching element to a conductive state, and then activating the precharge circuit to precharge the pair of data nodes. After the precharge circuit is deactivated by deactivating the precharge circuit, the pre-charge operation is performed from the pair of non-volatile memory units. A first pre-sense operation is performed in which a voltage after pre-charging of the pair of data nodes is separately discharged with an amount of current flowing between the drain and the source in accordance with the accumulated charge amount of each floating gate, and the first pre-sense operation is performed. After the pre-sense operation is performed for a predetermined period, the voltage of the control terminal is partially decreased or gradually decreased during a predetermined second pre-sense period, and the volatile latch circuit is activated so that the voltage of the pair of data nodes After performing a second pre-sense operation for preamplifying the difference and executing the second pre-sense operation for the second pre-sense period, the first switching element is turned off or the read voltage is applied to the control terminal. It is configured that a series of control operations can be performed in which the main sense operation is started by performing at least one of the complete stop operation. One feature.

  In the semiconductor memory device according to the present invention, in addition to the first feature, the nonvolatile memory section further includes two control terminals, and the control circuit controls the two control terminals before starting the precharge operation. The voltage of each of the terminals is changed from the initial voltage to the read voltage, and the voltage of one of the two control terminals is changed from the read voltage to the initial voltage at or after the start of the second pre-sense operation, A second feature is that a control operation is performed in which the other voltage of the two control terminals is changed from the read voltage to the initial voltage at the start of the main sense operation.

  In the semiconductor memory device according to the present invention, in addition to the first feature, the control circuit further transitions all voltages at the control terminal from an initial voltage to the read voltage before the precharge operation is started. All the voltages of the control terminals are transitioned from the read voltage to an intermediate voltage between the initial voltage and the read voltage at the start of the second pre-sense operation, and the intermediate voltage at the start or after the start of the main sense operation. A third feature is that a control operation for transitioning from a voltage to the initial voltage is performed.

  In the semiconductor memory device according to the present invention, in addition to the first feature, the control circuit further transitions all voltages at the control terminal from an initial voltage to the read voltage before the precharge operation is started. A fourth feature is that a control operation for gradually transitioning all voltages of the control terminal from the read voltage to the initial voltage is performed at least during the second pre-sense period after the start of the second pre-sense operation. To do.

  According to the semiconductor memory device having the first to fourth characteristics, after the precharge circuit precharges the pair of data nodes by the control operation of the control circuit, the first presense operation performs the operation of the pair of data nodes. The potential is decreased by an amount of current corresponding to the amount of charge stored in each floating gate of the pair of nonvolatile memory units, and then the voltage at the control terminal is gradually decreased partially or during a predetermined second pre-sense period. After the second pre-sense operation for preamplifying the voltage difference between the pair of data nodes by activating the nonvolatile latch circuit, the influence of the current amount of the pair of nonvolatile memory units on the pair of data nodes is affected. The data corresponding to the voltage difference between the pair of data nodes can be held in the volatile latch circuit in the main sense operation, and the data held in the nonvolatile memory unit It can be held is transferred to the volatile latch circuit. Here, in the conventional recall operation, since the second pre-sense operation is not provided and the pre-sense operation is directly shifted to the main sense operation, the floating operation occurs when the voltage (word line voltage) of the control terminal of the nonvolatile memory unit is high. As the gate potential rises unnecessarily and the amount of current in the non-volatile memory portion on the higher threshold voltage side increases, the voltage difference between the pair of data nodes is reduced by the pre-sense operation, and the main sense operation is started. In some cases, the required voltage difference could not be obtained and malfunctioned. However, according to the semiconductor memory device having the first to fourth characteristics, in the second pre-sense operation, the voltage at the control terminal is partially or gradually decreased during a predetermined second pre-sense period, thereby making a pair of nonvolatile memory devices. The potential corresponding to the amount of charge stored in each floating gate of the volatile memory portion is lowered to an intermediate potential between the potential in the initial state and the potential before the start of the second pre-sense operation by capacitive coupling between the floating gate and the control terminal. Alternatively, it gradually decreases to the initial potential. Accordingly, since the current amount of the pair of nonvolatile memory sections after the start of the second pre-sense operation decreases to a medium level, the voltage of the control terminal is high and the potential of the floating gate is unnecessarily increased and increased. Since the amount of current in the nonvolatile memory unit on the higher threshold voltage side is reduced, the reduction in the voltage difference between the pair of data nodes is suppressed. Further, by simultaneously activating the volatile latch circuit, the voltage difference between the pair of data nodes is gradually enlarged, and the voltage difference necessary for the subsequent main sense operation is obtained. Even when the voltage is high, normal data transfer operation (recall operation) is possible.

  As described above, when compared with the conventional data transfer operation (recall operation), the pre-sense operation in the conventional recall operation is performed on the pair of data nodes after the precharge. The main sense operation amplifies the voltage difference between a pair of data nodes generated in the pre-sense operation as necessary. In the data transfer operation in the semiconductor memory device having this feature, the first pre-sense operation corresponds to the conventional pre-sense operation, and the second pre-sense operation includes the conventional pre-sense operation and the main sense operation. This is an operation to be executed after suppressing the amount of current corresponding to the amount of charge stored in each floating gate of a pair of nonvolatile memory sections. Therefore, the second pre-sense operation is not an operation that merely suppresses an increase in voltage when the voltage (word line voltage) at the control terminal is high.

  Here, assuming that the control terminal voltage (word line voltage) is simply suppressed through the first and second pre-sense operations, when the control terminal voltage is low, the non-volatile memory section on the side where the threshold voltage is low The current amount is also reduced, and a voltage difference between the pair of data nodes is not sufficiently generated by the first and second pre-sense operations, and the main sense operation may malfunction. However, in the data transfer operation in the semiconductor memory device of this feature, the voltage of the control terminal is lowered and the volatile latch circuit is activated only in the second pre-sense operation. Since the voltage difference between the pair of data nodes is normally generated in the first pre-sense operation even if the current amount of the non-volatile memory portion on the low threshold voltage side decreases when the voltage of the second threshold voltage is low, The voltage difference can be further amplified by the volatile latch circuit activated in the pre-sense operation, and the malfunction of the subsequent main sense operation can be avoided. Therefore, in the data transfer operation in the semiconductor memory device of this feature, it is possible to widen the operating voltage range of the control terminal to the high voltage side while maintaining normal operation on the low side of the control terminal voltage.

  In particular, according to the semiconductor memory device having the second feature, the operation of partially reducing the voltage of the control terminal at the start of the second pre-sense operation is provided with two control terminals for one nonvolatile memory unit. Can be easily realized by returning one voltage of two control terminals to each nonvolatile memory unit from the read voltage to the initial voltage at the start of the second pre-sense operation. Further, the first switching element can be deactivated by performing a control operation for returning the other voltage of the two control terminals from the read voltage to the initial voltage at the start of the main sense operation. The pair of data nodes can be electrically separated from the non-volatile memory portion without turning off the main sense operation. When the main sense operation is started by turning off the first switching element and electrically separating the pair of data nodes from the nonvolatile memory unit, the other of the two control terminals is started after the main sense operation is started. A control operation for returning the voltage from the read voltage to the initial voltage may be performed.

  In addition to any of the above features, the semiconductor memory device according to the present invention is further characterized in that the floating gate of the nonvolatile memory portion is formed of one layer polysilicon.

  According to the semiconductor memory device having the fifth feature, the semiconductor memory device can be manufactured at low cost without using an extra process or mask for forming the nonvolatile memory portion by using the single-layer polysilicon CMOS process. And the logic circuit can be mixedly mounted on the same semiconductor substrate.

  In addition to any of the above features, the semiconductor memory device according to the present invention further includes a first memory unit having a MOSFET structure in which the nonvolatile memory section includes a first floating gate, the source, and the drain; A second floating gate formed on an insulating film on a first conductivity type well electrically isolated from a formation region of the first memory unit formed on a semiconductor substrate; And a second memory unit electrically connected to the well, wherein the floating gate is formed by electrically connecting the first floating gate and the second floating gate. .

  According to the semiconductor memory device of the sixth feature, a nonvolatile memory unit having at least one control terminal can be specifically realized using a one-layer polysilicon CMOS process.

  In the semiconductor memory device according to the present invention, in addition to the sixth feature, the second memory unit further includes a diffusion region of a second conductivity type different from the first conductivity type on the well surface. A seventh feature is that the second control gate is provided in a part of a lower region of the two floating gates, and the other one of the control gates is electrically connected to the diffusion region of the second conductivity type.

  According to the semiconductor memory device of the seventh feature, a nonvolatile memory portion having two control terminals can be specifically realized using a one-layer polysilicon CMOS process.

  The data transfer method according to the present invention includes a floating gate, a source, a drain, a floating gate capable of controlling a conduction state between the source and the drain according to a stored charge amount, and one or two capacitively coupled to the floating gate. A volatile latch circuit capable of amplifying and holding a voltage difference between a pair of non-volatile memory portions having a control terminal and a pair of data nodes, and the pair of data nodes toward a predetermined power supply voltage A precharge circuit for precharging; one of the pair of data nodes and the drain of one of the pair of nonvolatile memory units; and the other of the pair of data nodes and the pair of nonvolatile memories. A pair of first switching elements that connect the other drains of the first portion to each other so as to be electrically conductive and cut-off, and the source of the first pair of nonvolatile memory portions And a second switching element that electrically connects and disconnects between reference voltages so that data stored complementarily in the pair of non-volatile memory units is stored in the volatile memory. A data transfer method for transferring and storing data in a latch circuit, wherein a predetermined read voltage is applied to the control terminal, and the first switching element and the second switching element are set in a conductive state, and then the precharge circuit A precharge step of activating the pair of data nodes and deactivating the precharge circuit and ending the precharge step, and then the floating gate from the pair of nonvolatile memory units The pair of data nodes is pre-charged with the amount of current flowing between the drain and the source in accordance with the accumulated charge amount of each of the pair of data nodes. A first pre-sensing step for discharging a subsequent voltage separately; and after the first pre-sensing step, the voltage of the control terminal is partially or gradually decreased during a predetermined second pre-sensing period, and the volatile latch circuit is activated And performing a second pre-sense step for preamplifying a voltage difference between the pair of data nodes and performing the second pre-sense step for the second pre-sense period, and then turning off the first switching element, A main sense step of performing at least one of the operation of completely stopping the application of the read voltage to the control terminal and amplifying and storing the voltage difference between the pair of data nodes by the volatile latch circuit The first feature is to have.

  In the data transfer method according to the present invention, in addition to the first feature, the non-volatile memory unit further includes two control terminals, and the voltage of each of the two control terminals before the start of the precharge step. Is transferred from the initial voltage to the read voltage, and one voltage of the two control terminals is changed from the read voltage to the initial voltage at the start of the second pre-sense step, and the other voltage of the two control terminals is changed. A second feature is that a control operation is performed to transition from the read voltage to the initial voltage at or after the start of the main sense step.

  In addition to the first feature, the data transfer method according to the present invention further transitions all voltages of the control terminal from an initial voltage to the read voltage before starting the precharge step, Transition all voltages from the read voltage to an intermediate voltage between the initial voltage and the read voltage at the start of the second pre-sense step, and from the intermediate voltage to the initial voltage at or after the start of the main sense step. The third feature is to make a transition to.

  In addition to the first feature, the data transfer method according to the present invention further transitions all voltages of the control terminal from an initial voltage to the read voltage before the precharge step, and A fourth feature is that all the voltages of the control terminals are gradually shifted from the read voltage toward the initial voltage at least during the second pre-sense step period after the start of the step.

  According to the data transfer method of the first to fourth features, after the precharge circuit precharges the pair of data nodes, the potential of the pair of data nodes is a pair of nonvolatiles in the first presense step. The voltage of the control terminal is lowered at a current amount corresponding to the amount of charge stored in each floating gate of the memory unit, and then the voltage at the control terminal is gradually lowered partially or during a predetermined second pre-sense period, and the volatile latch circuit is activated. After performing the second pre-sense step for preamplifying the voltage difference between the pair of data nodes, the main sense step is performed by blocking the influence of the current amount of the pair of nonvolatile memory units on the pair of data nodes. The data corresponding to the voltage difference between the pair of data nodes can be held in the volatile latch circuit, and the data held in the nonvolatile memory portion can be stored in the volatile latch. Can be held is transferred to the circuit. Here, in the conventional recall operation, since the second pre-sense step is not provided and the pre-sense step is directly shifted to the main sense step, the floating operation occurs when the voltage (word line voltage) of the control terminal of the nonvolatile memory unit is high. The potential of the gate rises unnecessarily, and the amount of current in the non-volatile memory portion on the higher threshold voltage side increases, so that the voltage difference between the pair of data nodes is reduced by the pre-sense step, and the main sense step In some cases, the required voltage difference could not be obtained and malfunctioned. However, according to the data transfer methods of the first to fourth characteristics, in the second pre-sense step, the voltage of the control terminal is partially or gradually decreased during a predetermined second pre-sense period, thereby making a pair of nonvolatiles. The potential corresponding to the amount of charge stored in each floating gate of the volatile memory portion is lowered to an intermediate potential between the potential in the initial state and the potential before the start of the second pre-sense operation by capacitive coupling between the floating gate and the control terminal. Alternatively, it gradually decreases to the initial potential. Accordingly, since the current amount of the pair of nonvolatile memory portions after the start of the second pre-sense step decreases to a medium level, the voltage of the control terminal is high and the potential of the floating gate is increased unnecessarily. Since the amount of current in the nonvolatile memory unit on the higher threshold voltage side is reduced, the reduction in the voltage difference between the pair of data nodes is suppressed. Further, by simultaneously activating the volatile latch circuit, the voltage difference between the pair of data nodes is gradually enlarged, and the voltage difference necessary for the subsequent main sense step is obtained. Even when the voltage is high, normal data transfer operation (recall operation) is possible.

  Here, assuming that the control terminal voltage (word line voltage) is simply suppressed through the first and second pre-sense steps, when the control terminal voltage is low, the non-volatile memory section on the lower threshold voltage side , The voltage difference between the pair of data nodes is not sufficiently generated by the first and second pre-sense steps, and may malfunction in the main sense step. However, in the data transfer method of this feature, the voltage of the control terminal is lowered only in the second pre-sense step and the volatile latch circuit is activated, so that the voltage of the control terminal is low in the second pre-sense step. In this case, even if the current amount of the non-volatile memory part on the lower threshold voltage side is decreased, the voltage difference between the pair of data nodes is normally generated in the first presense step. The voltage difference can be further amplified by the volatile latch circuit that has been made, and the malfunction of the subsequent main sense step can be avoided. Therefore, in the data transfer method of this feature, it is possible to expand the operating voltage range of the control terminal to the high voltage side while maintaining normal operation on the low voltage side of the control terminal.

  Next, a semiconductor memory device and a data transfer method according to the present invention (hereinafter referred to as “the present device” and “the present method” as appropriate) will be described with reference to the drawings.

<First Embodiment>
FIG. 6 shows a circuit configuration example of the device of the present invention. In the circuit configuration shown in FIG. 6, a pair of nonvolatile memory portions M1 and M2 are provided, each of which is a floating gate type nonvolatile memory using one-layer polysilicon suitable for a logic CMOS process. A differential configuration with high noise resistance in which 1-bit data is complementarily held in the pair of nonvolatile memory units M1 and M2. The volatile latch circuit LC transfers the complementary data held in the pair of nonvolatile memory units M1 and M2 to the pair of data nodes SD and SDB, and amplifies the voltage difference between the pair of data nodes SD and SDB. A latch circuit in which one output and the other input of the two inverter circuits IN1 and IN2 are connected to each other, and an NMOS transistor Qn1 that activates the latch circuit is connected to the two inverter circuits IN1, The configuration is provided between the source terminal of the NMOS transistor of IN2 and the ground voltage line. A control signal SEN for activating the volatile latch circuit is input to the gate of the NMOS transistor Qn1.

  As shown in the cross-sectional view of FIG. 2A, the equivalent circuit diagram of FIG. 2B, and the symbol diagram of FIG. 2C, the nonvolatile memory units M1 and M2 include a source SR, a drain DN, a source and a drain. The floating gate FG can be controlled by the amount of accumulated charge, and two control terminals CG1 and CG2 that are capacitively coupled to the floating gate FG. A pair of nonvolatile memory sections are provided, and complementary data, that is, “0” and “1” of 1-bit data are determined by the amount of charge stored in the floating gate FG, the source SR, the drain DN, and the floating gate The threshold voltages of MOSFETs made of FG are stored with a difference. For example, the threshold voltage of the nonvolatile memory unit on the data node SD side is set low (large amount of current), and the threshold voltage of the nonvolatile memory unit on the data node SDB side is set high (small amount of current). Further, the first control terminals CG1 of the pair of nonvolatile memory units are commonly connected to the first word line WL1, and the second control terminal CG2 is commonly connected to the second word line WL2.

  Further, as shown in FIG. 2A, the non-volatile memory portions M1 and M2 are configured to include a first memory unit and a second memory unit, and are formed using a single layer polysilicon suitable for a logic CMOS process. A first floating gate FG1 of one memory unit and a second floating gate FG2 of a second memory unit are formed, and the first floating gate FG1 and the second floating gate FG2 are electrically connected to form a floating gate FG. . The nonvolatile memory units M1 and M2 have the same configuration as the nonvolatile memory unit of the conventional semiconductor memory device shown in FIG.

  In the circuit configuration of the device of the present invention, a pair of data nodes SD and SDB are precharged separately to the power supply voltage Vcc, a pair of precharge circuits comprising PMOS transistors Qp1 and Qp2, and a pair of data nodes SD, A pair of NMOS transistors Qn2 and Qn3 (corresponding to a first switching element) that connect between the SDB and the drain DN of the first memory unit of the pair of nonvolatile memory units M1 and M2 so as to be electrically conductive and cut-off respectively. And an NMOS transistor Qn4 (secondly connected) between the source SR of the first memory unit of the pair of nonvolatile memory units M1 and M2 and the ground voltage line (corresponding to the reference voltage line) so that they can be electrically connected and disconnected. Equivalent to a switching element). A control signal PRE for controlling the precharge operation to the pair of data nodes SD and SDB is input to the gates of the PMOS transistors Qp1 and Qp2. A control signal RG for controlling the electrical connection between the pair of data nodes SD and SDB and the pair of nonvolatile memory units M1 and M2 is input to the gates of the NMOS transistors Qn2 and Qn3. A control signal SRC for controlling electrical connection between the pair of nonvolatile memory portions M1 and M2 and the ground voltage line is input to the gate of the NMOS transistor Qn4.

  The device according to the present invention further inputs the control signals PRE, SEN, RG, SRC and the word lines WL1, WL2 in a recall operation (data transfer operation from the nonvolatile memory units M1, M2 to the volatile latch circuit LC). A control circuit CNT for controlling the voltage and its change timing is provided. The device of the present invention is characterized by voltage control and timing control of each control signal by the control circuit CNT.

  FIG. 7 shows the input voltage waveforms of the control signals PRE, SEN, RG, SRC and the word lines WL1, WL2, the floating gate FG, and a pair of data nodes in the recall operation of the first embodiment (the method of the present invention). The voltage waveforms of SD and SDB are shown. Note that the control signal SRC and the high-level voltage Vwl of the word lines WL1 and WL2 in FIG. 7 correspond to a predetermined read voltage. In this embodiment, as will be described later, even when the read voltage Vwl is high, Normal recall operation is possible. The voltages at the time when the other control signals PRE, SEN, RG are at the high level are all set to the power supply voltage Vcc. Note that the voltage at the low level of each control signal and word line is the ground voltage (0 V). As will be described later, by separating the read voltage Vwl from the power supply voltage Vcc and making it independent, the lower limit value of the operating voltage range of the power supply voltage Vcc can be reduced. Note that the voltage when the control signal SRC is at a high level may be the power supply voltage Vcc similarly to the voltages when the other control signals PRE, SEN, and RG are at a high level.

  FIG. 7 shows a voltage waveform when the read voltage Vwl malfunctioning in the conventional recall operation is high for comparison with the conventional recall operation shown in FIG.

  In the device according to the present invention, the recall operation includes four operation steps of precharge, first presense, second presense, and main sense, which are executed in order.

  First, from the initial state in which the control signal PRE for the precharge operation is at a high level and the other control signals SEN, RG, SRC and the word lines WL1, WL2 are at a low level, the control signals RG, SRC are prior to the precharge operation. And the word lines WL1 and WL2 are transited to a high level. At this time, the coupling capacitance between the first control terminal CG1 and the second floating gate FG2 is C1, the coupling capacitance between the second control terminal CG2 and the second floating gate FG2 is C2, and the entire floating gate FG including the coupling capacitances C1 and C2. Let Ct be the capacitance of the floating gate FG, the potential of the floating gate FG increases by Vwl × (C1 + C2) / Ct. Since the stored charge amount of the floating gate FG is different between the pair of nonvolatile memory portions M1 and M2, the absolute value of the potential of the floating gate FG is different from each other.

  Subsequently, the control signal PRE is changed from a high level to a low level during the precharge period, the PMOS transistors Qp1 and Qp2 are turned on, and the potential of the pair of data nodes SD and SDB is precharged toward the power supply voltage Vcc. To do. During the precharge period, since the control signals RG and SRC and the word lines WL1 and WL2 are at a high level, the pair of nonvolatile memory units M1 and M2 generates a current corresponding to the accumulated charge amount of each floating gate FG. Shed. Here, as an example, the threshold voltage of the nonvolatile memory unit M1 on the data node SD side is set low (large amount of current), and the threshold voltage of the nonvolatile memory unit M2 on the data node SDB side is set high (small amount of current). Therefore, the potential of the data node SD is slightly lower than that of the data node SDB. Further, in terms of DC, the potentials of the pair of data nodes SD and SDB are the current between the PMOS transistors Qp1 and Qp2 and the current between the source and drain of the corresponding first memory unit of the nonvolatile memory units M1 and M2. Is automatically adjusted to a balanced potential. When the control signal PRE is returned to the high level, the PMOS transistors Qp1 and Qp2 are turned off, and the first pre-sense operation is automatically started, and a pair of the non-volatile memory units M1 and M2 is set according to the currents of the pair. The potentials of the data nodes SD and SDB are lowered. In the example of FIG. 7, the threshold voltage of the non-volatile memory M2 on the data node SDB side is high, but the read voltage Vwl is high, so the potential of the data node SDB does not maintain a high potential, and both the data nodes SD and SDB The potential of

  After performing the first pre-sense operation for a predetermined period (first pre-sense period), the voltage of the second word line WL2 connected to each second control terminal CG2 of the pair of nonvolatile memory units M1 and M2 is set to the initial state. While returning to the ground voltage, the control signal SEN is transited to a high level, the NMOS transistor Qn1 is turned on to activate the volatile latch circuit LC, and the second pre-sense operation is started. As a result, the potentials of the floating gates FG of the pair of nonvolatile memory units M1 and M2 are lowered by Vwl × C2 / Ct, so that the nonvolatile memory unit M2 on the data node SDB side is on the data node SD side. Since the threshold voltage is higher than that of the non-volatile memory portion M1, the decrease in the amount of current becomes remarkable, and a pair of data nodes SD by the PMOS transistors constituting the inverter circuits IN1, IN2 of the activated volatile latch circuit LC, The voltage difference between the pair of data nodes SD and SDB is amplified according to the current difference between the pair of nonvolatile memory units M1 and M2 by the charging operation of the SDB. Specifically, only the data node SDB side is charged, and the data node SD side is pulled down to the ground voltage by the nonvolatile memory unit M1 and the volatile latch circuit LC.

  After the second pre-sense operation is performed for a predetermined period (second pre-sense period), the control signal RG is changed to a low level to turn off the NMOS transistors Qn2 and Qn3, and a pair of non-volatile data nodes SD and SDB. The main sense operation is started by electrically separating the memory units M1 and M2. As a result, complementary data corresponding to the potential of the pair of data nodes SD and SDB is held in the volatile latch circuit LC.

  FIG. 8 shows the voltage dependence of the operation result of the recall operation in the present embodiment. 8 shows the dependence of the recall operation result on the power supply voltage Vcc and the word line voltage (read voltage) Vwl. The horizontal axis indicates the power supply voltage Vcc, and the vertical axis indicates the word lines WL1 and WL2. Read voltage Vwl. In FIG. 8, “P” indicates that the recall operation has passed under each voltage condition, and “F” indicates that the recall operation has failed. In FIG. 8, the boundary line is displayed as a bold line to make it easier to see the boundary between the pass area and the fail area. As is clear from FIG. 8, in the recall operation of the present embodiment, the second pre-sense operation is provided before the main sense operation, so that the recall operation does not fail and operates normally even in a region where the read voltage Vwl is high. I understand that. In the recall operation in the present embodiment, the lower limit value of the operating range of the power supply voltage Vcc is 1.2V, and the lower limit value of the operating range of the read voltage Vwl is 2.85V. It can be seen that the voltage Vwl is substantially constant within each operating range. Therefore, it can be seen that the lower limit value of the operating range of the power supply voltage Vcc can be lowered by controlling the read voltage Vwl independently of the power supply voltage Vcc.

Second Embodiment
Next, a second embodiment of the device of the present invention and the method of the present invention will be described. In the second embodiment, only the control operation (the method of the present invention) of the control circuit CNT is different, and the circuit configuration of the device of the present invention is the same as that of the first embodiment, and therefore, redundant description is omitted.

  FIG. 9 shows the input voltage waveforms of the control signals PRE, SEN, RG, SRC and the word lines WL1, WL2, the floating gate FG and a pair of data nodes in the recall operation (the method of the present invention) of the second embodiment. The voltage waveforms of SD and SDB are shown.

  In the second embodiment, the start procedure of the main sense operation is different from that of the first embodiment. In the first embodiment, after the second pre-sense operation is performed for a predetermined period (second pre-sense period), the control signal RG is changed to a low level to turn off the NMOS transistors Qn2 and Qn3, and the pair of data nodes SD and SDB The main sense operation is started by electrically separating the pair of nonvolatile memory units M1 and M2 (see FIG. 7). However, in the second embodiment, the signal level of the control signal RG is maintained at a high level. The voltage of the first word line WL1 connected to each first control terminal CG1 of the pair of nonvolatile memory units M1 and M2 is returned to the ground voltage in the initial state. As a result, the potentials of the floating gates FG of the pair of nonvolatile memory units M1 and M2 further decrease by Vwl × C1 / Ct following the second pre-sense operation, so that the initial state is restored, and the nonvolatile memory unit M1 , M2 are both turned off. Therefore, even if the NMOS transistors Qn2 and Qn3 are turned on, the pair of data nodes SD and SDB and the pair of nonvolatile memory portions M1 and M2 can be electrically separated, and the main sense operation can be started. Also in the second embodiment, the process up to the second pre-sense operation is exactly the same as in the first embodiment, and the main sense operation can be started substantially in the same manner as in the first embodiment. The same operating range expansion effect can be obtained.

<Third Embodiment>
Next, a third embodiment of the device of the present invention and the method of the present invention will be described. In the third embodiment, only the control operation (the method of the present invention) of the control circuit CNT is different, and the circuit configuration of the device of the present invention is the same as that of the first embodiment, and therefore, redundant description is omitted.

  FIG. 10 shows the input voltage waveforms of the control signals PRE, SEN, RG, SRC and the word lines WL1, WL2, the floating gate FG and a pair of data nodes in the recall operation of the third embodiment (the method of the present invention). The voltage waveforms of SD and SDB are shown.

  In the third embodiment, the start procedure of the second pre-sense operation is different from that of the first embodiment. In the first embodiment, after the first pre-sense operation is performed for a predetermined period (first pre-sense period), the second word line WL2 connected to each second control terminal CG2 of the pair of nonvolatile memory units M1 and M2 Is returned to the ground voltage in the initial state, and the potential of each floating gate FG of the pair of nonvolatile memory portions M1 and M2 is lowered by Vwl × C2 / Ct (see FIG. 7). In the embodiment, the voltages of the two word lines WL1 and WL2 are simultaneously reduced to an intermediate voltage Vmid between the read voltage Vwl and the ground voltage (for example, half of the read voltage Vwl). As a result, the potentials of the floating gates FG of the pair of nonvolatile memory portions M1 and M2 are lowered by Vmid × (C1 + C2) / Ct. By setting the intermediate voltage Vmid so that Vmid × (C1 + C2) / Ct is the same as or substantially the same as Vwl × C2 / Ct, the second pre-sense operation of the third embodiment is exactly the same as the first embodiment. An effect can be produced. Therefore, also in the third embodiment, the same operation range expansion effect as described in the first embodiment can be obtained. The intermediate voltage Vmid can be generated by dividing the read voltage Vwl by resistance.

<Fourth embodiment>
Next, a fourth embodiment of the device of the present invention and the method of the present invention will be described. In the fourth embodiment, only the control operation (the method of the present invention) of the control circuit CNT is different, and the circuit configuration of the device of the present invention is the same as that of the first embodiment, and therefore, a duplicate description is omitted.

  FIG. 11 shows the input voltage waveforms of the control signals PRE, SEN, RG, SRC and the word lines WL1, WL2, the floating gate FG, and a pair of data nodes in the recall operation of the fourth embodiment (the method of the present invention). The voltage waveforms of SD and SDB are shown.

  In the fourth embodiment, the start procedure of the second pre-sense operation is different from that of the first embodiment. In the first embodiment, after the first pre-sense operation is performed for a predetermined period (first pre-sense period), the second word line WL2 connected to each second control terminal CG2 of the pair of nonvolatile memory units M1 and M2 In the fourth embodiment, the potential of the floating gates FG of the pair of nonvolatile memory portions M1 and M2 is reduced by Vwl × C2 / Ct (see FIG. 7). In the embodiment, the voltages of the two word lines WL1 and WL2 are gradually lowered from the read voltage Vwl to the ground voltage over the second pre-sense period. As a result, the potentials of the floating gates FG of the pair of nonvolatile memory portions M1 and M2 are finally lowered by Vwl × (C1 + C2) / Ct and returned to the initial state, but after the start of the second pre-sense operation, The intermediate state similar to that of the third embodiment is maintained without suddenly returning to the initial state. As a result, the second pre-sense operation of the fourth embodiment can achieve substantially the same operational effects as the first embodiment. Therefore, also in the fourth embodiment, the same operation range expansion effect as described in the first embodiment can be obtained. A specific method for gradually reducing the voltages of the word lines WL1 and WL2 can be realized by increasing the signal fall time using a delay circuit such as an RC circuit using resistors and capacitors. Note that the falling of the signals of the word lines WL1 and WL2 does not necessarily have to be linear.

  FIG. 11 illustrates the case where the voltages of the two word lines WL1 and WL2 are gradually decreased from the read voltage Vwl to the ground voltage over the second pre-sense period. However, the voltages of the word lines WL1 and WL2 are completely reduced. Before reaching the ground voltage, the control signal RG may be shifted to a low level to start the main sense operation.

  In the fourth embodiment, when the voltages of the two word lines WL1 and WL2 are reduced to the ground voltage, the main sense operation is substantially started. Therefore, the timing for transitioning the control signal RG to the low level is not necessarily limited. It does not have to be strictly controlled.

<Another embodiment>
Non-volatile memory parts M1, M2, volatile latch circuit LC, precharge circuit (PMOS transistors Qp1, Qp2), first switching element (NMOS transistors Qn2, Qn3) in the device of the present invention of the first to fourth embodiments. Each of the specific circuit configurations is not limited to the circuit configurations shown in FIGS.

  In the recall operations of the first to fourth embodiments, it is assumed that the nonvolatile memory units M1 and M2 include two control terminals CG1 and CG2, respectively, and are connected to the word lines WL1 and WL2, respectively. In the recall operation of the third and fourth embodiments, since the same control is performed without distinguishing the two word lines WL1 and WL2 in the control related to the start of the second pre-sense operation, the nonvolatile memory unit M1 , M2 is also applicable to a single control terminal. Therefore, the recall operation of the third and fourth embodiments can be applied to one nonvolatile memory unit that has a control terminal capacitively coupled to the floating gate FG, so the specific structure of the floating gate FG and the control terminal is not limited. Absent. That is, the recall operation of the third and fourth embodiments can be applied to the case where the nonvolatile memory unit is configured by a conventional flash memory cell.

  The present invention is composed of a nonvolatile memory unit and a volatile latch circuit, and holds data in the nonvolatile memory unit in the power-off state and latches data held in the nonvolatile memory unit in the power-on state. The present invention can be used for a semiconductor memory device that transfers data to a circuit for storage and a data transfer method thereof.

A circuit diagram showing an example of a circuit configuration of a conventional semiconductor memory device for transferring data stored in a nonvolatile memory section to a volatile latch circuit and storing it Sectional view schematically showing the schematic sectional structure of the nonvolatile memory section, its equivalent circuit diagram and symbol diagram FIG. 1 is a schematic voltage waveform diagram schematically showing a control signal and an input voltage waveform of a word line and a voltage waveform of a floating gate and a pair of data nodes in the conventional data transfer operation for the semiconductor memory device shown in FIG. FIG. 3 is a path-fail distribution diagram showing the voltage dependence of the operation result of the conventional data transfer operation shown in FIG. Schematic voltage waveform schematically showing a control signal and a word line input voltage waveform and a voltage waveform of a floating gate and a pair of data nodes for explaining the cause of failure of the conventional data transfer operation in a region where the word line voltage is high Figure 1 is a circuit diagram showing a circuit configuration example of a semiconductor memory device according to the present invention. 1 is a schematic voltage waveform diagram schematically showing a control signal, an input voltage waveform of a word line, and a voltage waveform of a floating gate and a pair of data nodes in the first embodiment of the data transfer operation of the semiconductor memory device according to the present invention. FIG. 7 is a path-fail distribution diagram showing the voltage dependence of the operation result of the data transfer operation according to the first embodiment shown in FIG. Schematic voltage waveform diagram schematically showing the control signal and the input voltage waveform of the word line and the voltage waveform of the floating gate and the pair of data nodes in the second embodiment of the data transfer operation of the semiconductor memory device according to the present invention. Schematic voltage waveform diagram schematically showing a control signal and an input voltage waveform of a word line and a voltage waveform of a floating gate and a pair of data nodes in the third embodiment of the data transfer operation of the semiconductor memory device according to the present invention. Schematic voltage waveform diagram schematically showing a control signal, an input voltage waveform of a word line, and a voltage waveform of a floating gate and a pair of data nodes in the fourth embodiment of the data transfer operation of the semiconductor memory device according to the invention.

Explanation of symbols

1: Semiconductor substrate 2: N-type well 3: Gate insulating film 4: Insulating film CG1: First control terminal (N ⁺ contact diffusion layer)
CG2: Second control terminal (P ⁺ diffusion layer)
CNT: Control circuit DN: Drain (N ⁺ diffusion layer)
FG: floating gate FG1: first floating gate FG2: second floating gate IN1, IN2: inverter circuit LC: volatile latch circuit M1, M2: nonvolatile memory unit PRE: precharge control signal Qn1: volatile latch circuit active NMOS transistors Qn2 and Qn3 used for conversion: NMOS transistors (first switching elements)
Qn4: NMOS transistor (second switching element)
Qp1, Qp2: PMOS transistors (precharge circuit)
RG: Control signal for controlling electrical connection between data node and nonvolatile memory unit SD, SDB: Data node SEN: Control signal for volatile latch circuit activation SR: Source (N ⁺ diffusion layer)
SRC: Control signal for controlling electrical connection between the nonvolatile memory section and the ground voltage line Vcc: Power supply voltage Vwl: Word line voltage (read voltage)
WL1: first word line WL2: second word line

Claims (11)

1 of a non-volatile memory unit comprising a source, a drain, a floating gate capable of controlling a conduction state between the source and the drain by the amount of accumulated charge, and one or two control terminals capacitively coupled to the floating gate. Vs.
A volatile latch circuit capable of amplifying and holding a voltage difference between a pair of data nodes;
A precharge circuit for precharging the pair of data nodes toward a predetermined power supply voltage;
Between one of the pair of data nodes and the drain of one of the pair of nonvolatile memory units, and between the other of the pair of data nodes and the other drain of the pair of nonvolatile memory units. A pair of first switching elements that are electrically connected to each other so as to be electrically conductive and interruptable;
A second switching element that connects between the source of the pair of nonvolatile memory units and a predetermined reference voltage so as to be electrically conductive and interruptable;
A precharge operation of the precharge circuit; a voltage control of the control terminals of the pair of nonvolatile memory units; a latch operation of the volatile latch circuit; an on / off operation of the pair of first switching elements; A control circuit for individually controlling the on / off operation of the second switching element,
The control circuit applies a predetermined read voltage to the control terminal, sets the first switching element and the second switching element to a conductive state, and then activates the precharge circuit to thereby activate the pair of data After performing an operation of precharging a node, deactivating the precharge circuit and ending the precharge operation, the drain corresponding to the amount of charge accumulated in each of the floating gates from the pair of nonvolatile memory units And a first pre-sense operation for separately discharging the voltage after pre-charging of the pair of data nodes with the amount of current flowing between the sources, and after executing the first pre-sense operation for a predetermined period, The voltage is gradually reduced partially or during a predetermined second pre-sense period, and the volatile latch circuit is activated to After performing a second pre-sense operation for preamplifying the voltage difference of the data node and performing the second pre-sense operation for the second pre-sense period, the first switching element is turned off or the reading to the control terminal is performed A semiconductor memory device configured to be capable of a series of control operations in which a main sense operation is started by performing at least one of the operations of completely stopping voltage application. The nonvolatile memory unit has two control terminals,
The control circuit causes each voltage of the two control terminals to transition from the initial voltage to the read voltage before the precharge operation is started, and the voltage of one of the two control terminals is changed to the second presense operation. Performing a control operation of transitioning from the read voltage to the initial voltage at the start, and transitioning the other voltage of the two control terminals from the read voltage to the initial voltage at or after the start of the main sense operation. The semiconductor memory device according to claim 1.   The control circuit transitions all voltages at the control terminal from an initial voltage to the read voltage before starting the precharge operation, and sets all voltages at the control terminal at the start of the second pre-sense operation. 2. A control operation is performed in which a transition is made from a read voltage to an intermediate voltage between the initial voltage and the read voltage, and a transition is made from the intermediate voltage to the initial voltage at or after the start of the main sense operation. The semiconductor memory device described in 1.   The control circuit transitions all voltages of the control terminal from an initial voltage to the read voltage before starting the precharge operation, and at least during the second presense period after starting the second presense operation. 2. The semiconductor memory device according to claim 1, wherein a control operation is performed to gradually transition all of the voltages from the read voltage toward the initial voltage.   5. The semiconductor memory device according to claim 1, wherein the floating gate of the nonvolatile memory portion is formed of one-layer polysilicon. The nonvolatile memory unit is
A first memory unit having a MOSFET structure including a first floating gate, the source, and the drain;
A second floating gate formed on an insulating film on a first conductivity type well electrically isolated from a formation region of the first memory unit formed on a semiconductor substrate; 2. The semiconductor device according to claim 1, further comprising a second memory unit electrically connected to the well, wherein the floating gate is formed by electrically connecting the first floating gate and the second floating gate. The semiconductor memory device according to any one of?   The second memory unit includes a diffusion region of a second conductivity type different from the first conductivity type in a part of a region below the second floating gate on the well surface, and the other one of the control gates The semiconductor memory device according to claim 6, wherein the semiconductor memory device is electrically connected to the diffusion region of the second conductivity type. A non-volatile memory comprising a floating gate, a source, a drain, a floating gate capable of controlling a conduction state between the source and the drain by the amount of accumulated charge, and one or two control terminals capacitively coupled to the floating gate A pair of parts,
A volatile latch circuit capable of amplifying and holding a voltage difference between a pair of data nodes;
A precharge circuit for precharging the pair of data nodes toward a predetermined power supply voltage;
Between one of the pair of data nodes and the drain of one of the pair of nonvolatile memory units, and between the other of the pair of data nodes and the other drain of the pair of nonvolatile memory units. A pair of first switching elements that are electrically connected to each other so as to be electrically conductive and interruptable;
A semiconductor memory device comprising: a second switching element that electrically connects and disconnects between the source of the pair of nonvolatile memory units and a predetermined reference voltage;
A data transfer method for transferring data stored in a complementary manner in the pair of nonvolatile memory sections to the volatile latch circuit and storing the data,
A predetermined read voltage is applied to the control terminal to set the first switching element and the second switching element to a conductive state, and then the precharge circuit is activated to precharge the pair of data nodes. A precharge step;
After deactivating the precharge circuit and ending the precharge step, the amount of current flowing between the drain and the source from the pair of nonvolatile memory units according to the amount of charge accumulated in each of the floating gates A first pre-sense step of discharging the voltage after pre-charging of the pair of data nodes separately;
After the first pre-sense step, the voltage at the control terminal is partially lowered or gradually decreased during a predetermined second pre-sense period, and the volatile latch circuit is activated to reduce the voltage difference between the pair of data nodes. A second pre-sense step for preamplifying;
After executing the second pre-sense step in the second pre-sense period, at least one of the operation of turning off the first switching element or completely stopping the application of the read voltage to the control terminal is performed. And a main sense step of amplifying and storing a voltage difference between the pair of data nodes by the volatile latch circuit. The nonvolatile memory unit has two control terminals,
Before starting the precharge step, the voltage of each of the two control terminals is changed from the initial voltage to the read voltage, and one voltage of the two control terminals is changed to the read voltage at the start of the second presense step. The control operation is performed to make a transition from the read voltage to the initial voltage at the start of the main sense step or after the start of the main sense step. 9. The data transfer method according to 8.   Before starting the precharge step, all voltages at the control terminal are changed from an initial voltage to the read voltage, and all voltages at the control terminal are changed from the read voltage to the initial voltage at the start of the second presense step. 9. The data transfer method according to claim 8, wherein transition is made to an intermediate voltage between the voltage and the read voltage, and transition is made from the intermediate voltage to the initial voltage at or after the start of the main sense step. Before starting the precharge step, all voltages of the control terminal are changed from an initial voltage to the read voltage, and all voltages of the control terminal are at least during the second presense step after the start of the second presense step. 9. The data transfer method according to claim 8, wherein a transition is gradually made from the read voltage toward the initial voltage.

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