JP5710681B2 - Semiconductor integrated device - Google Patents

Description

  The present invention relates to a semiconductor integrated device.

  A conventional semiconductor memory circuit 1 is shown in FIG. As shown in FIG. 12, the semiconductor memory circuit 1 has a cell array region 2, a sense amplifier region 3, and a driver region 4.

  The cell array region 2 has a plurality of memory cells CELL (CELL1, CELL2,...).

  Each memory cell is connected to one of the bit line pair D and DB. Each memory cell has a gate transistor Tr and a cell capacitor Ccell. In the gate transistor Tr, one of the drain and the source is connected to one of the bit lines D and DB, and the other of the drain and the source is connected to the cell capacitor Ccell. A connection point between the gate transistor Tr and the cell capacitor Ccell is a cell node. A terminal on the opposite side of the cell node of the cell capacitor Ccell is connected to the HVDD terminal. The HVDD terminal is supplied with a voltage of ½ VDD (VDD: power supply voltage). The gate transistor Tr has a gate connected to the word line WL (WL1, WL2,...).

  The sense amplifier region 3 includes a sense amplifier SA1 and a precharge circuit PDLU1.

  The sense amplifier SA1 includes PMOS transistors TP11 and TP12 and NMOS transistors TN11 and TN12. The PMOS transistor TP11 and the NMOS transistor TN11 are connected in series between the sense amplifier control lines SAP and SAN. The PMOS transistor TP12 and the NMOS transistor TN12 are also connected in series between the sense amplifier control lines SAP and SAN. A connection node A1 between the PMOS transistor TP11 and the NMOS transistor TN11 is connected to the bit line D and the gates of the PMOS transistor TP12 and the NMOS transistor TN12. The connection node A2 between the PMOS transistor TP12 and the NMOS transistor TN12 is connected to the bit line DB and the gates of the PMOS transistor TP11 and the NMOS transistor TN11.

  The precharge circuit PDLU1 includes NMOS transistors TN21, TN22, and TN23. The NMOS transistor TN21 is connected between the bit line pair D and DB. The NMOS transistor TN22 is connected to the HVDD terminal and the bit line D, and the NMOS transistor TN23 is connected to the HVDD terminal and the bit line DB. A precharge control line PDL is connected to the gates of the NMOS transistors TN21, TN22, and TN23. For convenience, the symbols “WL”, “SAP”, “SAN”, and “PDL” indicate the name of a signal and the name of a signal applied to the wiring.

  The driver area 4 includes driver amplifiers AMP1, AMP2,. Furthermore, driver amplifiers AMP11, AMP12, and AMP20 are provided. The amplifiers AMP1, AMP2, ... apply word signals WL1, WL2, ... to the word lines WL1, WL2, ..., respectively. The power supply voltages of the driver amplifiers AMP1, AMP2,... Are supplied from the VPP power supply 10. The voltage VPP supplied by the VPP power supply 10 is higher than the power supply voltage VDD.

  The driver amplifiers AMP11 and AMP12 apply the sense amplifier signals SAP and SAN to the sense amplifier control lines SAP and SAN, respectively, according to the control signal SE. The power supply voltage of the amplifier AMP11 is supplied from the VDD power supply 20. The VDD power supply 20 supplies a power supply voltage VDD. The driver amplifier AMP12 supplies the ground voltage GND to the sense amplifier control line SAN according to the control signal SE.

  The driver amplifier AMP20 applies a precharge control signal PDL to the precharge control line PDL. The power supply voltage of the driver amplifier AMP20 is supplied from the VPDL power supply 30. The voltage VPDL supplied from the VPDL power supply 30 is higher than the power supply voltage VDD. The reason why the voltage VPDL is made higher than the power supply voltage VDD is as follows. First, as described above, the precharge voltage of the bit line pair D and DB is ½ VDD. For this reason, if the potential of the high-level precharge control signal PDL is the power supply voltage VDD, the potential difference between the gate and the drain (or source) is about ½ VDD. For this reason, there is a possibility that the NMOS transistors TN21 to TN23 cannot be activated quickly and sufficiently. In particular, this phenomenon becomes prominent when the power supply voltage VDD is lowered. Therefore, in order to increase the operating speed of the precharge circuit, it is necessary to apply a voltage higher than the power supply voltage VDD (for example, about VDD + 0.5 V) to the gates of the NMOS transistors TN21 to TN23.

  Here, a transistor having a gate oxide film thickness having a breakdown voltage in the range of the normal power supply voltage VDD is referred to as a thin film transistor, and a transistor including a gate oxide film thicker than the gate oxide film thickness of the thin film transistor is referred to as a thick film transistor. In the conventional semiconductor memory circuit 1, as shown in FIG. 12, a thick film transistor is used as a constituent transistor. Such a thick film transistor has a withstand voltage characteristic of a relatively high voltage (for example, 1.5 V or more). However, the thicker the gate oxide film is, the larger the channel length is required. Therefore, the thick film transistor has a problem of increasing the layout area.

  FIG. 13 shows a timing chart for explaining the operation of the semiconductor memory circuit 1. However, this example shows a case where the memory cell CELL1 holding high-level information is selected and the information is read out to the bit line. Further, it is assumed that the bit line pair D, DB is precharged at 1/2 VDD.

  As shown in FIG. 13, at time t1, the word signal WL1 rises and becomes the voltage VPP. At this time, since high level information is held in the memory cell CELL1, the potential of the bit line D slightly increases. At time t2, the control signal SE becomes high level, the sense amplifier control signal SAP becomes the power supply voltage VDD, and the sense amplifier control signal SAN becomes the ground voltage GND. Therefore, the sense amplifier SA1 starts a sensing operation, and amplifies the potential difference between the bit line pair D and DB to the power supply voltage VDD and the ground voltage GND. Then, the amplified potential difference between the bit line pair D and DB is read out to an external circuit.

  Thereafter, at time t3, the word signal WL1 falls to the ground voltage GND. Therefore, the cell node of the memory cell CELL1 and the bit line D are electrically disconnected. Further, the control signal SE also falls to the ground voltage GND. For this reason, the sense amplifier SA1 stops the sensing operation. At time t4, the precharge control signal PDL rises to the voltage VPDL, and the bit line pair D, DB is precharged to 1/2 VDD again. The above is the description of the operation of the conventional semiconductor memory circuit 1.

  In recent years, there has been a demand for higher integration and higher performance of semiconductor integrated devices such as system LSIs. For this reason, the miniaturization of the manufacturing process of the semiconductor integrated device is progressing so that it can operate at high speed, and the power supply voltage is also lowered. In such a system LSI, a logic circuit and a storage circuit such as a DRAM are mixedly mounted. Therefore, a circuit such as the semiconductor memory circuit 1 as described above is also formed into one chip together with a logic circuit that operates at high speed. For this reason, the semiconductor memory circuit 1 is also required to be increased in speed and integration, and in order to reduce the chip area and increase the speed, the gate oxide film of the transistor to be formed is becoming thinner.

  Here, the NMOS transistors TP11, TP12, TN11, and TN12 constituting the sense amplifier SA1 are required to have a breakdown voltage of about the power supply voltage VDD at the maximum. For this reason, low-voltage thin film transistors for power supply voltages having a reduced potential can be used for the NMOS transistors TP11, TP12, TN11, and TN12. However, as described above, the high potential VPP is applied to the gate of the gate transistor Tr of the memory cell. As such a gate transistor Tr, it is difficult to reduce the thickness of the gate oxide film, and a thick film transistor having a relatively thick gate oxide film must be used.

  Further, a system LSI incorporating such a semiconductor memory circuit 1 has a logic circuit as a peripheral circuit of the semiconductor memory circuit 1 as described above. This logic circuit performs logic processing using data held by the semiconductor memory circuit 1. Such a logic circuit is required to operate at high speed, and the thinnest transistor is used in a semiconductor integrated device such as a system LSI. As an example in which a transistor having a different gate oxide film thickness is used in one semiconductor integrated device as in this system LSI, there is a technique as described in Patent Document 1.

JP 2001-15704 A

  In the technology of Patent Document 1, a thick film transistor is used as a cell transistor of a memory cell, a precharge MOS transistor, and a thin film transistor that is also used in a logic circuit is used as a sense amplifier. Patent Document 1 describes that a high voltage is not applied to such a thin-film precharge MOS transistor. However, the operation speed of the precharge circuit cannot be increased unless the transistor used in the precharge circuit is applied with a voltage higher than the power supply voltage as in the semiconductor memory circuit 1. For this reason, the semiconductor integrated device configured by the technique of Patent Document 1 has a problem in that the high-speed operation is limited.

  The present invention is a semiconductor integrated device having a semiconductor memory circuit and a peripheral circuit for controlling the semiconductor memory circuit, the peripheral circuit being driven by a power supply voltage and having a first gate oxide film thickness. The semiconductor memory circuit includes a bit line pair connected to one of the gate transistors of the memory cell, a precharge circuit for precharging the bit line pair to a predetermined precharge voltage, and A sense amplifier that is driven by the power supply voltage and amplifies a potential difference between the pair of bit lines, and the precharge circuit includes a second transistor having the first gate oxide film thickness, A precharge control signal having a first voltage for activating the precharge circuit is applied to the gates of the two transistors, and the first voltage is derived from the power supply voltage. At a high potential, and the or less voltage level amount corresponding high voltage of said power supply voltage than the precharge voltage.

  The semiconductor integrated device according to the present invention can operate at high speed.

1 is a semiconductor integrated device according to a first exemplary embodiment; 1 is a semiconductor memory circuit according to a first embodiment; 3 is a timing chart illustrating an operation of the semiconductor memory circuit according to the first embodiment; FIG. 3 is a schematic diagram showing a gate-drain voltage relationship of a thin film transistor constituting the precharge circuit according to the first embodiment. FIG. 3 is a schematic diagram showing a gate-drain voltage relationship of a thin film transistor constituting the precharge circuit according to the first embodiment. 3 is a table showing differences between the conventional technology and the semiconductor memory circuit according to the first embodiment; 3 is a semiconductor memory circuit according to a second embodiment; 6 is a timing chart illustrating an operation of the semiconductor memory circuit according to the second embodiment; FIG. 6 is a schematic diagram illustrating a relationship between a gate-drain voltage of a thin film transistor included in a precharge circuit according to a second embodiment. FIG. 6 is a schematic diagram illustrating a relationship between a gate-drain voltage of a thin film transistor included in a precharge circuit according to a second embodiment. 10 is a table showing differences between the conventional technology and the semiconductor memory circuit according to the first and second embodiments. This is a conventional semiconductor memory circuit. 6 is a timing chart showing the operation of a conventional semiconductor memory circuit.

  Embodiment 1 of the Invention

  Hereinafter, a specific first embodiment to which the present invention is applied will be described in detail with reference to the drawings. In the first embodiment, the present invention is applied to a semiconductor integrated device 100 such as a system LSI. A schematic diagram of a system LSI chip of the semiconductor integrated device 100 is shown in FIG. As shown in FIG. 1, the semiconductor integrated device 100 includes a semiconductor memory circuit 101 and a logic circuit 105.

  The logic circuit 105 is integrated with logic gates that perform logic operations, such as a control circuit such as a CPU of the semiconductor integrated device 100 and an address decoder of the semiconductor memory circuit 101. Here, the semiconductor integrated device 100 such as a system LSI is required to have high performance. For this reason, the logic operation by the logic gates constituting the logic circuit 105 is also required to operate at high speed. Therefore, in the logic circuit 105, the manufacturing process of the transistors forming the logic gate can be miniaturized so that the logic gate can operate as fast as possible. In this miniaturization, the gate oxide film of the transistor is thinned. For this reason, the transistors constituting the logic circuit 105 are most miniaturized in the semiconductor integrated device 100, and the thinning is promoted.

  As the gate oxide film becomes thinner, the breakdown voltage of the transistor naturally decreases. Therefore, the operating voltage of the logic gate must be lowered, and the power supply voltage VDD can be lowered. For this reason, the power supply voltage VDD of the logic circuit 105 is lowered to be, for example, 1.0 V or less.

  Hereinafter, unless otherwise specified, it is assumed that the power supply voltage VDD in the first embodiment is a reduced power supply voltage (for example, 1.0 V or less) used in the logic circuit 105. Further, a transistor including a gate oxide film having a withstand voltage of about a low power supply voltage VDD as used in the logic circuit 105 is referred to as a thin film transistor. On the other hand, a transistor having a withstand voltage with a voltage higher than the power supply voltage VDD needs to have a thicker gate oxide film than the above-described thin film transistor. For this reason, such a transistor is referred to as a thick film transistor.

  The semiconductor memory circuit 101 is a built-in DRAM of the semiconductor integrated device 100. The semiconductor memory circuit 101 holds data processed by the logic circuit 105. As illustrated in FIG. 1, the semiconductor memory circuit 101 includes a cell array region 102, a sense amplifier region 103, and a driver region 104. An example of the circuit configuration of such a semiconductor memory circuit 101 is shown in FIG. In the first embodiment, however, the semiconductor memory circuit 101 shown in FIG. 2 is described as a DRAM circuit composed of one bit line pair in order to avoid making the figure complicated. Note that the semiconductor memory circuit 101 may further include a plurality of bit line pairs and memory cells, sense amplifiers, precharge circuits, and the like connected to the bit line pairs. Further, the semiconductor memory circuit 101 is not limited to a DRAM but may be an SRAM or the like.

  The cell array region 102 has a plurality of memory cells CELL (CELL101, CELL102,...).

  Each memory cell is connected to one of the bit line pair D and DB. Each memory cell has a gate transistor Tr and a cell capacitor Ccell. In the gate transistor Tr, one of the drain and the source is connected to one of the bit lines D and DB, and the other of the drain and the source is connected to the cell capacitor Ccell. A connection point between the gate transistor Tr and the cell capacitor Ccell is a cell node. A terminal on the opposite side of the cell node of the cell capacitor Ccell is connected to the HVDD terminal. The HVDD terminal is supplied with a voltage of ½ VDD (VDD: power supply voltage). Each gate transistor Tr has a gate connected to a word line WL (WL101, WL102,...). For convenience, reference numerals “WL101”, “WL102”,... Indicate the word line names and the names of word signals applied to the word lines.

  For example, when the word signal WL101 becomes high level, the gate transistor of the memory cell CELL101 is turned on, and the cell node and the bit line D are electrically connected. Further, when the word signal WL102 becomes high level, the gate transistor of the memory cell CELL102 is turned on, and the cell node and the bit line D are electrically connected. When one of the word signals WL101, WL102,... Is selected and becomes high level, all other word lines are at low level. Therefore, when the word signal of a selected word signal line becomes high level, the information held in the memory cell connected to this word signal line is read to the bit line. Other memory cells are not selected. As will be described later, each word signal at the high level is VPP having a higher potential than the power supply voltage VDD. This is to increase the activation speed of the gate transistor and reduce the on-resistance. Therefore, each gate transistor Tr is required to have a high breakdown voltage, and is therefore formed of a thick film transistor.

  The sense amplifier region 103 includes a sense amplifier SA101 and a precharge circuit PDLU101.

  The sense amplifier SA101 includes PMOS transistors TP111 and TP112 and NMOS transistors TN111 and TN112. The PMOS transistor TP111 and the NMOS transistor TN111 are connected in series between the sense amplifier control lines SAP and SAN. The PMOS transistor TP112 and the NMOS transistor TN112 are also connected in series between the sense amplifier control lines SAP and SAN. A connection node A1 between the PMOS transistor TP111 and the NMOS transistor TN111 is connected to the bit line D and the gates of the PMOS transistor TP112 and the NMOS transistor TN112. The connection node A2 between the PMOS transistor TP112 and the NMOS transistor TN112 is connected to the bit line DB and the gates of the PMOS transistor TP111 and the NMOS transistor TN111. For convenience, the symbols “SAP” and “SAN” indicate the name of the sense amplifier control line and the name of the sense amplifier control signal applied to the sense amplifier control line. As will be described later, when the control signal SE is at a high level, the sense amplifier control signal SAP becomes the power supply voltage VDD, and the sense amplifier control signal SAN becomes the ground voltage GND. Therefore, the voltage between the gate and the drain (or the source) of the PMOS transistors TP111 and TP112 and the NMOS transistors TN111 and TN112 is about the power supply voltage VDD at the maximum. For this reason, the thin film transistor is configured to have a withstand voltage with respect to the power supply voltage VDD whose voltage is lowered.

  The precharge circuit PDLU101 includes NMOS transistors TN121, TN122, and TN123. The NMOS transistor TN121 is connected between the bit line pair D and DB. The NMOS transistor TN122 is connected to the HVDD terminal and the bit line D, and the NMOS transistor TN123 is connected to the HVDD terminal and the bit line DB. A precharge control line PDL is connected to the gates of the NMOS transistors TN121, TN122, and TN123. For convenience, the symbol “PDL” indicates the name of a precharge control line and also indicates the name of a precharge control signal applied to the precharge control line.

  The driver area 104 includes driver amplifiers AMP101, AMP102,. Further, driver amplifiers AMP111, AMP112, and AMP120 are provided.

  The driver amplifiers AMP101, AMP102, ... apply word signals WL101, WL102, ... to the word lines WL101, WL102, ..., respectively. The power supply voltage on the high potential side of the driver amplifiers AMP101, AMP102,... Therefore, the power supply terminals on the high potential side of the driver amplifiers AMP101, AMP102,... Are connected to the terminal 130. Further, the power supply voltage on the low potential side is connected to the ground terminal GND. The voltage VPP supplied from the VPP power supply 110 is higher than the power supply voltage VDD. For example, it is assumed that it is about 1.5 times the power supply voltage VDD. From this, when the power supply voltage VDD is 1.0V, it becomes about 1.5V, and when the power supply voltage VDD is 0.8V, it becomes about 1.2V.

  The driver amplifiers AMP111 and AMP112 apply the sense amplifier control signals SAP and SAN to the sense amplifier control lines SAP and SAN, respectively, according to the control signal SE. The power supply voltage of the amplifier AMP111 is supplied from the VDD power supply 120. The VDD power supply 120 supplies the power supply voltage VDD. The driver amplifier AMP112 supplies the ground voltage GND to the sense amplifier control line SAN according to the control signal SE.

  The driver amplifier AMP120 applies a precharge control signal PDL to the precharge control line PDL. The power supply voltage on the high potential side of the driver amplifier AMP103 is supplied from the VPP power supply 110. Therefore, the potential of the high-level precharge control signal PDL is VPP. The power supply terminal of the driver amplifier AMP120 is connected to the terminal 130 like the driver amplifiers AMP101, AMP102,. Further, the power supply voltage on the low potential side is connected to the ground terminal GND. Therefore, the potential of the low-level precharge control signal PDL becomes the ground potential GND. For convenience, the symbols “VDD” and “GND” indicate the power supply voltage and the ground voltage, as well as the respective terminal names.

  FIG. 3 is a timing chart for explaining the operation of the semiconductor memory circuit 101. However, this example shows a case where the memory cell CELL 101 holding high level information is selected and the information is read out to the bit line D. Further, it is assumed that the bit line pair D, DB before time t1 is precharged at 1/2 VDD.

  As shown in FIG. 3, at time t1, the word signal WL101 rises and changes from the ground voltage GND to the voltage VPP. Therefore, the gate transistor of the memory cell CELL101 is turned on, and the cell node and the bit line D are electrically connected. The cell node holds high level data, and charges flow out to the bit line D. For this reason, the potential of the cell node decreases, but the potential of the bit line D slightly increases.

  Next, at time t2, the control signal SE becomes high level. Therefore, the sense amplifier control signal SAP becomes the power supply voltage VDD, and the sense amplifier control signal SAN becomes the ground voltage GND. Therefore, the sense amplifier SA101 starts a sensing operation. The sense amplifier SA101 amplifies the potential difference between the slightly opened bit line pair D and DB described above to the power supply voltage VDD and the ground voltage GND. Note that the amplified potential difference between the pair of bit lines D and DB is read as high-level data as read data from the semiconductor memory circuit 101 by an external circuit and used for data processing of the logic circuit 105 and the like. Further, the potential of the cell node of the memory cell CELL101 also rises.

  Thereafter, at time t3, the word signal WL101 and the control signal SE fall to the ground voltage GND. Therefore, the gate transistor of the memory cell CELL101 is turned off, and the cell node of the memory cell CELL101 and the bit line D are electrically cut off. Further, the sense amplifier SA101 stops the sensing operation.

  At time t4, the precharge control signal PDL rises from the ground voltage GND to the voltage VPP. Therefore, the NMOS transistors TN121, TN122, and TN123 of the precharge circuit PDLU101 are turned on. Therefore, the bit line pair D, DB is equalized and charged to 1/2 VDD, and precharged again to 1/2 VDD. The above is the description of the operation of the semiconductor memory circuit 101.

  Here, VPP having a higher potential than the power supply voltage VDD is applied between the gates and drains (or sources) of the NMOS transistors TN121, TN122, and TN123 of the thin film transistor having only the withstand voltage of the power supply voltage VDD. For this reason, it is conceivable that the NMOS transistors TN121, TN122, and TN123 are broken down. Here, the voltage relationship between the gate and drain (or source) of the NMOS transistors TN121, TN122, and TN123 is divided into the cases where the precharge control signal PDL is at the high level and the low level, as shown in FIGS. 5 (a) and 5 (b) are schematic diagrams. 4A and 4B show an example of the NMOS transistor TN121, and FIGS. 5A and 5B show examples of the NMOS transistor TN122.

  First, as shown in FIG. 4A, when the precharge control signal PDL is at a low level, the ground voltage GND is applied to the precharge control line PDL. Note that the period during which the precharge control signal PDL is at a low level corresponds to the period from time t1 to time t3 in FIG. For this reason, the power supply voltage VDD is applied to the bit line D as the maximum voltage, and the ground voltage GND is applied to the bit line DB as the minimum voltage. Therefore, the voltage between the gate and drain (or source) of the NMOS transistor TN121 is about the power supply voltage VDD at the maximum.

  Further, as shown in FIG. 4B, when the precharge control signal PDL is at a high level, the voltage VPP is applied to the precharge control line PDL. Note that the period in which the precharge control signal PDL is at a high level corresponds to the period after time t4 in FIG. At this time, the bit line pair D, DB is precharged to ½ VDD. Therefore, 1 / 2VDD is applied to the drain (or source) of the NMOS transistor TN121, and even if the voltage VPP is applied to the gate, the potential difference of (VPP−1 / 2VDD) or the gate and drain (or source). ) It doesn't take in between.

  As can be seen from FIGS. 4A and 4B, for example, when the power supply voltage VDD is 1.0 V and the voltage VPP is 1.5 V, the voltage applied between the gate and drain (or source) of the NMOS transistor TN121. Is about 1.0 V at the maximum. For this reason, even if a thin film transistor having a breakdown voltage of about the power supply voltage VDD is used for the precharge circuit PDLU101, the transistor does not break down. Further, the timing at which the word signal WL101 is activated and the timing at which the precharge control signal PDL is activated have almost no overlapping period as can be seen from FIG. Therefore, the generation periods of the charge / discharge peak current of the VPP power supply 110 do not overlap.

  Next, as shown in FIG. 5A, when the precharge control signal PDL is at low level, the ground voltage GND is applied to the precharge control line PDL. Therefore, the power supply voltage VDD is applied to the bit line D as the maximum voltage, and 1/2 VDD is applied to the HVDD terminal. Therefore, the voltage between the gate and drain (or source) of the NMOS transistor TN122 is about the power supply voltage VDD at the maximum.

  As shown in FIG. 5B, when the precharge control signal PDL is at a high level, the voltage VPP is applied to the precharge control line PDL. At this time, the bit line D is precharged to ½ VDD. Therefore, 1 / 2VDD is applied to the drain (or source) of the NMOS transistor TN122, and even if the voltage VPP is applied to the gate, the potential difference of (VPP−1 / 2VDD) or the gate and drain (or source). ) It doesn't take in between.

  As can be seen from FIGS. 5A and 5B, for example, when the power supply voltage VDD is 1.0 V and the voltage VPP is 1.5 V, the voltage is applied between the gate and drain (or source) of the NMOS transistor TN122. The voltage is 1.0 V at the maximum, and a thin film transistor having a withstand voltage corresponding to the power supply voltage VDD can be used like the NMOS transistor TN121. The same applies to the NMOS transistor TN123.

  Based on the above, FIG. 6 shows a table summarizing the relationship between the conventional semiconductor memory circuit 1, the technique of Patent Document 1, and the semiconductor memory circuit 101 of the first embodiment. First, in the conventional semiconductor memory circuit 1, the power supply voltage VDD is a high voltage (higher than 1.0 V). The voltages VPP and VPDL are supplied from the VPP power supply 10 and the VPDL power supply 30 by boosting the power supply voltage VDD. For this reason, the gate transistor of the memory cell, the transistor of the sense amplifier, and the transistor of the precharge circuit are all thick film transistors having a high breakdown voltage. If the transistor of the precharge circuit is a thick film transistor, the speed of the precharge circuit can be increased by the boosted voltage VPDL. However, the thick film transistor cannot reduce the layout area. For this reason, it is difficult to reduce the circuit scale and speed up the circuit operation.

  Even if the manufacturing process is further miniaturized and the transistor of the sense amplifier SA101, which requires only a withstand voltage of the reduced power supply voltage VDD, can be thinned, the gate oxide film of the transistor of the precharge circuit can be thinned. I can't proceed. Therefore, there is a possibility that the pitch of the precharge circuit PDLU101 will not fit in the pitch of the sense amplifier SA101, which causes a problem.

  With the miniaturization of the manufacturing process and the lowering of the power supply voltage VDD (for example, about 1.0 V), a low breakdown voltage thin film transistor is used as a transistor constituting the semiconductor integrated device. Therefore, in the technique of Patent Document 1, a high breakdown voltage thick film transistor is used as the gate transistor of the memory cell, but a low breakdown voltage used in the logic circuit is used as the sense amplifier transistor and the precharge circuit transistor. The thin film transistor is used. Therefore, the problem that the precharge circuit pitch does not fit in the pitch of the sense amplifier such as the semiconductor memory circuit 1 is solved. However, in the technique of Patent Document 1, since a high voltage is not applied to the transistors of the precharge circuit, there is a limit to increasing the operation speed of the precharge circuit.

  For this reason, in the semiconductor memory circuit 101 of the first embodiment, a word having a higher potential than the power supply voltage VDD is used while using a thin film transistor having a withstand voltage of about the power supply voltage VDD which is reduced in voltage as the transistor constituting the precharge circuit. The voltage VPP for generating a signal is also used for the precharge control signal PDL. This voltage VPP has been lowered by lowering the power supply voltage VDD. When these VDD and VPP are below a certain level (for example, VDD is 1.0 V or less and VPP is 1.5 V or less), as described in FIGS. 4A and 4B and FIGS. 5A and 5B, A thin film transistor having a breakdown voltage of about the power supply voltage VDD can be used without causing dielectric breakdown. Therefore, without causing dielectric breakdown of the gate oxide film, VPP having a higher potential than the power supply voltage VDD is used for the precharge control signal PDL, and the operation speed of the precharge circuit can be increased.

  Further, as shown in FIG. 2, the voltage VPP is supplied from the terminal 130 to the driver amplifiers AMP101, AMP102,... And the driver amplifier AMP120 by the VPP power supply 110. Therefore, it is not necessary to provide the VPDL power supply 30 unlike the semiconductor memory circuit 1, and only the VPP power supply 110 is sufficient. For this reason, in the semiconductor memory circuit 101, the power supply can be reduced by one as compared with the semiconductor memory circuit 1, and the circuit scale can be reduced.

  Further, in the semiconductor memory circuit 1, since the VPP power supply 10 and the VPDL power supply 30 are different, it is necessary to separate the power supply wiring network, and the wiring layer of the chip has to be increased. Furthermore, a decoupling capacitor for preventing crosstalk between the wiring networks is also necessary. However, since the semiconductor memory circuit 101 of the first embodiment has only the VPP power supply 110, the above-described double wiring layer and decoupling capacitance are not necessary, which also contributes to a reduction in circuit scale.

  Further, as described above, since the generation periods of the charge / discharge peak currents of the VPP power supply 110 do not overlap, it is not particularly necessary to reinforce the power supply of the VPP power supply 110, and there is no increase factor in circuit scale. Therefore, circuit design is facilitated, and the design period can be shortened, design errors can be reduced, design costs can be reduced, and the like.

  Embodiment 2 of the Invention

Hereinafter, a specific second embodiment to which the present invention is applied will be described in detail with reference to the drawings. In the second embodiment, as in the first embodiment, the present invention is applied to a semiconductor integrated device such as a system LSI. The semiconductor integrated device 200 of the second embodiment is different in the configuration of the semiconductor memory circuit portion of the first embodiment. The semiconductor memory circuit of the second embodiment is referred to as a semiconductor memory circuit 201. That is, the semiconductor integrated device 200 of the second embodiment has a configuration in which the semiconductor memory circuit 101 of the semiconductor integrated device 100 of FIG.
The semiconductor integrated device 200 includes a semiconductor memory circuit 201 and a logic circuit 105. The semiconductor memory circuit 201 is a system LSI embedded DRAM as in the first embodiment. In the second embodiment, the state in which the thinning of the transistors constituting the logic circuit 105 that is a peripheral circuit of the semiconductor memory circuit 201 and the reduction of the power supply voltage are further advanced than in the first embodiment (for example, VDD = 0). .8V or less).

  FIG. 7 shows a configuration of the semiconductor memory circuit 201 according to the second embodiment. As shown in FIG. 7, the semiconductor memory circuit 201 includes a cell array region 202, a sense amplifier region 103, and a driver region 204. In addition, the structure which attached | subjected the code | symbol same as FIG. 2 among the code | symbols shown in FIG. 7 has shown the same or similar structure as FIG. The difference from the first embodiment is a cell array region 202 and a driver region 204. In the second embodiment, the difference will be mainly described, and the description of the other components similar to those in the first embodiment will be omitted.

  The cell array region 202 has a plurality of memory cells CELL (CELL 201, CELL 202,...). Each memory cell is connected to a pair of bit lines D and DB as in the first embodiment. Each memory cell has a gate transistor Tr and a cell capacitor Ccell. Here, the memory cell of the second embodiment is different from that of the first embodiment in that the gate transistor Tr is formed of a thin film transistor similar to the logic circuit 105. For this reason, the circuit scale of the cell array region 202 can be reduced. Other configurations are the same as those in the first embodiment.

  The driver area 204 includes driver amplifiers AMP201, AMP202,. Further, driver amplifiers AMP111, AMP112, and AMP120 are provided. The driver amplifiers AMP201, AMP202,... Generate word signals WL201, WL202,. In response to the word signals WL201, WL202,..., The gate transistors Tr of the memory cells CELL201, CELL202,. Here, the memory cell of the second embodiment differs from the first embodiment in that the voltage VPPL supplied from the VPP power supply 110 to the high-potential side power supply voltage of the driver amplifiers AMP201, AMP202,. The voltage VKK supplied from the VKK power supply 140 is used as the power supply voltage on the side. Therefore, the potential of the selected word signal (high level) is the voltage VPPL, and the potential of the unselected word signal (low level) is the voltage VKK.

  As described above, the power supply voltage VDD is lower than that in the first embodiment, and the voltage VPP is also naturally reduced. Further, the gate transistor Tr of the memory cell is a thin film transistor, and the gate oxide film is made thinner than in the first embodiment. Therefore, the VPP power supply 110 supplies a voltage VPPL that is lower than the voltage VPP of the first embodiment in order to prevent dielectric breakdown of the gate transistor Tr. For example, when the power supply voltage VDD is 0.8 V, the voltage VPPL can be about 1.5 V, which is about 1.2 V. In this case, a voltage higher than the power supply voltage VDD is applied to the gate transistor Tr of the thin film transistor. However, the semiconductor memory circuit 201 can operate at high speed by miniaturization, and the period during which a high-level word signal is applied to the gate transistor Tr of the selected memory cell is short. Also, the probability that the same memory cell is always selected in the plurality of memory cells CELL101, CELL102,... Is very low. Furthermore, VPPL is lowered to about 1.2V. For these reasons, even when the voltage VPPL higher than the power supply voltage VDD is applied to the gate transistor Tr of the thin film transistor, the possibility of dielectric breakdown is very low, and the thinned gate transistor Tr is formed as in the second embodiment. There is no problem even if it is used.

  On the other hand, the voltage VKK supplied by the VKK power supply 140 is a negative voltage lower than the ground voltage GND. For example, the voltage VKK supplied by the VKK power supply 140 includes a voltage of −0.3V or less. This voltage VKK is supplied to the low potential side power supply terminals of the driver amplifiers AMP201, AMP202,. For this reason, the potential of the non-selected word line can be made negative. By this negativeization, the voltage VPPL supplied from the VPP power supply 110 can be further reduced. For example, the voltage VPPL supplied from the VPP power supply 110 can be reduced to about 1.0V. For this reason, the gate transistor Tr of each memory cell in the cell array region 202 can be further thinned. In addition, the possibility of dielectric breakdown of the gate transistor Tr can be further reduced. At the same time, the back gate voltage of the gate transistor Tr may be negativeized.

  FIG. 8 shows a timing chart for explaining the operation of the semiconductor memory circuit 201. However, this example shows a case where the memory cell CELL 201 holding high-level information is selected and the information is read out to the bit line D. Further, it is assumed that the bit line pair D, DB before time t1 is precharged at 1/2 VDD. The power supply voltage VDD is 0.8V, the voltage VPPL is 1.0V, and the voltage VKK is −0.3V.

  As shown in FIG. 8, the word signal WL201 rises at time t1 and changes from the voltage VKK to the voltage VPP. Therefore, the gate transistor of the memory cell CELL201 is turned on, and the cell node and the bit line D are electrically connected. The cell node holds high level data, and charges flow out to the bit line D. For this reason, the potential of the cell node decreases, but the potential of the bit line D slightly increases.

  Next, at time t2, the control signal SE becomes high level. Therefore, the sense amplifier control signal SAP becomes the power supply voltage VDD, and the sense amplifier control signal SAN becomes the ground voltage GND. Therefore, the sense amplifier SA101 starts a sensing operation. The sense amplifier SA101 amplifies the potential difference between the slightly opened bit line pair D and DB described above to the power supply voltage VDD and the ground voltage GND. Note that the amplified potential difference between the pair of bit lines D and DB is read as high-level data as read data from the semiconductor memory circuit 201 by an external circuit and used for data processing of the logic circuit 105 and the like. Further, the potential of the cell node of the memory cell CELL201 also rises.

  Thereafter, at time t3, the word signal WL201 falls to the voltage VKK, and the control signal SE falls to the ground voltage GND. Therefore, the gate transistor of the memory cell CELL201 is turned off, and the cell node of the memory cell CELL201 and the bit line D are electrically disconnected. Further, the sense amplifier SA101 stops the sensing operation.

  At time t4, the precharge control signal PDL rises from the ground voltage GND to the voltage VPP. Therefore, the NMOS transistors TN121, TN122, and TN123 of the precharge circuit PDLU101 are turned on. Therefore, the bit line pair D, DB is smoothed and charged to 1/2 VDD, and precharged to 1/2 VDD again. The above is the description of the operation of the semiconductor memory circuit 201.

  Here, the voltage relationship between the gates and drains (or sources) of the NMOS transistors TN121, TN122, and TN123 is shown in FIGS. 9A and 10A when the precharge control signal PDL is at a low level. When the signal PDL is at a high level, FIG. 9B and FIG. As can be seen from these schematic diagrams, as in the first embodiment, the voltage between the gate and drain (or source) of the NMOS transistors TN121, TN122, and TN123 is at most the power supply voltage VDD or less. In this example, since the precharge voltage of the bit line pair is ½ VDD (0.4 V), as can be seen from FIGS. 9B and 10B, the precharge control signal PDL is at the high level. The voltage between the gate and drain (or source) at that time is 0.6V. Therefore, even when the precharge voltage is lowered to 0.2 V, the voltage between the gate and the drain (or source) can be kept below the power supply voltage VDD. Therefore, the precharge voltage of the bit line pair D and DB can be reduced to 1/2 VDD or less.

  FIG. 11 shows a table summarizing the relationship between the conventional semiconductor memory circuit 1, the technique of Patent Document 1, the semiconductor memory circuit 101 of the first embodiment, and the semiconductor memory circuit 201. In this table, the relationship of the semiconductor memory circuit 201 is added to the table of FIG. As shown in FIG. 11, the semiconductor memory circuit 201 uses low-voltage thin film transistors for the gate transistors of the memory cells, the transistors of the sense amplifier, and the transistors of the precharge circuit. The maximum voltage applied to the gate transistor Tr and the gate of the precharge circuit transistor is also VPPL (<VPP).

  As described above, in the semiconductor memory circuit 201 of the second embodiment, all of the gate transistors Tr of the memory cells, the sense amplifier SA101, and the transistors of the precharge circuit PDLU101 are made of the same thin film transistor as the logic circuit 105 that is miniaturized and reduced in power supply voltage. Configure. This makes it unnecessary to divide the gate oxide film of the transistor into a thick film or a thin film when manufacturing the LSI chip, and to simplify the manufacturing process. Further, it is possible to reduce the manufacturing cost and the period due to the simplification of the manufacturing process. Further, in the semiconductor memory circuit 201 of the second embodiment, the voltage VPP is lowered by making the word signal negative or the like. Even in such a configuration, as in the first embodiment, a thin film transistor having a tolerance of about the power supply voltage VDD can be used in the precharge circuit, and the voltage VPP used in the word signal can be used as the precharge control signal PDL. . In the second embodiment, the circuit scale of the cell array region 202 can be reduced. Further, the supply voltage of the VPP power supply 110 can be further reduced, and the transistor size can be reduced by further reducing the gate oxide film of the transistor of the precharge circuit. In addition, power consumption can be reduced due to a decrease in power supply voltage. Other effects are the same as those of the first embodiment.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. For example, the above-described circuit configuration of the sense amplifier has been described as a type driven by a general power supply voltage, but of course, the present invention is not limited to this, and it goes without saying that various sense amplifier variations are applicable. Absent. As an example, a step-down power supply may be used as the power supply for the sense amplifier. Furthermore, an overdrive type circuit configuration that uses a voltage higher than the stepped down power supply (for example, a power supply voltage before stepping down) may be used only at the start of operation. Alternatively, a power source that does not step down may be used to operate at a voltage slightly higher than the above-described power source voltage only for a very short period during overdrive at the start of operation.

100, 200 Semiconductor integrated device 101, 201 Semiconductor memory circuit 102 Cell array region 103 Sense amplifier region 104 Driver region 105 Logic circuit 110 VPP power source 120 VDD power source 240 VKK power source CELL101, CELL102, CELL201, CELL202 Memory cell Tr Gate transistor Ccell Cell capacitance D , DB bit line pair SA101 sense amplifier PDLU precharge circuit TP111, TP112 PMOS transistors TN111, TN112, TN121 to TN123 NMOS transistors AMP101, AMP102, AMP111, AMP112, AMP120, AMP201, AMP202 driver amplifier

Claims (8)

A semiconductor integrated device having a semiconductor memory circuit and a peripheral circuit for controlling the semiconductor memory circuit,
The peripheral circuit includes a first transistor in which a breakdown voltage of the gate oxide film with respect to a power supply voltage of the peripheral circuit is a first voltage;
The semiconductor memory circuit is
A bit line pair connected to one of the gate transistors of the memory cell;
A precharge circuit for precharging the bit line pair to a predetermined precharge voltage;
A sense amplifier that amplifies the potential difference between the bit line pair to the power supply voltage and the ground voltage ;
Have
The precharge circuit includes a second transistor having a gate oxide film having a breakdown voltage of the first voltage, and a gate of the second transistor has a second voltage precharge that activates the precharge circuit. A control signal is applied,
The second voltage is higher than the first voltage and equal to or lower than a voltage higher than the precharge voltage by a voltage level of the first voltage. 2. The semiconductor integrated device according to claim 1, wherein a word signal of the second voltage that activates the gate transistor is applied to a word line connected to the gate transistor. A first driver amplifier for supplying the word signal to the word line;
A second driver amplifier for supplying the precharge control signal;
3. The semiconductor integrated device according to claim 2, wherein power supply terminals of the first and second driver amplifiers are respectively connected to voltage supply terminals that supply the second voltage. The first and second transistors have a first gate oxide thickness;
4. The semiconductor integrated device according to claim 1, wherein the gate transistor includes a third transistor having a second gate oxide film thickness larger than the first gate oxide film thickness. 5. The first and second transistors have a first gate oxide thickness;
4. The semiconductor integrated device according to claim 1, wherein the gate transistor includes a fourth transistor having the first gate oxide film thickness.   The semiconductor integrated device according to claim 1, wherein the precharge voltage is substantially ½ of the first voltage. The semiconductor integrated device according to claim 1, wherein the peripheral circuit is a logic circuit including an address decoder of the semiconductor memory circuit. A first driver amplifier that applies a word signal to a word line connected to the gate transistor of the memory cell; and a second driver amplifier that applies an activation signal to a precharge control line of the precharge circuit. And
2. The semiconductor integrated device according to claim 1, wherein a voltage lower than a voltage supplied to a low-potential-side power supply terminal of the second driver amplifier is supplied to a low-potential-side power supply terminal of the first driver amplifier. .

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