JP4212558B2 - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device Download PDF

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JP4212558B2
JP4212558B2 JP2004571838A JP2004571838A JP4212558B2 JP 4212558 B2 JP4212558 B2 JP 4212558B2 JP 2004571838 A JP2004571838 A JP 2004571838A JP 2004571838 A JP2004571838 A JP 2004571838A JP 4212558 B2 JP4212558 B2 JP 4212558B2
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circuit
power supply
voltage
semiconductor integrated
integrated circuit
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JPWO2004102780A1 (en
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雅文 山崎
敏也 内田
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Fujitsu Semiconductor Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4072—Circuits for initialization, powering up or down, clearing memory or presetting
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0083—Converters characterised by their input or output configuration
    • H02M1/009—Converters characterised by their input or output configuration having two or more independently controlled outputs

Description

本発明は、半導体集積回路装置に関し、特に、内部回路および該内部回路を制御する制御回路に昇圧電源回路で昇圧された出力電圧を用いる半導体集積回路装置に関する。   The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device that uses an output voltage boosted by a boost power supply circuit for an internal circuit and a control circuit that controls the internal circuit.

近年、半導体集積回路装置は、様々な携帯機器搭載されており、その電源電圧も低電圧化されている。そして、このような低電圧で駆動される半導体集積回路装置においては、昇圧電源回路が使用され、その昇圧電源回路で昇圧された出力電圧を使用して動作するようになっている。   In recent years, semiconductor integrated circuit devices have been mounted on various portable devices, and the power supply voltage has been lowered. In such a semiconductor integrated circuit device driven at a low voltage, a boost power supply circuit is used, and an operation is performed using an output voltage boosted by the boost power supply circuit.

ところで、例えば、ＤＲＡＭ（Dynamic Random Access Memory）においては、まず、電源を投入すると昇圧電源回路が動きだし、昇圧電源回路の出力電圧を利用する降圧電源回路がその昇圧された出力電圧（昇圧電圧）の電位が所定のレベルに達してから動作し、昇圧電圧を降圧電源回路で降圧して制御回路に印加し、その制御回路による内部回路のリセット（例えば、欠陥の生じたメモリセルの冗長処理等）を行っていた。さらに、ＤＲＡＭ以外の様々な半導体集積回路装置においても、内部回路と、その内部回路を制御する制御回路に対して昇圧電源回路で昇圧された出力電圧（昇圧電圧）を用いるものが提供されている。なお、制御回路に対しては、昇圧電圧を降圧電源回路で降圧した電圧を印加するもの以外に、昇圧電圧を直接印加する半導体集積回路装置もある。   By the way, for example, in a dynamic random access memory (DRAM), first, when power is turned on, the boost power supply circuit starts to operate, and the step-down power supply circuit that uses the output voltage of the boost power supply circuit generates the boosted output voltage (boost voltage). It operates after the potential reaches a predetermined level, and the boosted voltage is stepped down by the step-down power supply circuit and applied to the control circuit, and the internal circuit is reset by the control circuit (for example, redundancy processing of a defective memory cell) Had gone. Further, in various semiconductor integrated circuit devices other than DRAMs, devices using an output voltage (boosted voltage) boosted by a boost power supply circuit for an internal circuit and a control circuit for controlling the internal circuit are provided. . For the control circuit, there is a semiconductor integrated circuit device that directly applies the boosted voltage in addition to the voltage applied by stepping down the boosted voltage by the step-down power supply circuit.

このような内部降圧電源の制御に昇圧電源を用いる半導体集積回路装置（チップ）において、チップ内部の昇圧電圧（昇圧電源回路の出力電圧）を用いている回路に、例えば、製造上の原因によるリークがあった場合、その昇圧電源回路の出力の電位が十分上がらないことが考えられる。これは、例えば、ＤＲＡＭにおいて、リークの原因となる回路に冗長機能が設けられており、内部回路の起動時のリセット（パワーオンリセット）によって切り離すことができる回路であっても、リセットを行うことができずに不良となっていた。   In such a semiconductor integrated circuit device (chip) that uses a boosted power source for controlling the internal step-down power supply, for example, a leak due to a manufacturing cause may occur in a circuit that uses the boosted voltage inside the chip (output voltage of the boosted power supply circuit). If there is, it is conceivable that the output potential of the boost power supply circuit does not rise sufficiently. This is because, for example, in a DRAM, a circuit that causes a leak has a redundancy function, and even a circuit that can be disconnected by a reset (power-on reset) at the time of startup of an internal circuit is reset. I was unable to do so.

また、昇圧電源回路をそれぞれの回路毎に複数設けることも考えられるが、その場合には、昇圧電源回路のための素子数が増大し、また、専有面積も大きくなって好ましくない。   In addition, it is conceivable to provide a plurality of booster power supply circuits for each circuit, but in this case, the number of elements for the booster power supply circuit increases and the occupied area becomes large, which is not preferable.

なお、従来の半導体集積回路装置およびその問題点に関しては、後に図面を参照して詳述する。   A conventional semiconductor integrated circuit device and its problems will be described in detail later with reference to the drawings.

本発明は上述した従来技術が有する問題点に鑑みてなされたものであり、チップ内部（内部回路）に昇圧電圧からのリークがあった場合でも、正しく初期化動作を行うことができる半導体集積回路装置の提供を目的とする。   The present invention has been made in view of the above-described problems of the prior art, and a semiconductor integrated circuit capable of correctly performing an initialization operation even when there is a leak from a boosted voltage inside the chip (internal circuit). The purpose is to provide a device.

本発明によれば、昇圧電圧を発生する昇圧電源回路、該昇圧電圧により駆動される内部回路、前記昇圧電圧を降圧し、降圧電圧を出力する降圧電源回路、および、前記降圧電圧を受け取って前記内部回路を制御する制御回路を有し、前記昇圧電源回路は、前記内部回路用の第１の出力端子と、前記降圧電源回路用の第２の出力端子とを備え、前記昇圧電源回路は、前記第１の出力端子に対して直列に接続された第１のスイッチと、前記第２の出力端子に対して直列に接続された第２のスイッチと、前記第１のスイッチをオンするタイミングを、前記第２のスイッチをオンするタイミングよりも遅らせる遅延回路と、を備えることを特徴とする半導体集積回路装置が提供される。 According to the present invention, a boost power supply circuit that generates a boost voltage, an internal circuit driven by the boost voltage, a step-down power supply circuit that steps down the boost voltage and outputs a step-down voltage, and receives the step-down voltage and A control circuit for controlling an internal circuit, wherein the boost power supply circuit includes a first output terminal for the internal circuit and a second output terminal for the step-down power supply circuit; A first switch connected in series to the first output terminal; a second switch connected in series to the second output terminal; and a timing for turning on the first switch. There is provided a semiconductor integrated circuit device comprising a delay circuit that delays the second switch from a timing at which the second switch is turned on .

本発明においては、制御回路（降圧電源回路）を制御する昇圧電圧のために、昇圧電源回路から専用の取り出し端子を用意するようになっており、内部回路への昇圧電圧（昇圧電源線）と、制御回路への昇圧電圧を分けることにより、たとえ内部回路に昇圧電圧のリークがあった場合であっても、制御回路はそのまま動作することにより初期化が実行される。   In the present invention, a dedicated extraction terminal is prepared from the boost power supply circuit for the boost voltage for controlling the control circuit (step-down power supply circuit), and the boost voltage (boost power supply line) to the internal circuit is prepared. By dividing the boosted voltage to the control circuit, even if there is a leak of the boosted voltage in the internal circuit, the control circuit operates as it is to perform initialization.

また、この昇圧電源の分離を、半導体集積回路装置の初期化動作時にだけ行うようにすることによって、それぞれの昇圧電圧に用意した安定化容量（平滑容量）を共有化することが可能になり、実装面積の削減を図ることができる。なお、それぞれの昇圧電圧の取り出し端子にダイオードを順方向に設けることで電流の逆流をなくすことができる。   In addition, by performing the separation of the boost power source only during the initialization operation of the semiconductor integrated circuit device, it becomes possible to share the stabilization capacitance (smoothing capacitance) prepared for each boost voltage, The mounting area can be reduced. It should be noted that a reverse current flow can be eliminated by providing a diode in the forward direction for each boosted voltage extraction terminal.

まず、本発明に係る半導体集積回路装置の実施例を説明する前に、従来の半導体集積回路装置およびその問題点を、添付図面（図１〜図３）を参照して詳述する。   First, before describing an embodiment of a semiconductor integrated circuit device according to the present invention, a conventional semiconductor integrated circuit device and its problems will be described in detail with reference to the accompanying drawings (FIGS. 1 to 3).

図１は半導体集積回路装置の一例としてのＤＲＡＭを概略的に示すブロック図であり、主として本発明に関連する従来のＤＲＡＭの一部のみを説明するものである。図１において、参照符号１００は昇圧電源回路、２は降圧電源回路、３０は選択回路（制御回路）、４はコマンド／アドレスデコード回路、４０はコマンド／アドレス端子、５はデータ入出力回路、５０はデータ端子、６はセンスアンプ、そして、７はメモリセルを示している。また、参照符号ＶＤＤは高電位電源電圧（例えば、１．８Ｖ±０．２Ｖ）、ＶＳＳは低電位電源電圧（例えば、０Ｖ）、ＶＰＰは昇圧電圧（昇圧電源回路１００の出力電圧：例えば、３．２〜３．６Ｖ）、ＶＩＩは降圧電圧（降圧電源回路２の出力電圧：例えば、１．６〜１．８Ｖ）、ＢＬはビット線、そして、ＷＬはワード線を示している。   FIG. 1 is a block diagram schematically showing a DRAM as an example of a semiconductor integrated circuit device, and only a part of a conventional DRAM related to the present invention will be mainly described. In FIG. 1, reference numeral 100 is a step-up power supply circuit, 2 is a step-down power supply circuit, 30 is a selection circuit (control circuit), 4 is a command / address decoding circuit, 40 is a command / address terminal, 5 is a data input / output circuit, 50 Is a data terminal, 6 is a sense amplifier, and 7 is a memory cell. Reference sign VDD is a high-potential power supply voltage (for example, 1.8 V ± 0.2 V), VSS is a low-potential power supply voltage (for example, 0 V), and VPP is a boosted voltage (output voltage of the boosted power supply circuit 100: 3 VII to 3.6 V), VII denotes a step-down voltage (output voltage of the step-down power supply circuit 2: 1.6 to 1.8 V, for example), BL denotes a bit line, and WL denotes a word line.

外部からのコマンド／アドレス信号は、コマンド／アドレス端子４０を介してコマンド／アドレスデコード回路４に供給され、選択回路３０を介してアドレス信号に対応したワード線ＷＬを選択すると共に、センスアンプ６を介してアドレス信号に対応したビット線ＢＬを選択して所定のメモリセル７をアクセスする。このアドレス信号に応じてアクセスされたメモリセル７に対する外部からの書き込みデータは、データ端子５０、データ入出力回路５およびライトアンプ（センスアンプ６）を介してメモリセル７に供給され、また、メモリセル７からの読み出しデータは、センスアンプ６、データ入出力回路５およびデータ端子５０を介して外部に出力される。なお、選択回路３０は、上述した通常のワード線選択処理の他、以下に説明するような欠陥の生じているメモリセルに対する冗長処理も行っている。   The command / address signal from the outside is supplied to the command / address decoding circuit 4 via the command / address terminal 40, selects the word line WL corresponding to the address signal via the selection circuit 30, and turns on the sense amplifier 6. Then, the bit line BL corresponding to the address signal is selected to access a predetermined memory cell 7. Write data from the outside to the memory cell 7 accessed according to the address signal is supplied to the memory cell 7 via the data terminal 50, the data input / output circuit 5 and the write amplifier (sense amplifier 6), Data read from the cell 7 is output to the outside through the sense amplifier 6, the data input / output circuit 5 and the data terminal 50. In addition to the normal word line selection process described above, the selection circuit 30 performs a redundancy process for a defective memory cell as described below.

図２は図１のＤＲＡＭにおけるメモリセルの選択回路の一例を概略的に示すブロック回路図である。   FIG. 2 is a block circuit diagram schematically showing an example of a memory cell selection circuit in the DRAM of FIG.

図２に示されるように、選択回路３０は、アドレス信号ＡＤＤが入力されたアドレス信号用のレベル変換回路３１１、活性化信号（コマンド信号：イネーブル信号）ＥＮが入力されたコマンド信号用のレベル変換回路３１２、増幅回路３２１〜３２３、ｐチャネル型ＭＯＳトランジスタ（ｐＭＯＳトランジスタ）３３，３４、および、ｎチャネル型ＭＯＳトランジスタ（ｎＭＯＳトランジスタ）３５，３６を備えている。ここで、レベル変換回路３１１および３１２には、昇圧電圧ＶＰＰおよび降圧電圧ＶＩＩの両方の電圧が印加されている。   As shown in FIG. 2, the selection circuit 30 includes a level conversion circuit 311 for an address signal to which an address signal ADD is input, and a level conversion for a command signal to which an activation signal (command signal: enable signal) EN is input. A circuit 312, amplifier circuits 321 to 323, p-channel MOS transistors (pMOS transistors) 33 and 34, and n-channel MOS transistors (nMOS transistors) 35 and 36 are provided. Here, both the boosted voltage VPP and the step-down voltage VII are applied to the level conversion circuits 311 and 312.

レベル変換回路３１１は、増幅回路３２１を介してトランジスタ３４および３５を制御してアドレス信号ＡＤＤに対応したワード線ＷＬを選択するために使用され、また、レベル変換回路３１２は、増幅回路３２２および３２３を介してそれぞれ対応するトランジスタ３３および３６を制御して選択回路３０を活性化するために使用される。すなわち、増幅回路３２２からの高レベル『Ｈ』の信号によりｎＭＯＳトランジスタ３５がオンすると共に、増幅回路３２３からの低レベル『Ｌ』の信号によりｎＭＯＳトランジスタ３６がオフし、さらに、増幅回路３２１からの低レベル『Ｌ』の信号がトランジスタ３４および３５で反転されてワード線ＷＬが選択（高レベル『Ｈ』）される。   The level conversion circuit 311 is used to select the word line WL corresponding to the address signal ADD by controlling the transistors 34 and 35 via the amplification circuit 321, and the level conversion circuit 312 includes the amplification circuits 322 and 323. Are used to activate the selection circuit 30 by controlling the corresponding transistors 33 and 36 respectively. That is, the nMOS transistor 35 is turned on by a high-level “H” signal from the amplifier circuit 322, the nMOS transistor 36 is turned off by a low-level “L” signal from the amplifier circuit 323, and further from the amplifier circuit 321. The low level “L” signal is inverted by the transistors 34 and 35 to select the word line WL (high level “H”).

図３は図２の選択回路におけるレベル変換回路の一例を示す回路図である。
図３に示されるように、レベル変換回路３１１（３１２）は、複数のｐＭＯＳトランジスタ３１１１〜３１１６および複数のｎＭＯＳトランジスタ３１１７〜３１２２で構成されている。ここで、トランジスタ３１１１、３１１７、３１１５，３１２１および３１１６，３１２２はＣＭＯＳインバータを構成している。なお、参照符号ｎ１１はインバータ３１１１，３１１７の出力ノードを示し、また、ｎ１２はインバータ３１１５，３１２１の入力ノードを示している。 FIG. 3 is a circuit diagram showing an example of the level conversion circuit in the selection circuit of FIG.
As shown in FIG. 3, the level conversion circuit 311 (312) includes a plurality of pMOS transistors 3111 to 3116 and a plurality of nMOS transistors 3117 to 3122. Here, the transistors 3111, 3117, 3115, 3121 and 3116, 3122 constitute a CMOS inverter. Reference numeral n11 indicates an output node of the inverters 3111 and 3117, and n12 indicates an input node of the inverters 3115 and 3121.

図３に示すレベル変換回路３１１において、まず、ｎＭＯＳトランジスタ３１１８は、ｐＭＯＳトランジスタ３１１１２がオンのとき、昇圧電源線（ＶＰＰ）→ノードｎ１２→ノードｎ１１→降圧電源線（ＶＩＩ）という経路で流れる電流を遮断するための役割をしている。また、ｎＭＯＳトランジスタ３１１９およびｐＭＯＳトランジスタ３１１４のゲートに供給されるリセット信号／ｒｓｔは、起動時には低レベル『Ｌ』となり、それ以外では昇圧電圧ＶＰＰのレベルとなる信号であり、起動時の出力信号ｏｕｔの低レベル『Ｌ』出力を保証している。ただし、このリセット信号／ｒｓｔもレベル変換回路を通しているため、降圧電圧ＶＩＩが保証されない場合には、このリセット信号／ｒｓｔも不定となる場合がある。   In the level conversion circuit 311 shown in FIG. 3, first, when the pMOS transistor 31112 is on, the nMOS transistor 3118 receives a current flowing through a path of the boost power supply line (VPP) → node n12 → node n11 → step-down power supply line (VII). It plays the role of blocking. Further, the reset signal / rst supplied to the gates of the nMOS transistor 3119 and the pMOS transistor 3114 is a low level “L” at the time of startup, and is the level of the boost voltage VPP at other times, and the output signal out at the time of startup. The low level “L” output is guaranteed. However, since this reset signal / rst also passes through the level conversion circuit, if the step-down voltage VII is not guaranteed, this reset signal / rst may be undefined.

すなわち、リセット信号／ｒｓｔを生成するレベル変換回路にトランジスタ３１１９，３１１４の無いレベル変換回路を用いた場合、降圧電圧ＶＩＩが不定で昇圧電圧ＶＰＰを上昇させていく時に、出力信号ｏｕｔ（すなわち、リセット信号／ｒｓｔ）が昇圧電圧ＶＰＰ側に張りついている場合が考えられる。通常、ｐＭＯＳトランジスタ３１１２の駆動能力は、トランジスタ３１１３の駆動能力よりも小さくなるように設計され、起動時にこのような出力状態にはならないようにしているが、製造上のパーティクル等によって、トランジスタ３１１３の駆動能力が著しく低下した場合やトランジスタ３１１２，３１１３の駆動能力が逆転している場合も有り得る。   That is, when the level conversion circuit without the transistors 3119 and 3114 is used as the level conversion circuit for generating the reset signal / rst, when the step-down voltage VII is indefinite and the step-up voltage VPP is raised, the output signal out (that is, reset) It is conceivable that the signal / rst) is stuck to the boosted voltage VPP side. Normally, the driving capability of the pMOS transistor 3112 is designed to be smaller than the driving capability of the transistor 3113 and is not set to such an output state at the time of start-up. There may be a case where the driving capability is remarkably lowered or the driving capability of the transistors 3112 and 3113 is reversed.

さらに、チップ内における多数のレベル変換回路において、トランジスタ３１１２の駆動能力がトランジスタ３１１３の駆動能力よりも小さくなるようにされていた場合、多数のワード線ＷＬが選択され、その容量が大きなために昇圧電圧ＶＰＰの立ち上がりが遅くなる場合がある。また、選択されたワード線に本来使用しない低電位電源線（ＶＳＳ）へのリークのある不良ワード線が含まれる場合、昇圧電圧ＶＰＰを立ち上げることができないことにもなってしまう。   Further, in many level conversion circuits in the chip, when the driving capability of the transistor 3112 is made smaller than the driving capability of the transistor 3113, a large number of word lines WL are selected, and the capacity is increased. The rise of the voltage VPP may be delayed. Further, when the selected word line includes a defective word line that leaks to a low potential power supply line (VSS) that is not originally used, the boosted voltage VPP cannot be raised.

これらの選択信号は、降圧電圧ＶＩＩが立ち上がり、レベル変換回路の入力が確定した段階で、基本的に全てのワード線ＷＬがオフとなる。   These selection signals basically turn off all the word lines WL when the step-down voltage VII rises and the input of the level conversion circuit is confirmed.

このように、内部降圧電源の制御に昇圧電源を用いる半導体集積回路装置においては、例えば、製造上の原因によるリークがあった場合、例えば、ＤＲＡＭにおいて、リークの原因となる回路に冗長機能が設けられており、内部回路の起動時のリセットによって切り離すことができる回路であっても、リセットを行うことができずに不良となっていた。   As described above, in a semiconductor integrated circuit device that uses a boost power source for controlling an internal step-down power source, for example, when there is a leak due to a manufacturing cause, a redundancy function is provided in a circuit that causes the leak in, for example, a DRAM. Even in the case of a circuit that can be disconnected by reset at the time of starting up the internal circuit, the reset cannot be performed and the circuit is defective.

以下、本発明に係る半導体集積回路装置の実施例を、添付図面を参照して詳述する。
図４は本発明に係る半導体集積回路装置の要部の構成を概念的に示すブロック図である。図４において、参照符号１は昇圧電源回路、２は降圧電源回路、３は制御回路、そして、４は内部回路を示している。また、参照符号ＶＤＤは高電位電源電圧（例えば、１．８Ｖ±０．２Ｖ）、ＶＳＳは低電位電源電圧（例えば、０Ｖ）、ＶＰＰ１およびＶＰＰ２は昇圧電圧（昇圧電源回路１の出力電圧：例えば、３．２〜３．６Ｖ）、ＶＩＩは降圧電圧（降圧電源回路２の出力電圧：例えば、１．６〜１．８Ｖ）、そして、ＶＧは降圧電源回路２における内部電圧を示している。 Hereinafter, embodiments of a semiconductor integrated circuit device according to the present invention will be described in detail with reference to the accompanying drawings.
FIG. 4 is a block diagram conceptually showing the structure of the main part of the semiconductor integrated circuit device according to the present invention. In FIG. 4, reference numeral 1 is a step-up power supply circuit, 2 is a step-down power supply circuit, 3 is a control circuit, and 4 is an internal circuit. Reference sign VDD is a high potential power supply voltage (for example, 1.8V ± 0.2V), VSS is a low potential power supply voltage (for example, 0V), VPP1 and VPP2 are boosted voltages (output voltage of boosted power supply circuit 1: 3.2 to 3.6 V), VII denotes a step-down voltage (output voltage of the step-down power supply circuit 2: 1.6 to 1.8 V, for example), and VG denotes an internal voltage in the step-down power supply circuit 2.

本発明に係る半導体集積回路装置は、昇圧電圧ＶＰＰ１，ＶＰＰ２を発生する昇圧電源回路１、昇圧電圧ＶＰＰ１により駆動される内部回路８、および、昇圧電圧ＶＰＰ２を受け取って内部回路８を制御する制御回路３を備えている。昇圧電源回路１は、内部回路８に対して昇圧電圧ＶＰＰ１を印加するための第１の出力端子ＯＴ１、および、降圧電源回路２を介して制御回路３に所定の電圧（降圧電圧ＶＩＩ）を印加するための第２の出力端子ＯＴ２を備える。   The semiconductor integrated circuit device according to the present invention includes a boost power supply circuit 1 that generates boosted voltages VPP1 and VPP2, an internal circuit 8 that is driven by the boosted voltage VPP1, and a control circuit that receives the boosted voltage VPP2 and controls the internal circuit 8 3 is provided. The step-up power supply circuit 1 applies a predetermined voltage (step-down voltage VII) to the control circuit 3 via the first output terminal OT1 for applying the step-up voltage VPP1 to the internal circuit 8 and the step-down power supply circuit 2. A second output terminal OT2 is provided.

図４に示されるように、降圧電源回路２は、例えば、差動増幅器（オペアンプ）２１、容量２２、および、ｎＭＯＳトランジスタ２３を備える。差動増幅器２１は、正入力端子に供給された基準電圧Ｖｒに応じた所定の内部電圧（高電位電源電圧ＶＤＤよりも高い電圧）ＶＧを出力し、この内部電圧ＶＧがｎＭＯＳトランジスタ２３のゲートに印加されて、これにより降圧および安定化された降圧電圧（例えば、１．６〜１．８Ｖの範囲における一定の電圧）ＶＩＩが出力される。ここで、容量２２は、差動増幅器２１の出力電圧を平滑化（安定化）するためのものである。   As shown in FIG. 4, the step-down power supply circuit 2 includes, for example, a differential amplifier (op-amp) 21, a capacitor 22, and an nMOS transistor 23. The differential amplifier 21 outputs a predetermined internal voltage (voltage higher than the high potential power supply voltage VDD) VG corresponding to the reference voltage Vr supplied to the positive input terminal, and this internal voltage VG is supplied to the gate of the nMOS transistor 23. As a result, a step-down and stabilized step-down voltage (for example, a constant voltage in the range of 1.6 to 1.8 V) VII is output. Here, the capacitor 22 is for smoothing (stabilizing) the output voltage of the differential amplifier 21.

ここで、本発明係る半導体集積回路装置における昇圧電源回路１は、以下に詳述するように、第１の端子ＯＴ１から出力される昇圧電圧ＶＰＰ１の変動（例えば、内部回路８におけるリークによる電圧降下）に関わらず、第２の端子ＯＵ２から出力される昇圧電圧ＶＰＰ２を所定のレベルで出力する出力電圧制御部を備えている。   Here, the step-up power supply circuit 1 in the semiconductor integrated circuit device according to the present invention, as will be described in detail below, changes in the step-up voltage VPP1 output from the first terminal OT1 (for example, a voltage drop due to leakage in the internal circuit 8). ) Regardless of whether the boosted voltage VPP2 output from the second terminal OU2 is output at a predetermined level.

図５は本発明に係る半導体集積回路装置の一実施例としてのＤＲＡＭを概略的に示すブロック図である。   FIG. 5 is a block diagram schematically showing a DRAM as an embodiment of a semiconductor integrated circuit device according to the present invention.

前述した図１に示す従来のＤＲＡＭとの比較から明らかなように、或いは、図４を参照して説明したように、本実施例のＤＲＡＭにおいて、昇圧電源回路１は、第１の昇圧電圧ＶＰＰ１を出力する第１の出力端子ＯＴ１、および、第２の昇圧電圧ＶＰＰ２を出力する第２の出力端子ＯＴ２を有している。ここで、第１の昇圧電圧ＶＰＰ１は内部回路８に印加され、また、第２の昇圧電圧ＶＰＰ２は選択回路（制御回路）３０に印加される。なお、図５（図１も同様）における選択回路３０は、第１の昇圧電圧ＶＰＰ１が印加される内部回路８の部分、および、第２の昇圧電圧ＶＰＰ２が印加される制御回路（３）の部分の両方の回路部分を含んでいる。また、降圧電源回路２の出力電圧（降圧電圧）ＶＩＩは、内部回路８にも与えられており、例えば、コマンド／アドレスデコード回路４、データ入出力回路５およびセンスアンプ６等にも使用されている。さらに、内部回路８としては、コマンド／アドレスデコード回路４、データ入出力回路５、センスアンプ６およびメモリセル７の他、様々な回路が含まれるのはもちろんである。   As is apparent from the comparison with the conventional DRAM shown in FIG. 1 described above or as described with reference to FIG. 4, in the DRAM of this embodiment, the boosting power supply circuit 1 includes the first boosted voltage VPP1. Is output, and the second output terminal OT2 outputs the second boosted voltage VPP2. Here, the first boosted voltage VPP 1 is applied to the internal circuit 8, and the second boosted voltage VPP 2 is applied to the selection circuit (control circuit) 30. Note that the selection circuit 30 in FIG. 5 (also in FIG. 1) includes a portion of the internal circuit 8 to which the first boosted voltage VPP1 is applied and a control circuit (3) to which the second boosted voltage VPP2 is applied. Includes both circuit parts of the part. Further, the output voltage (step-down voltage) VII of the step-down power supply circuit 2 is also supplied to the internal circuit 8, and is used, for example, in the command / address decoding circuit 4, the data input / output circuit 5, the sense amplifier 6, and the like. Yes. Furthermore, the internal circuit 8 includes various circuits in addition to the command / address decoding circuit 4, the data input / output circuit 5, the sense amplifier 6, and the memory cell 7.

図６は本発明に係る半導体集積回路装置における昇圧電源回路の構成を概念的に示すブロック図である。   FIG. 6 is a block diagram conceptually showing the structure of the boost power supply circuit in the semiconductor integrated circuit device according to the present invention.

図６に示されるように、昇圧電源回路１は、第１の出力端子ＯＴ１に対して直列に接続された第１のスイッチ１１、および、第２の出力端子ＯＴ２に対して直列に接続された第２のスイッチ１２を備える。   As shown in FIG. 6, the boosting power supply circuit 1 is connected in series to the first switch 11 connected in series to the first output terminal OT1 and to the second output terminal OT2. A second switch 12 is provided.

図７は図６の昇圧電源回路の一例を示すブロック図である。
図７に示されるように、昇圧電源回路１は、第１のスイッチ１１、第２のスイッチ１２、遅延回路１３、および、レベル変換回路１４を備える。第１および第２のスイッチ１１，１２は、レベル変換回路１４の出力信号／ＣＮＴ（／ＣＮＴ’）によって制御される。ここで、第１のスイッチ１１に供給される制御信号／ＣＮＴ’は、第２のスイッチ１２に供給される制御信号／ＣＮＴを遅延回路１３で遅延した信号とされている。 FIG. 7 is a block diagram showing an example of the boost power supply circuit of FIG.
As shown in FIG. 7, the boost power supply circuit 1 includes a first switch 11, a second switch 12, a delay circuit 13, and a level conversion circuit 14. The first and second switches 11 and 12 are controlled by the output signal / CNT (/ CNT ′) of the level conversion circuit 14. Here, the control signal / CNT ′ supplied to the first switch 11 is a signal obtained by delaying the control signal / CNT supplied to the second switch 12 by the delay circuit 13.

昇圧電源回路１は、図１を参照して説明した従来の半導体集積回路装置における昇圧電源回路（１００）と同様に、電源電圧（ＶＤＤ）から昇圧された昇圧電圧Ｖｉｐ（ＶＰＰ）を生成する。さらに、この昇圧電圧Ｖｉｐは、第１のスイッチ１１を介して内部回路８用の第１の昇圧電圧ＶＰＰ１として第１の出力端子ＯＴ１から出力されると共に、第２のスイッチ１２を介して制御回路３用の第２の昇圧電圧ＶＰＰ２として第２の出力端子ＯＴ２から出力される。そして、第１および第２のスイッチ１１，１２は、レベル変換回路１４の出力信号／ＣＮＴ（／ＣＮＴ’）によって制御される。   The boost power supply circuit 1 generates a boosted voltage Vip (VPP) boosted from the power supply voltage (VDD), similarly to the boost power supply circuit (100) in the conventional semiconductor integrated circuit device described with reference to FIG. Further, the boosted voltage Vip is output from the first output terminal OT1 as the first boosted voltage VPP1 for the internal circuit 8 through the first switch 11, and also the control circuit through the second switch 12. 3 is output from the second output terminal OT2 as the second boosted voltage VPP2 for 3. The first and second switches 11 and 12 are controlled by the output signal / CNT (/ CNT ′) of the level conversion circuit 14.

すなわち、第２のスイッチ１２は、レベル変換回路１４からの制御信号／ＣＮＴにより制御され、また、第１のスイッチ１１は、第２のスイッチ１２に供給される制御信号／ＣＮＴを遅延回路１３で遅延した制御信号／ＣＮＴ’により制御される。   That is, the second switch 12 is controlled by the control signal / CNT from the level conversion circuit 14, and the first switch 11 receives the control signal / CNT supplied to the second switch 12 by the delay circuit 13. It is controlled by the delayed control signal / CNT ′.

図８は図７の昇圧電源回路における遅延回路の一例を示す図である。図８に示されるように、遅延回路８は、縦列接続された複数（偶数個）のインバータ１３１，１３２で構成され、第１のスイッチ１１に対して、第２のスイッチ１２に供給される制御信号／ＣＮＴをインバータ１３１，１３２で遅延した制御信号／ＣＮＴ’を供給するようになっている。   FIG. 8 is a diagram showing an example of a delay circuit in the boost power supply circuit of FIG. As shown in FIG. 8, the delay circuit 8 includes a plurality (even number) of inverters 131 and 132 connected in cascade, and is supplied to the second switch 12 with respect to the first switch 11. A control signal / CNT ′ obtained by delaying the signal / CNT by the inverters 131 and 132 is supplied.

これにより、半導体集積回路装置（例えば、ＤＲＡＭ）の電源オン時において、第１のスイッチ１１がオンして内部回路８へ昇圧電圧ＶＰＰ１が印加されるよりも前のタイミングで、第２のスイッチ１２をオンして昇圧電圧ＶＰＰ２を制御回路３（降圧電源回路２）へ供給することになり、たとえリークの原因となる回路（例えば、リークが生じる欠陥ワード線）が内部回路８に存在する場合でも、制御回路３を正常に動作させて上記リークの原因となる回路の切り離し処理等（例えば、欠陥ワード線を遮断して予備のワード線に切り替える冗長処理）を行うことができる。   Thereby, when the power of the semiconductor integrated circuit device (for example, DRAM) is turned on, the second switch 12 is turned on at a timing before the first switch 11 is turned on and the boosted voltage VPP1 is applied to the internal circuit 8. Is turned on to supply the boosted voltage VPP2 to the control circuit 3 (step-down power supply circuit 2), even if a circuit that causes a leak (for example, a defective word line that causes a leak) exists in the internal circuit 8. Then, the control circuit 3 can be normally operated to perform the process of disconnecting the circuit causing the leak (for example, the redundant process of cutting off the defective word line and switching to the spare word line).

ここで、第１の昇圧電圧ＶＰＰ１および第２の昇圧電圧ＶＰＰ２は、例えば、同電位の電圧であり、上記半導体集積回路装置の起動時の処理が終了した後は、第１の出力端子ＯＴ１と第２の出力端子ＯＴ２を短絡して昇圧電圧の電源容量（平滑容量）を大きくすることができる。   Here, the first boosted voltage VPP1 and the second boosted voltage VPP2 are, for example, voltages of the same potential, and after the start-up process of the semiconductor integrated circuit device is completed, the first boosted voltage VPP1 and the second boosted voltage VPP2 The power supply capacity (smoothing capacity) of the boosted voltage can be increased by short-circuiting the second output terminal OT2.

図９は本発明に係る半導体集積回路装置における昇圧電源回路の要部構成の第１実施例を示す回路図であり、図１０は図９の昇圧電源回路の動作を説明するための概略的な波形図である。なお、以下では、昇圧電源回路１が２倍の高電位電源電圧（ＶＤＤ×２）を発生する場合を説明するが、例えば、３倍（ＶＤＤ×３）等の他の電圧を発生する場合においても、本発明は同様に適用することができるのはいうまでもない。   FIG. 9 is a circuit diagram showing a first embodiment of the main configuration of the boost power supply circuit in the semiconductor integrated circuit device according to the present invention. FIG. 10 is a schematic diagram for explaining the operation of the boost power supply circuit of FIG. It is a waveform diagram. In the following description, a case where the boost power supply circuit 1 generates a double high potential power supply voltage (VDD × 2) will be described. However, for example, when another voltage such as triple (VDD × 3) is generated. However, it goes without saying that the present invention can be similarly applied.

図９に示されるように、本第１実施例の昇圧電源回路１は、スイッチ１０，１１，１２、および、容量１５，１６，１７を備えている。図９および図１０に示されるように、まず、スイッチ１０がオンでスイッチ１１および１２がオフの状態で、プリチャージ電位（Ｖｐｒ：例えば、ＶＤＤに等しい）からノードｎ１のプリチャージを行う。このとき、ポンプ電圧ＶｍｐはＶＳＳ（０Ｖ）である。   As shown in FIG. 9, the boost power supply circuit 1 of the first embodiment includes switches 10, 11, 12 and capacitors 15, 16, 17. As shown in FIGS. 9 and 10, first, the node n1 is precharged from a precharge potential (Vpr: equal to VDD, for example) with the switch 10 on and the switches 11 and 12 off. At this time, the pump voltage Vmp is VSS (0 V).

次に、スイッチ１０をオフとしポンプ電圧Ｖｍｐの電位を叩き上げることでノードｎ１の電位はＶＤＤ（例えば、ＶＤＤ×２）に上昇する。さらに、スイッチ（第２のスイッチ）１２が制御信号／ＣＮＴによりオンし、次いで、スイッチ（第１のスイッチ）１１が遅延された制御信号／ＣＮＴ’によりオンする。これにより、第２のスイッチ１２を経由する第２の昇圧電圧ＶＰＰ２は、第１のスイッチ１１を経由する第１の昇圧電圧ＶＰＰ１よりも早いタイミングで降圧電源回路２に印加され、さらに、降圧電源回路２の出力電圧（降圧電圧）ＶＩＩが制御回路３（選択回路３０）に印加されて制御回路３が動作する。   Next, the switch 10 is turned off and the potential of the pump voltage Vmp is boosted, whereby the potential of the node n1 rises to VDD (for example, VDD × 2). Further, the switch (second switch) 12 is turned on by the control signal / CNT, and then the switch (first switch) 11 is turned on by the delayed control signal / CNT '. As a result, the second boosted voltage VPP2 that passes through the second switch 12 is applied to the step-down power supply circuit 2 at a timing earlier than the first boosted voltage VPP1 that passes through the first switch 11, and further, the step-down power supply The output voltage (step-down voltage) VII of the circuit 2 is applied to the control circuit 3 (selection circuit 30), and the control circuit 3 operates.

これにより、例えば、図３に示したレベル変換回路においても、まず、降圧電圧ＶＩＩが立ち上がってレベル変換回路の入力が確定し、全てのワード線ＷＬがオフとなるため、例えば、ＤＲＡＭにおける欠陥部分（製造上の原因によりリークが生じる部分）の冗長処理を起動時に正しく行うことができる。すなわち、例えば、内部降圧電源の制御に昇圧電源を用いる半導体集積回路装置において、チップ内部の昇圧電圧を用いている回路に製造上の原因によるリークがあった場合でも、制御回路に対しては正しい電圧を印加して通常の制御動作を行わせることが可能になる。   Thereby, for example, also in the level conversion circuit shown in FIG. 3, first, the step-down voltage VII rises, the input of the level conversion circuit is determined, and all the word lines WL are turned off. Redundancy processing (a portion where leakage occurs due to manufacturing reasons) can be correctly performed at startup. That is, for example, in a semiconductor integrated circuit device that uses a boosted power supply for controlling an internal step-down power supply, even if there is a leak due to a manufacturing cause in a circuit using the boosted voltage inside the chip, it is correct for the control circuit. A normal control operation can be performed by applying a voltage.

なお、前述したように、第１の昇圧電圧ＶＰＰ１（降圧電源回路２に印加される昇圧電圧）および第２の昇圧電圧ＶＰＰ２（内部回路８に印加される昇圧電圧）は、例えば、同電位の電圧であり、半導体集積回路装置の起動時の処理が終了した後は、第１の出力端子ＯＴ１と第２の出力端子ＯＴ２を短絡して昇圧電圧の電源容量を大きくするようになっている。   As described above, the first boosted voltage VPP1 (the boosted voltage applied to the step-down power supply circuit 2) and the second boosted voltage VPP2 (the boosted voltage applied to the internal circuit 8) have, for example, the same potential. After the processing at the time of starting the semiconductor integrated circuit device is completed, the first output terminal OT1 and the second output terminal OT2 are short-circuited to increase the power supply capacity of the boosted voltage.

図１１は本発明に係る半導体集積回路装置における昇圧電源回路の要部構成の第２実施例を示す回路図である。   FIG. 11 is a circuit diagram showing a second embodiment of the main configuration of the boost power supply circuit in the semiconductor integrated circuit device according to the present invention.

図１１から明らかなように、本第２実施例の半導体集積回路装置における昇圧電源回路では、第１のスイッチ１１と直列に第１のダイオード１８が順方向に設けられ、且つ、第２のスイッチ１２と直列に第２のダイオード１９が順方向に設けられている。これにより、例えば、半導体集積回路装置の起動時の処理が終了した後に第１の出力端子ＯＴ１と第２の出力端子ＯＴ２を短絡した場合でも、電流の逆流を防止して昇圧電圧ＶＰＰ（ＶＰＰ１，ＶＰＰ２）を効率的に発生するようになっている。   As is apparent from FIG. 11, in the boost power supply circuit in the semiconductor integrated circuit device according to the second embodiment, the first diode 18 is provided in the forward direction in series with the first switch 11, and the second switch A second diode 19 is provided in series in the forward direction. Thereby, for example, even when the first output terminal OT1 and the second output terminal OT2 are short-circuited after the processing at the time of starting the semiconductor integrated circuit device is completed, the backflow of current is prevented and the boosted voltage VPP (VPP1, VPP1, VPP2) is generated efficiently.

図１２は本発明に係る半導体集積回路装置における昇圧電源回路の要部構成の第３実施例を示す回路図である。   FIG. 12 is a circuit diagram showing a third embodiment of the main configuration of the boost power supply circuit in the semiconductor integrated circuit device according to the present invention.

図１２と図１１との比較から明らかなように、本第３実施例の半導体集積回路装置における昇圧電源回路では、第２のスイッチ１２に対してのみ第２のダイオード１９を設けるようになっている。なお、第１のスイッチ１１に対してのみ第１のダイオード１８を設けることもできる。   As is clear from the comparison between FIG. 12 and FIG. 11, in the step-up power supply circuit in the semiconductor integrated circuit device of the third embodiment, the second diode 19 is provided only for the second switch 12. Yes. Note that the first diode 18 may be provided only for the first switch 11.

図１３は本発明に係る半導体集積回路装置における昇圧電源回路の要部構成の第４実施例を示す回路図である。   FIG. 13 is a circuit diagram showing a fourth embodiment of the main configuration of the boost power supply circuit in the semiconductor integrated circuit device according to the present invention.

図１３に示されるように、本第４実施例の半導体集積回路装置における昇圧電源回路では、交互に動作する２組の昇圧回路部分（スイッチ１０１，１１１，１１２および容量１５１と、スイッチ１０２，１１２，１２２および容量１５２との２組の昇圧回路部分）を設け、効率的に昇圧動作を行わせるようになっている。   As shown in FIG. 13, in the step-up power supply circuit in the semiconductor integrated circuit device of the fourth embodiment, two sets of step-up circuit portions that operate alternately (switches 101, 111, 112 and capacitor 151, and switches 102, 112 , 122 and a capacitor 152) are provided to efficiently perform a boosting operation.

ここで、第１の昇圧回路部分のスイッチ１０１，１１１，１１２と、第２の昇圧回路部分のスイッチ１０２，１１２，１２２とは互いに１８０度の位相で動作するようになっている。さらに、各第１のスイッチ１１１および１１２を制御する制御信号／ＣＮＴ１’および／ＣＮＴ２’は、それぞれ各第２のスイッチ１２１および１２２を制御する制御信号／ＣＮＴ１および／ＣＮＴ２を遅延した信号となっている。また、プリチャージ電圧Ｖｐｒ１，Ｖｐｒ２およびポンプ電圧Ｖｍｐ１，Ｖｍｐ２はそれぞれ同電位の電圧とされている。この昇圧電源回路は、様々な構成を適用することができる。   Here, the switches 101, 111, and 112 in the first booster circuit portion and the switches 102, 112, and 122 in the second booster circuit portion operate with a phase of 180 degrees. Further, the control signals / CNT1 ′ and / CNT2 ′ for controlling the first switches 111 and 112 are signals obtained by delaying the control signals / CNT1 and / CNT2 for controlling the second switches 121 and 122, respectively. Yes. The precharge voltages Vpr1 and Vpr2 and the pump voltages Vmp1 and Vmp2 are set to the same potential. Various configurations can be applied to the boost power supply circuit.

すなわち、上述した本実施例に係る半導体集積回路装置における昇圧電源回路、降圧電源回路、制御回路および内部回路は、様々な構成を適用することができるのはいうまでもない。   That is, it goes without saying that various configurations can be applied to the step-up power supply circuit, the step-down power supply circuit, the control circuit, and the internal circuit in the semiconductor integrated circuit device according to this embodiment described above.

このように、本発明に係る半導体集積回路装置によれば、チップ内部に昇圧電圧からのリークがあった場合でも、正しく初期化動作を行うことができる。また、起動後に２つの昇圧電圧を電気的にショートさせることで、容量（平滑容量）を兼用することができ、キャパシタの面積を削減することができる。さらに、昇圧電圧の取り出し端子にダイオードを設けることで、電流の逆流を防ぎ効率よく昇圧電圧を取り出すことができる。   Thus, according to the semiconductor integrated circuit device of the present invention, the initialization operation can be performed correctly even when there is a leak from the boosted voltage inside the chip. In addition, by electrically shorting the two boosted voltages after startup, the capacitance (smoothing capacitance) can be shared, and the area of the capacitor can be reduced. Furthermore, by providing a diode at the boost voltage extraction terminal, it is possible to prevent the backflow of current and efficiently extract the boost voltage.

半導体集積回路装置の一例としてのＤＲＡＭを概略的に示すブロック図である。1 is a block diagram schematically showing a DRAM as an example of a semiconductor integrated circuit device. 図１のＤＲＡＭにおけるメモリセルの選択回路の一例を概略的に示すブロック回路図である。FIG. 2 is a block circuit diagram schematically showing an example of a memory cell selection circuit in the DRAM of FIG. 1. 図２の選択回路におけるレベル変換回路の一例を示す回路図である。FIG. 3 is a circuit diagram illustrating an example of a level conversion circuit in the selection circuit of FIG. 2. 本発明に係る半導体集積回路装置の要部の構成を概念的に示すブロック図である。1 is a block diagram conceptually showing the structure of a main part of a semiconductor integrated circuit device according to the present invention. 本発明に係る半導体集積回路装置の一実施例としてのＤＲＡＭを概略的に示すブロック図である。1 is a block diagram schematically showing a DRAM as an embodiment of a semiconductor integrated circuit device according to the present invention. FIG. 本発明に係る半導体集積回路装置における昇圧電源回路の構成を概念的に示すブロック図である。1 is a block diagram conceptually showing the structure of a boost power supply circuit in a semiconductor integrated circuit device according to the present invention. 図６の昇圧電源回路の一例を示すブロック図である。FIG. 7 is a block diagram illustrating an example of a boost power supply circuit in FIG. 6. 図７の昇圧電源回路における遅延回路の一例を示す図である。FIG. 8 is a diagram illustrating an example of a delay circuit in the boost power supply circuit of FIG. 7. 本発明に係る半導体集積回路装置における昇圧電源回路の要部構成の第１実施例を示す回路図である。1 is a circuit diagram showing a first embodiment of a configuration of main parts of a boost power supply circuit in a semiconductor integrated circuit device according to the present invention; FIG. 図９の昇圧電源回路の動作を説明するための概略的な波形図である。FIG. 10 is a schematic waveform diagram for explaining the operation of the boost power supply circuit of FIG. 9. 本発明に係る半導体集積回路装置における昇圧電源回路の要部構成の第２実施例を示す回路図である。FIG. 6 is a circuit diagram showing a second embodiment of the main configuration of the boost power supply circuit in the semiconductor integrated circuit device according to the present invention. 本発明に係る半導体集積回路装置における昇圧電源回路の要部構成の第３実施例を示す回路図である。そして、FIG. 11 is a circuit diagram showing a third embodiment of the main configuration of the boost power supply circuit in the semiconductor integrated circuit device according to the present invention. And 本発明に係る半導体集積回路装置における昇圧電源回路の要部構成の第４実施例を示す回路図である。FIG. 10 is a circuit diagram showing a fourth embodiment of the main configuration of the boost power supply circuit in the semiconductor integrated circuit device according to the present invention.

Claims (5)

昇圧電圧を発生する昇圧電源回路、
該昇圧電圧により駆動される内部回路、
前記昇圧電圧を降圧し、降圧電圧を出力する降圧電源回路、および、
前記降圧電圧を受け取って前記内部回路を制御する制御回路を有し、
前記昇圧電源回路は、前記内部回路用の第１の出力端子と、前記降圧電源回路用の第２の出力端子とを備え、
前記昇圧電源回路は、
前記第１の出力端子に対して直列に接続された第１のスイッチと、
前記第２の出力端子に対して直列に接続された第２のスイッチと、
前記第１のスイッチをオンするタイミングを、前記第２のスイッチをオンするタイミングよりも遅らせる遅延回路と、
を備えることを特徴とする半導体集積回路装置。A boost power supply circuit for generating a boost voltage;
An internal circuit driven by the boosted voltage;
A step-down power supply circuit that steps down the step-up voltage and outputs a step-down voltage; and
A control circuit that receives the step-down voltage and controls the internal circuit;
The step-up power supply circuit includes a first output terminal for the internal circuit and a second output terminal for the step-down power supply circuit ,
The boost power supply circuit includes:
A first switch connected in series to the first output terminal;
A second switch connected in series to the second output terminal;
A delay circuit that delays the timing of turning on the first switch from the timing of turning on the second switch;
The semiconductor integrated circuit device, characterized in that it comprises a. 請求項１に記載の半導体集積回路装置において、
前記昇圧電源回路は、前記第１の端子から出力される前記昇圧電圧の変動に関わらず、前記第２の端子から出力される前記昇圧電圧を所定のレベルで出力する出力電圧制御部を備えること
を特徴とする半導体集積回路装置。The semiconductor integrated circuit device according to claim 1,
The boost power supply circuit includes an output voltage control unit that outputs the boosted voltage output from the second terminal at a predetermined level regardless of fluctuations in the boosted voltage output from the first terminal. A semiconductor integrated circuit device. 請求項２に記載の半導体集積回路装置において、
前記出力電圧制御部は、さらに、前記第１のスイッチの後段に設けられた平滑用の第１の容量と、前記第２のスイッチの後段に設けられた平滑用の第２の容量とを備えること
を特徴とする半導体集積回路装置。The semiconductor integrated circuit device according to claim 2 ,
The output voltage control unit further includes a first capacitor for smoothing provided after the first switch and a second capacitor for smoothing provided after the second switch. A semiconductor integrated circuit device. 請求項２に記載の半導体集積回路装置において、
前記出力電圧制御部は、さらに、前記第１のスイッチと直列に設けられた順方向の第１のダイオードと、前記第２のスイッチと直列に設けられた順方向の第２のダイオードとのうちの少なくとも一方を備えること
を特徴とする半導体集積回路装置。The semiconductor integrated circuit device according to claim 2 ,
The output voltage control unit further includes a forward first diode provided in series with the first switch and a forward second diode provided in series with the second switch. A semiconductor integrated circuit device comprising: at least one of the above. 請求項１に記載の半導体集積回路装置において、
前記第１および第２の出力端子は、該半導体集積回路装置の起動時にのみ分離され、一旦起動した後は電気的に短絡されること
を特徴とする半導体集積回路装置。The semiconductor integrated circuit device according to claim 1,
The first and second output terminals are separated only when the semiconductor integrated circuit device is activated, and are electrically short-circuited after being activated.
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US20060273848A1 (en) 2006-12-07
CN1695291A (en) 2005-11-09
US20050201186A1 (en) 2005-09-15
DE60335147D1 (en) 2011-01-05
CN100423421C (en) 2008-10-01
JPWO2004102780A1 (en) 2006-07-13
EP2256910A1 (en) 2010-12-01
US7113027B2 (en) 2006-09-26
WO2004102780A1 (en) 2004-11-25
EP1624558A1 (en) 2006-02-08
EP1624558B1 (en) 2010-11-24
EP2256910B1 (en) 2012-12-05
EP1624558A4 (en) 2008-12-17
US7508252B2 (en) 2009-03-24

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