JP2012174282A - Nonvolatile storage device, integrated circuit device, and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile storage device capable of surely latching read data by a differential latch circuit even if there are manufacturing variations and the like, and to provide an integrated circuit device, an electronic apparatus and the like.SOLUTION: In a nonvolatile semiconductor storage device 100 which includes a first nonvolatile memory cell MC1, a word line drive circuit 130 for supplying a selection voltage to a word line WL for selecting the first nonvolatile memory cell MC1, a reference current generation circuit 110 for generating a reference current when the selection voltage has been supplied to the word line WL, and a differential latch circuit 120 for latching data according to a difference between the current passing through the first nonvolatile memory cell MC1 and the reference current when the selection voltage has been supplied to the word line WL, the word line drive circuit 130 drives the word line WL so that a time in which the word line WL is shifted from a selection state to a non-selection state becomes longer than a time in which the word line WL is shifted from the non-selection state to the selection state.

Description

  The present invention relates to a nonvolatile memory device, an integrated circuit device, and an electronic device, and more particularly to a nonvolatile memory device, an integrated circuit device, an electronic device, and the like including a differential latch circuit.

  Generally, a storage device such as a nonvolatile semiconductor storage device including a memory cell array composed of nonvolatile memory cells is equipped with a redundant circuit in order to improve the yield. The redundant circuit replaces defective memory cells or the like in the memory cell array with redundant memory cells or the like in the redundant memory cell array.

  FIG. 15 schematically shows a configuration example of a memory cell array of a nonvolatile semiconductor memory device as a memory device.

  The memory cell array 10 includes a normal memory cell array 20, a redundant memory cell array 30, and a fuse memory cell array 40, and each memory cell array is composed of nonvolatile memory cells. In the memory cell array 10, a plurality of word lines WL extending in the row direction and a plurality of bit lines BL extending in the column direction are arranged. FIG. 15 shows only one word line and one bit line.

  The nonvolatile semiconductor memory device is inspected for defective memory cells among a plurality of nonvolatile memory cells constituting the normal memory cell array 20 at the time of product shipment. When a defective memory cell MCE is detected in the regular memory cell array 20, defect information such as address information of the defective memory cell MCE is stored in a predetermined nonvolatile memory cell in the fuse memory cell array 40. When a non-volatile memory cell in a predetermined area including the defective memory cell MCE is accessed, the non-volatile memory cell in the predetermined area in the redundant memory cell array 30 is stored on the basis of the defect information stored in the fuse memory cell array 40. Controlled to access.

  The fuse memory cell array 40 stores manufacturing information such as the inspection date and time and the manufacturing lot number in addition to the defect information. Information read from the fuse memory cell array 40 as necessary is used for purposes such as failure analysis. In the fuse memory cell array 40, adjustment data and the like of other macro circuits such as analog circuits are stored as trimming data and read out when the power is turned on.

  Various nonvolatile semiconductor memory devices having such a memory cell array have been proposed. For example, Patent Document 1 discloses a nonvolatile semiconductor memory device in which redundant memory is provided with two floating gate transistors, and redundant information is read out by a redundant memory circuit reading circuit configured by a differential latch circuit. ing.

JP 2002-358794 A

  The nonvolatile semiconductor memory device disclosed in Patent Document 1 latches read data by a differential latch circuit using a difference between threshold voltages of two floating gate transistors. Therefore, when the difference between the threshold voltages of the two transistors becomes small, there is a problem that erroneous data is latched due to switching noise, manufacturing variation in the logic threshold level of the differential latch circuit, or the like.

  The present invention has been made in view of the above technical problems. According to some aspects of the present invention, a nonvolatile memory device, an integrated circuit device, an electronic device, and the like that can reliably read data by a differential latch circuit even when a current difference to be compared is small. Can be provided.

  (1) According to a first aspect of the present invention, a nonvolatile memory device supplies a selection voltage to a first nonvolatile memory cell and a word line for selecting the first nonvolatile memory cell. A driving circuit; a reference current generating circuit that generates a reference current when the selection voltage is supplied to the word line; and a current that flows through the first nonvolatile memory cell when the selection voltage is supplied to the word line. And a differential latch circuit that latches data according to a difference between the reference line and the reference current, and the word line driving circuit has a time during which the word line transitions from a selected state to a non-selected state. The word line is driven so as to be longer than the time for transition from the non-selected state to the selected state.

  In this aspect, in the nonvolatile memory device including the differential latch circuit, the time for the word line driving circuit to transition from the selected state of the word line to the non-selected state is longer than the time to transition from the non-selected state to the selected state. Thus, the word line is driven. By doing so, the influence of switching noise can be reduced, and a situation in which the differential latch circuit latches erroneous data can be avoided.

  (2) In the nonvolatile memory device according to the second aspect of the present invention, in the first aspect, the word line driving circuit is configured such that when the word line transitions from the selected state to the non-selected state, The word line is driven so that a period during which a current flows through one of the nonvolatile memory cell and the reference current generation circuit is equal to or longer than a response period of the differential latch circuit.

  In this aspect, when the word line transitions from the selected state to the non-selected state, the period during which a current flows through one of the first nonvolatile memory cell and the reference current generating circuit is the response period of the differential latch circuit. The word line is driven to achieve the above. In this way, the state of the differential latch circuit is determined and can be operated reliably. For this reason, even when there is a small difference between the current flowing through the first nonvolatile memory cell and the reference current and there is a manufacturing variation in the logic threshold level of the differential latch circuit, the differential latch circuit latches erroneous data. It will be possible to avoid.

  (3) In the nonvolatile memory device according to the third aspect of the present invention, in the second aspect, the word line drive circuit causes the word line to transition from the selected state to the non-selected state only during a read operation. Then, the word line is driven so that a period during which a current flows through one of the first nonvolatile memory cell and the reference current generating circuit is equal to or longer than the response period.

  According to this aspect, only during the read operation, when the word line is changed from the selected state to the non-selected state, the period of the state in which a current flows in one of the first nonvolatile memory cell and the reference current generation circuit is different. The word line is driven so as to be longer than the response period of the dynamic latch circuit. By doing so, it is possible to shorten the transition time from the selected state of the word line to the non-selected state at the time of the operation other than at the time of the read operation. Therefore, an increase in writing time other than reading can be suppressed, and an increase in reading time can be minimized.

  (4) In the nonvolatile memory device according to the fourth aspect of the present invention, in the third aspect, the word line driving circuit includes a p-type first driving in which the word line is electrically connected to a drain. A transistor, an n-type second driving transistor whose word line is electrically connected to the drain, a drain of the second driving transistor is electrically connected to the drain, and a ground voltage is supplied to the source an n-type third drive transistor, the third drive transistor being gated by a given drive capability switching signal.

  According to this aspect, with a very simple configuration, non-volatile that reliably latches read data by the differential latch circuit while suppressing an increase in writing time other than reading and minimizing an increase in reading time A storage device can be provided.

  (5) In the nonvolatile memory device according to the fifth aspect of the present invention, in the third aspect, the word line driving circuit includes a p-type first driving in which the word line is electrically connected to a drain. A transistor, an n-type second driving transistor whose word line is electrically connected to the drain, a drain of the second driving transistor is electrically connected to the drain, and a ground voltage is supplied to the source an n-type third driving transistor; and a resistor element having one end electrically connected to the drain of the third driving transistor and the other end supplied with the ground voltage. The third driving transistor includes: , Gated by a given drive capability switching signal.

  According to this aspect, with a very simple configuration, non-volatile that reliably latches read data by the differential latch circuit while suppressing an increase in writing time other than reading and minimizing an increase in reading time A storage device can be provided.

  (6) In the nonvolatile memory device according to the sixth aspect of the present invention, in the fifth aspect, the resistance element is formed of a metal oxide semiconductor transistor.

  According to this aspect, with a very simple configuration, non-volatile that reliably latches read data by the differential latch circuit while suppressing an increase in writing time other than reading and minimizing an increase in reading time A storage device can be provided.

  (7) In the nonvolatile memory device according to the seventh aspect of the present invention, in any one of the first aspect to the sixth aspect, the reference current generation circuit is a threshold voltage of the first nonvolatile memory cell. 2 is a second nonvolatile memory cell having a different threshold voltage.

  According to this aspect, it is possible to provide a non-volatile memory device that has a very simple configuration and can reliably latch read data by a differential latch circuit even if a current difference to be compared is small. Become.

  (8) In the nonvolatile memory device according to the eighth aspect of the present invention, in any one of the first to sixth aspects, the reference current generation circuit has a threshold voltage of the first nonvolatile memory cell. And a metal oxide semiconductor transistor having a different threshold voltage.

  According to this aspect, it is possible to provide a non-volatile memory device that has a very simple configuration and can reliably latch read data by a differential latch circuit even if a current difference to be compared is small. Become.

  (9) According to a ninth aspect of the present invention, there is provided an integrated circuit device comprising: a non-volatile memory device according to any one of the above; and a processing device controlled based on data read from the non-volatile memory device. Including.

  According to this aspect, it is possible to provide a highly reliable integrated circuit device that can accurately read data without being affected by switching noise or a shift in the logic threshold level of the differential latch circuit. Become.

  (10) In a tenth aspect of the present invention, the electronic device includes any one of the nonvolatile memory devices described above.

  According to this aspect, it is possible to provide a highly reliable electronic device including the nonvolatile memory device that can reliably latch read data by the differential latch circuit even if the current difference to be compared is small. It becomes like this.

  (11) In an eleventh aspect of the present invention, an electronic device includes the integrated circuit device described above.

  According to this aspect, it is possible to provide a highly reliable electronic device including an integrated circuit device that can accurately read data without being affected by switching noise or a shift in the logic threshold level of the differential latch circuit. Will be able to.

1 is a block diagram of a configuration example of a nonvolatile semiconductor memory device according to a first embodiment. FIG. 2 is a circuit diagram of a configuration example of the nonvolatile semiconductor memory device in FIG. 1. FIG. 3 is an explanatory diagram of an operation example of the nonvolatile semiconductor memory device having the configuration of FIG. 2. FIG. 3 is a first operation explanatory diagram when erroneous data is latched in the configuration of FIG. 2. FIG. 6 is a second operation explanatory diagram when latching erroneous data in the configuration of FIG. 2. Explanatory drawing of the example of control of the word line by the word line drive circuit in 1st Embodiment. FIG. 7 is an explanatory diagram of operations of the first nonvolatile memory cell and the second nonvolatile memory cell when the word line shown in FIG. 6 is controlled. The circuit diagram of the example of composition of the nonvolatile semiconductor memory device in a 2nd embodiment. The circuit diagram of the example of composition of the nonvolatile semiconductor memory device in a 3rd embodiment. The circuit diagram of the example of composition of the nonvolatile semiconductor memory device in a 4th embodiment. FIG. 10 is a circuit diagram of a configuration example of a nonvolatile semiconductor memory device according to a fifth embodiment. 1 is a block diagram of a configuration example of a microcomputer according to the present invention. FIG. 11 is a block diagram illustrating a configuration example of an electronic device according to the invention. FIG. 14A is a perspective view of a configuration example of a mobile personal computer. FIG. 14B is a perspective view of a structural example of a mobile phone. The figure which shows typically the structural example of the memory cell array of the non-volatile semiconductor memory device as a memory | storage device.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. In addition, all of the configurations described below are not necessarily indispensable configuration requirements for solving the problems of the present invention.

[First Embodiment]
FIG. 1 is a block diagram showing a configuration example of the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

  The nonvolatile semiconductor memory device (nonvolatile memory device in a broad sense) 100 according to the first embodiment includes a first nonvolatile memory cell MC1, a reference current generation circuit 110, and a differential latch circuit 120. Yes. In addition, the nonvolatile semiconductor memory device 100 includes a word line WL, a word line driving circuit 130, and an output buffer 140. Although only one word line WL is shown in FIG. 1, the nonvolatile semiconductor memory device 100 includes a plurality of word lines, and a nonvolatile memory cell is connected to each word line.

  The first nonvolatile memory cell MC1 is a floating gate type memory cell, but may be another nonvolatile memory cell such as a MONOS (Metal Oxide Nitride Oxide Semiconductor) type memory cell. The first nonvolatile memory cell MC1 is composed of a memory cell transistor, the word line WL is electrically connected to the gate of the memory cell transistor, and the ground voltage VSS is supplied to the source. The drain of this memory cell transistor is connected to the differential latch circuit 120. When the selection voltage VWL is supplied to the word line WL, a read current flows through the first memory cell MC1.

  The reference current generation circuit 110 is electrically connected to the word line WL, and generates a reference current when a selection voltage is supplied to the word line WL. At this time, the reference current generation circuit 110 is connected to a predetermined node of the differential latch circuit 120, and draws the reference current from the node to the ground power supply.

  The differential latch circuit 120 latches data according to the difference between the current flowing through the first nonvolatile memory cell MC1 and the reference current when a selection voltage is supplied to the word line WL. The data latched by the differential latch circuit 120 is buffered by the output buffer 140 and output as read data.

  The word line driving circuit 130 supplies a selection voltage to the word line WL for selecting the first nonvolatile memory cell MC1. The word line driving circuit 130 is supplied with a selection voltage VWL generated by a power supply circuit (not shown) and a word line selection signal WLsel. When the word line selection signal WLsel becomes active, the word line WL is selected, and the word line driving circuit 130 supplies the selection voltage VWL to the word line WL. When the word line selection signal WLsel becomes inactive, the word line WL is not selected, and the word line driving circuit 130 supplies, for example, the ground voltage VSS to the word line WL.

  At this time, the word line driving circuit 130 sets the word line WL to the word line WL so that the time for the word line WL to transition from the selected state to the unselected state is longer than the time for the word line WL to transition from the unselected state to the selected state. Supply selection voltage. By so doing, the influence of switching noise when the word line WL transitions from the selected state to the unselected state can be reduced, and the situation where the differential latch circuit 120 latches erroneous data can be avoided. become.

  FIG. 2 shows a circuit diagram of a configuration example of the nonvolatile semiconductor memory device 100 of FIG. In FIG. 2, the same parts as those in FIG.

  In FIG. 2, the reference current generation circuit 110 is configured by a second nonvolatile memory cell MC2 having the same structure as that of the first nonvolatile memory cell MC1. The second nonvolatile memory cell MC2 is composed of a memory cell transistor, the word line WL is electrically connected to the gate of the memory cell transistor, and the ground voltage VSS is supplied to the source. The drain of this memory cell transistor is connected to the differential latch circuit 120. When the selection voltage VWL is supplied to the word line WL, a read current flows as a reference current in the second memory cell MC2.

  The second nonvolatile memory cell MC2 has a threshold voltage different from the threshold voltage of the first nonvolatile memory cell MC1. For example, when the first nonvolatile memory cell MC1 is set to the erased state, the second nonvolatile memory cell MC2 is set to the programmed state. Alternatively, for example, when the first nonvolatile memory cell MC1 is set to the programmed state, the second nonvolatile memory cell MC2 is set to the erased state.

  The differential latch circuit 120 includes a first inverter circuit INV1 and a second inverter circuit INV2. The input (node Dout) of the first inverter circuit INV1 is electrically connected to the drain of the first nonvolatile memory cell MC1 and the output of the second inverter circuit INV2. The input (node XDout) of the second inverter circuit INV2 is electrically connected to the drain of the second nonvolatile memory cell MC2 and the output of the first inverter circuit INV1. The input of the first inverter circuit INV1 (the output of the second inverter circuit INV2) is electrically connected to the input of the output buffer 140.

  The first inverter circuit INV1 and the second inverter circuit INV2 are supplied with the power supply voltage VD0 on the high potential side during the read operation. The power supply voltage VD0 is a drain voltage of a p-type metal oxide semiconductor (hereinafter referred to as MOS) transistor in which a logic power supply voltage VDD is supplied to the source and the substrate. A gate signal XAC that becomes active during a read operation is supplied to the gate of the p-type MOS transistor. The power supply voltage VD0 is a voltage having substantially the same potential as the logic power supply voltage VDD.

  FIG. 3 is an explanatory diagram of an operation example of the nonvolatile semiconductor memory device 100 having the configuration of FIG.

  The read data output when the selection voltage VWL is supplied to the word line WL differs depending on the threshold voltage Vth of the first nonvolatile memory cell MC1 and the second nonvolatile memory cell MC2.

  When the threshold voltage of the first nonvolatile memory cell MC1 is low (for example, erased state) and the threshold voltage of the second nonvolatile memory cell MC2 is high (for example, programmed state), the following occurs. At this time, the read current of the first nonvolatile memory cell MC1 becomes larger than the read current of the second nonvolatile memory cell MC2. Therefore, the potential of the node XDout is higher than the potential of the node Dout, and an L level is output as read data. Thereafter, the states of the nodes Dout and XDout are maintained.

  When the threshold voltage Vth1 of the first nonvolatile memory cell MC1 is high (for example, the program state) and the threshold voltage Vth2 of the second nonvolatile memory cell MC2 is low (for example, the erase state), the following occurs. At this time, the read current of the second nonvolatile memory cell MC2 becomes larger than the read current of the first nonvolatile memory cell MC1. Therefore, the potential of the node Dout is higher than the potential of the node XDout, and an H level is output as read data. Thereafter, the states of the nodes Dout and XDout are maintained.

  By the way, if the difference between the threshold voltage Vth1 of the first nonvolatile memory cell MC1 and the threshold voltage Vth2 of the second nonvolatile memory cell MC2 is small, the difference between the read currents of both transistors is small. At this time, erroneous data may be latched due to the influence of switching noise of the differential latch circuit 120 or the like, or the deviation of the logical threshold levels of the first inverter circuit INV1 and the second inverter circuit INV2.

  FIG. 4 shows a first operation explanatory diagram when erroneous data is latched in the configuration of FIG. FIG. 4 shows the voltage of the word line WL, the power supply voltage VD0, and the nodes Dout and XDout by taking time on the horizontal axis when Vth1 <VDD <Vth2.

  In FIG. 4, the power supply voltage VD0 is supplied to the differential latch circuit 120 after the word line WL is activated. Therefore, when the word line WL is selected and a selection voltage is supplied, first, a read current flows through the first nonvolatile memory cell MC1 having a low threshold voltage. Therefore, the potential of the node Dout decreases and becomes L level. After that, when the power supply voltage VD0 is supplied, the node XDout that is the output of the first inverter circuit INV1 becomes the H level, and then the states of the nodes Dout and XDout are maintained.

  However, due to switching noise when the word line WL is changed from the selected state to the non-selected state, the node Dout becomes the H level (E1) or the node XDout becomes the L level (E2), and then the states of the nodes Dout and XDout change. May be maintained.

  FIG. 5 shows a second operation explanatory diagram when erroneous data is latched in the configuration of FIG. FIG. 5 shows the voltages of the word line WL, the power supply voltage VD0, and the nodes Dout and XDout by taking time on the horizontal axis when Vth1 <Vth2 <VDD.

  Also in FIG. 5, the power supply voltage VD0 is supplied to the differential latch circuit 120 after the word line WL is activated. When the word line WL is selected and a selection voltage is supplied, first, a read current flows through the first nonvolatile memory cell MC1 having a low threshold voltage. Therefore, the potential of the node Dout decreases, and both the nodes Dout and XDout become L level. After that, when the power supply voltage VD0 is supplied, the node XDout that is the output of the first inverter circuit INV1 becomes the H level, and then the states of the nodes Dout and XDout are maintained.

  However, when the power supply voltage VD0 is supplied, if there is a deviation in the logic threshold level between the first inverter circuit INV1 and the second inverter circuit INV2, the node Dout is at the H level (E3) and the node XDout is at the L level (E4). ) May be reversed. Also in this case, the states of the nodes Dout and XDout are maintained thereafter.

  Further, due to switching noise when the word line WL is changed from the selected state to the non-selected state, the node Dout becomes the H level (E5) or the node XDout becomes the L level (E6), and then the state of the nodes Dout and XDout changes. May be maintained.

  As described above, erroneous data may be latched due to the influence of switching noise of the differential latch circuit 120 or the like, or the deviation of the logic threshold levels of the first inverter circuit INV1 and the second inverter circuit INV2. . At this time, the nonvolatile semiconductor memory device 100 outputs erroneous data as read data. Therefore, in the first embodiment, when the word line WL transitions from the selected state to the non-selected state, the word line driving circuit 130 performs the following control.

  FIG. 6 is an explanatory diagram of an example of control of the word line WL by the word line driving circuit 130 in the first embodiment. FIG. 6 schematically shows the voltage change of the word line WL in the case where Vth1 <Vth2 <VDD with time on the horizontal axis.

In Figure 6, the selection state of the word line WL at the time of transition to the non-selected state, illustrates the time when the selection voltage of the word line WL is coincident with the threshold voltage Vth1 of the first nonvolatile memory cell MC1 as t ₁ . Further, the selection state of the word line WL at the time of transition to the non-selected state, illustrates the time when the selection voltage of the word line WL is coincident with the threshold voltage Vth2 of the second nonvolatile memory cell MC2 as t _2.

  The word line driving circuit 130 applies a selection voltage to the word line WL so that the time for the word line WL to transition from the selected state to the unselected state is longer than the time for the word line WL to transition from the unselected state to the selected state. Supply. This reduces the influence of switching noise when the word line WL is transitioned from the selected state to the non-selected state.

Further, the word line driving circuit 130 sets only one of the first nonvolatile memory cell MC1 and the second nonvolatile memory cell MC2 to the on state during the transition period T1 from the selected state to the unselected state of the word line WL. Control to be. The transition period T1 is (t ₂ -t ₁ ). That is, the word line driving circuit 130 has a period (T1) in which a current flows in one of the first nonvolatile memory cell MC1 and the reference current generating circuit 110 when the word line WL transitions from the selected state to the non-selected state. However, the selection voltage is supplied to the word line WL so as to be longer than the response period of the differential latch circuit 120. Here, the response period of the differential latch circuit 120 is the time for determining the output of the differential latch circuit 120 or the differential latch after the current starts to flow to one of the first nonvolatile memory cell MC1 and the reference current generation circuit 110. This is the time until the output of the circuit 120 is determined.

  FIG. 7 is an operation explanatory diagram of the first nonvolatile memory cell MC1 and the second nonvolatile memory cell MC2 during the control of the word line WL shown in FIG.

In Figure 7, the word line WL is made from the selected state to the unselected state, illustrates the non-selective control start time is the time to start lower the potential of the selected voltage as t _0. At this time, in the period from time t _{0 to} t ₁ , the first nonvolatile memory cell MC1 and the second nonvolatile memory cell MC2 are turned on, and a differential latch is generated according to the difference between the read currents of the two memory cells. The latched state of the circuit 120 is maintained.

In the period up to time t ₁ after t _2, although the first nonvolatile memory cell MC1 remains on, the second non-volatile memory cell MC2 is turned off. Accordingly, the latch state of the differential latch circuit 120 is determined only by the read current of the first nonvolatile memory cell MC1. The time t ₂ after the period, the first non-volatile memory cells MC1 and the second nonvolatile memory cell MC2 is turned off, the latch state of the differential latch circuit 120 is maintained.

  As described above, in the first embodiment, a period in which only one of the first nonvolatile memory cell MC1 and the second nonvolatile memory cell MC2 is turned on is provided, and the differential latch circuit 120 operates reliably. Can be longer than the period. In this way, even when the difference in threshold voltage between the first nonvolatile memory cell MC1 and the second nonvolatile memory cell MC2 is small and there is a manufacturing variation in the logic threshold level of the latch circuit, the differential latch circuit It is possible to avoid a situation where 120 latches erroneous data.

[Second Embodiment]
In the first embodiment, the example in which the reference current generating circuit 110 is configured by the second nonvolatile memory cell MC2 has been described. However, the embodiment according to the present invention is not limited to this.

  FIG. 8 is a circuit diagram showing a configuration example of the nonvolatile semiconductor memory device according to the second embodiment of the present invention. 8, parts similar to those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  The configuration of the non-volatile semiconductor memory device 100a in the second embodiment is different from the configuration of the non-volatile semiconductor memory device 100 shown in FIG. In the second embodiment, the reference current generation circuit 110 is configured by an n-type MOS transistor NTr. In the MOS transistor NTr, the word line WL is electrically connected to the gate, the ground voltage VSS is supplied to the source, and the drain is connected to the node XDout of the differential latch circuit 120. The MOS transistor NTr has a threshold voltage different from the threshold voltage of the first nonvolatile memory cell MC1. When the selection voltage VWL is supplied to the word line WL, a current (drain current) flows as a reference current to the MOS transistor NTr.

  In the second embodiment, the operation of the nonvolatile semiconductor memory device 100a is the same as that of the first embodiment except that the second nonvolatile memory cell MC2 in FIG. 2 is replaced with a MOS transistor NTr. . That is, in the second embodiment, a period in which only one of the first nonvolatile memory cell MC1 and the MOS transistor NTr is turned on is set to be longer than a period in which the differential latch circuit 120 operates reliably. In this way, even if the difference in threshold voltage between the first nonvolatile memory cell MC1 and the MOS transistor NTr is small and there is a manufacturing variation in the logic threshold level of the latch circuit, the differential latch circuit 120 generates erroneous data. The situation of latching can be avoided.

[Third Embodiment]
In the first embodiment or the second embodiment, the selection voltage is supplied as shown in FIG. 6 in the selected state of the word line WL regardless of the read operation or the write operation. However, the present invention is not limited to this.

  FIG. 9 shows a circuit diagram of a configuration example of the nonvolatile semiconductor memory device according to the third embodiment of the present invention. 9, parts that are the same as those in FIG. 2 are given the same reference numerals, and descriptions thereof will be omitted as appropriate.

  The configuration of the nonvolatile semiconductor memory device 100b in the third embodiment is different from the configuration of the nonvolatile semiconductor memory device shown in FIG. 2 in the configuration of the word line driving circuit. In FIG. 9, the reference current generation circuit 110 is illustrated as being configured by the second nonvolatile memory cell MC2, but the reference current generation circuit 110 may be configured by the MOS transistor NTr in FIG.

  In addition to the selection voltage VWL and the word line selection signal WLsel, the driving capability switching signal RE is input to the word line driving circuit 130a in the third embodiment. The word line driving circuit 130a drives the word line WL by switching the current driving capability according to the driving capability switching signal RE. By controlling the timing of the drive capability switching signal RE, for example, the word line WL can be controlled as shown in FIG. 6 only during the transition from the selected state of the word line WL to the non-selected state.

  Such a word line drive circuit 130a includes inverter circuits INV3 and INV4, a negative OR circuit NR1, and a third drive transistor DTr3.

  A word line selection signal WLsel whose H level is an active level is input to the inverter circuit INV3. A word line selection signal WLsel and a drive capability switching signal RE are input to the negative OR circuit NR1.

  The inverter circuit INV4 includes a p-type first drive transistor DTr1 whose word line WL is electrically connected to its drain, and an n-type second drive transistor DTr2 whose word line WL is electrically connected to its drain. It has. Each of the first drive transistor DTr1 and the second drive transistor DTr2 is configured by a MOS transistor. The output of the inverter circuit INV3 is electrically connected to the gate of the first drive transistor DTr1 and the gate of the second drive transistor DTr2. The selection voltage VWL is supplied to the source of the first driving transistor DTr1 as the power supply voltage on the high potential side, and the ground voltage VSS is supplied to the source of the second driving transistor DTr2.

  The word line driving circuit 130a preferably controls the current driving capability of the second driving transistor DTr2 to be lower than the current driving capability of the first driving transistor DTr1 during the read operation. By doing so, the time for the potential change of the word line WL is lengthened during the transition period from the selected state of the word line WL to the non-selected state during the read operation.

  Therefore, in the third embodiment, the word line drive circuit 130a includes a third drive transistor DTr3 in parallel with the second drive transistor DTr2. The third drive transistor DTr3 is composed of an n-type MOS transistor, the drain of the second drive transistor DTr2 is electrically connected to the drain, and the ground voltage VSS is supplied to the source (grounded). The output of the NOR circuit NR1 is electrically connected to the gate of the third drive transistor DTr3.

  In the word line driving circuit 130a configured as described above, when the driving capability switching signal RE is at L level and the word line selection signal WLsel is at L level, the third driving transistor DTr3 is turned on, and the ground voltage VSS is applied to the word line WL. Supply. At this time, the second drive transistor DTr2 is also turned on, and charges can be extracted from the word line WL with high current drive capability.

  In the word line drive circuit 130a, when the drive capability switching signal RE is at L level and the word line selection signal WLsel is at H level, the third drive transistor DTr3 is turned off. At this time, in the word line driving circuit 130a, the first driving transistor DTr1 is turned on to supply the selection voltage VWL to the word line WL.

  Similarly, in the word line driving circuit 130a, when the driving capability switching signal RE is at the H level and the word line selection signal WLsel is at the L level, the third driving transistor DTr3 is turned off and the ground voltage VSS is supplied to the word line WL. To do. At this time, the second driving transistor DTr2 is turned on, and charges can be extracted from the word line WL with a low current driving capability.

  In the word line driving circuit 130a, when the driving capability switching signal RE is at the H level and the word line selection signal WLsel is at the H level, the third driving transistor DTr3 is turned off. At this time, in the word line driving circuit 130a, the first driving transistor DTr1 is turned on to supply the selection voltage VWL to the word line WL.

  As described above, the word line driving circuit 130a can switch the current driving capability according to the logic level of the driving capability switching signal RE and drive the word line WL when the word line WL transitions from the selected state to the non-selected state. it can. Specifically, the drive capability switching signal RE is set to the H level during the read operation, and the drive capability switching signal RE is set to the L level during other than the read operation. Thereby, the word line driving circuit 130a can supply the selection voltage to the word line WL so that the transition period T1 in FIG. 6 is equal to or longer than the response period of the differential latch circuit 120 only during the read operation. In the third embodiment, the transition period T1 includes the first nonvolatile memory cell MC1 and the second nonvolatile memory cell MC2 (in a broad sense, the reference line when the word line WL transitions from the selected state to the unselected state. This is a period in which a current flows through one of the current generation circuits 110).

  By doing so, the difference in threshold voltage between the first nonvolatile memory cell MC1 and the second nonvolatile memory cell MC2 (or MOS transistor NTr) is small, and there is a manufacturing variation in the logic threshold level of the latch circuit. However, a situation in which the differential latch circuit 120 latches erroneous data can be avoided. Furthermore, the transition time from the selected state of the word line WL to the non-selected state can be shortened during the operation other than the read operation compared to the read operation. Therefore, an increase in writing time other than reading can be suppressed, and an increase in reading time can be minimized.

[Fourth Embodiment]
In the third embodiment, the third driving transistor DTr3 is provided, and the example of switching the current driving capability when driving the word line WL by controlling the third driving transistor DTr3 has been described. The embodiment is not limited to this.

  FIG. 10 shows a circuit diagram of a configuration example of the nonvolatile semiconductor memory device according to the fourth embodiment of the present invention. 10, parts that are the same as those in FIG. 9 are given the same reference numerals, and descriptions thereof will be omitted as appropriate.

  The configuration of the nonvolatile semiconductor memory device 100c in the fourth embodiment is different from the configuration of the nonvolatile semiconductor memory device 100b shown in FIG. 9 in the configuration of the word line driving circuit. In FIG. 10, the reference current generation circuit 110 is illustrated as being configured by the second nonvolatile memory cell MC2, but the reference current generation circuit 110 may be configured by the MOS transistor NTr in FIG.

  In addition to the selection voltage VWL and the word line selection signal WLsel, the driving capability switching signal RE is input to the word line driving circuit 130b in the fourth embodiment. The word line driving circuit 130b controls the word line WL shown in FIG. 6 only during a period of transition from the selected state of the word line WL to the non-selected state by the drive capability switching signal RE. The word line driving circuit 130b includes inverter circuits INV3 and INV5, a first driving transistor DTr1, a second driving transistor DTr2, a fourth driving transistor DTr4, and a resistance element R1.

  A word line selection signal WLsel whose H level is an active level is input to the inverter circuit INV3. A drive capability switching signal RE is input to the inverter circuit INV5.

  The first driving transistor DTr1 is composed of a p-type MOS transistor, the selection voltage VWL is supplied to the source, the output of the inverter circuit INV3 is electrically connected to the gate, and the word line WL is electrically connected to the drain. Is done. The second drive transistor DTr2 is configured by an n-type MOS transistor. The second drive transistor DTr2 has a drain electrically connected to the word line WL, a gate electrically connected to the output of the inverter circuit INV3, a source connected to one end of the resistor element R1, and a fourth drive transistor DTr4 drain Are electrically connected. The fourth drive transistor DTr4 has a drain electrically connected to the source of the second drive transistor DTr2, a gate electrically connected to the output of the inverter circuit INV5, and a source supplied with the ground voltage VSS. The ground voltage VSS is supplied to the other end of the resistance element R1.

  In the word line drive circuit 130b having such a configuration, when the drive capability switching signal RE is at L level, the fourth drive transistor DTr4 is turned on. Therefore, when the word line selection signal WLsel is at the L level, the charges charged in the word line WL are discharged via the fourth drive transistor DTr4. On the other hand, when the drive capability switching signal RE is at the H level, the fourth drive transistor DTr4 is turned off. Therefore, when the word line selection signal WLsel is at the L level, the charges charged in the word line WL are discharged through the resistance element R1. Therefore, the current drive capability when extracting charges from the word line WL can be switched by the drive capability switching signal RE.

  In this way, the word line driving circuit 130b can be switched by the driving capability switching signal RE so that the current driving capability is lowered at least in the selected state from the selected state of the word line WL during the read operation. Accordingly, the word line driving circuit 130b can supply the selection voltage to the word line WL so that the transition time T1 in FIG. 6 is equal to or longer than the response period of the differential latch circuit 120 only during the read operation. In the fourth embodiment, the transition period T1 includes the first nonvolatile memory cell MC1 and the second nonvolatile memory cell MC2 (in a broad sense, the reference line when the word line WL transitions from the selected state to the unselected state. This is a period in which a current flows through one of the current generation circuits 110).

  By doing so, the difference in threshold voltage between the first nonvolatile memory cell MC1 and the second nonvolatile memory cell MC2 (or MOS transistor NTr) is small, and there is a manufacturing variation in the logic threshold level of the latch circuit. However, a situation in which the differential latch circuit 120 latches erroneous data can be avoided. Furthermore, the transition time from the selected state of the word line WL to the non-selected state can be shortened during the operation other than the read operation compared to the read operation. Therefore, an increase in writing time other than reading can be suppressed, and an increase in reading time can be minimized.

[Fifth Embodiment]
In the fourth embodiment, the resistance element R1 is provided to switch the current driving capability. However, the embodiment according to the present invention is not limited to this. In the fifth embodiment, for example, the function of the resistance element R1 is realized by a MOS transistor.

  FIG. 11 is a circuit diagram showing a configuration example of the nonvolatile semiconductor memory device according to the fifth embodiment of the invention. In FIG. 11, the same parts as those in FIG.

  The configuration of the nonvolatile semiconductor memory device 100d in the fifth embodiment is different from the configuration of the nonvolatile semiconductor memory device 100c shown in FIG. 10 in the configuration of the word line driving circuit. In FIG. 11, the reference current generation circuit 110 is illustrated as being configured by the second nonvolatile memory cell MC2, but the reference current generation circuit 110 may be configured by the MOS transistor NTr in FIG.

  In addition to the selection voltage VWL and the word line selection signal WLsel, the driving capability switching signal RE is input to the word line driving circuit 130c in the fifth embodiment. The word line driving circuit 130c controls the word line WL shown in FIG. 6 only during a period of transition from the selected state of the word line WL to the non-selected state by the driving capability switching signal RE. The word line driving circuit 130c includes inverter circuits INV3 and INV5, a first driving transistor DTr1, a second driving transistor DTr2, a fourth driving transistor DTr4, and a MOS transistor NTr1.

  A word line selection signal WLsel whose H level is an active level is input to the inverter circuit INV3. A drive capability switching signal RE is input to the inverter circuit INV5.

  The first driving transistor DTr1 is composed of a p-type MOS transistor, the selection voltage VWL is supplied to the source, the output of the inverter circuit INV3 is electrically connected to the gate, and the word line WL is electrically connected to the drain. Is done. The second drive transistor DTr2 is configured by an n-type MOS transistor. The second drive transistor DTr2 has a drain electrically connected to the word line WL, a gate electrically connected to the output of the inverter circuit INV3, a source connected to the drain of the MOS transistor Tr5, and a fourth drive transistor DTr4 drain Are electrically connected. In the fourth drive transistor DTr4, the drain is electrically connected to the source of the second drive transistor DTr2, the gate is electrically connected to the output of the inverter circuit INV5, and the ground voltage VSS is supplied to the source. The MOS transistor NTr1 is an n-type MOS transistor, and the selection voltage VWL is supplied to the gate of the MOS transistor NTr1, and the ground voltage VSS is supplied to the source.

  In the word line driving circuit 130c having such a configuration, when the driving capability switching signal RE is at L level, the fourth driving transistor DTr4 is turned on. For this reason, when the word line selection signal WLsel is at the L level, the charges charged in the word line WL are discharged via the fourth drive transistor DTr4. On the other hand, when the drive capability switching signal RE is at the H level, the fourth drive transistor DTr4 is turned off. Therefore, when the word line selection signal WLsel is at the L level, the charges charged in the word line WL are discharged via the MOS transistor NTr1. Therefore, the current drive capability when extracting charges from the word line WL can be switched by the drive capability switching signal RE.

  As described above, the word line driving circuit 130c can be switched by the driving capability switching signal RE so that the current driving capability is lowered at least from the selected state of the word line WL during the read operation to the non-selected state. Thereby, the word line driving circuit 130c can supply the selection voltage to the word line WL so that the transition time T1 in FIG. 6 is equal to or longer than the response period of the differential latch circuit 120 only during the read operation. In the fifth embodiment, the transition period T1 includes the first nonvolatile memory cell MC1 and the second nonvolatile memory cell MC2 (in a broad sense, the reference line when the word line WL transitions from the selected state to the unselected state. This is a period in which a current flows through one of the current generation circuits 110).

  By doing so, the difference in threshold voltage between the first nonvolatile memory cell MC1 and the second nonvolatile memory cell MC2 (or MOS transistor NTr) is small, and there is a manufacturing variation in the logic threshold level of the latch circuit. However, a situation in which the differential latch circuit 120 latches erroneous data can be avoided. Furthermore, the transition time from the selected state of the word line WL to the non-selected state can be shortened during operations other than during the read operation. Therefore, an increase in writing time other than reading can be suppressed, and an increase in reading time can be minimized.

[Application to integrated circuit devices]
The nonvolatile semiconductor memory device in any one of the above embodiments is suitable for incorporation in an integrated circuit device that improves reliability. Hereinafter, a microcomputer will be described as an example of the integrated circuit device in which the nonvolatile semiconductor memory device according to any one of the above embodiments is built. However, the integrated circuit device according to the present invention is not limited to the microcomputer. Absent.

  FIG. 12 shows a block diagram of a configuration example of a microcomputer according to the present invention.

  The microcomputer 400 includes a central processing unit (CPU) 410, a read only memory (ROM) 412, and a random access memory (RAM) 414. . Further, the microcomputer 400 includes a display driver 416, a timer circuit 418, an I / O circuit 420, and a power supply circuit 422. The CPU 410, ROM 412, RAM 414, display driver 416, timer circuit 418, I / O circuit 420, and power supply circuit 422 are connected via a bus 424.

  The CPU 410 reads a program or data stored in the ROM 412 or the RAM 414 via the bus 424 and executes processing corresponding to the read program or data. Thus, the CPU 410 controls the display driver 416, the timer circuit 418, the I / O circuit 420, and the power supply circuit 422. The ROM 412 is applied with the nonvolatile semiconductor memory device in any of the above-described embodiments, and stores a program in advance. The RAM 414 is used as a program storage area or work area. The display driver 416 performs image display control on a display device connected to the outside of the microcomputer 400 based on image data generated by the CPU 410 or the like and stored in the RAM 414. The timer circuit 418 measures the time and performs a timer interrupt to the CPU 410 and the like. The I / O circuit 420 realizes I / O access from a device connected to the outside of the microcomputer 400. The power supply circuit 422 generates power to be supplied to each part constituting the microcomputer 400.

  At least one of the CPU 410, the RAM 414, the display driver 416, the timer circuit 418, the I / O circuit 420, and the power supply circuit 422 is initialized by trimming data as a processing device. Trimming data is stored in the ROM 412 in advance, and is supplied to each part of the processing apparatus via a signal line such as the bus 424 when the power is turned on. That is, the processing device is controlled based on data (trimming data) read from the ROM 412.

  As described above, the microcomputer 400 to which the nonvolatile semiconductor memory device according to any one of the above embodiments is applied is equipped with the ROM 412 that can read data accurately without being affected by switching noise or the like. Therefore, it is possible to provide a microcomputer that can read data accurately and has high reliability.

〔Electronics〕
The nonvolatile semiconductor memory device in any of the above embodiments or the microcomputer 400 in FIG. 12 can be applied to the following electronic apparatus.

  FIG. 13 is a block diagram illustrating a configuration example of an electronic device according to the present invention.

  The electronic device 500 includes a processing unit 510, a storage unit 512, an operation unit 514, and a display unit 516. For example, the function of the processing unit 510 is realized by a known microcomputer, and the function of the storage unit 512 is realized by a hard disk drive device or the nonvolatile semiconductor memory device in any of the above embodiments. Alternatively, for example, the function of the processing unit 510 is realized by the microcomputer 400 of FIG. 12, and the function of the storage unit 512 is realized by a hard disk drive device or a known storage device. The operation unit 514 receives input data for controlling the electronic device 500. The processing unit 510 can change the process according to the input data received by the operation unit 514. The function of the display unit 516 is realized by a known display device such as a liquid crystal display panel or an organic electroluminescence (EL) display device. Such a display unit 516 displays an image generated by the processing unit 510.

  14A and 14B are perspective views of a configuration example of the electronic device 500 in FIG. FIG. 14A illustrates a perspective view of a configuration example of a mobile personal computer. FIG. 14B is a perspective view of a configuration example of a mobile phone.

  A personal computer 800 shown in FIG. 14A, which is one example of the configuration of the electronic device 500 in FIG. 13, includes a main body 810, a display portion 820, and an operation portion 830. The main body 810 includes the processing unit 510, the storage unit 512, and the like in FIG. The display unit 820 corresponds to the display unit 516 in FIG. 13, and its function is realized by, for example, a liquid crystal display panel. The operation unit 830 corresponds to the operation unit 514 in FIG. 13 and its function is realized by a keyboard or the like. The operation information via the operation unit 830 is analyzed by the processing unit 510 of the main body unit 810, and an image is displayed on the display unit 820 according to the operation information. Accordingly, a nonvolatile semiconductor memory device that can read data accurately without being affected by switching noise or the like is applied, and a personal computer 800 that achieves low power consumption can be provided.

  A cellular phone 900 illustrated in FIG. 14B that is one example of a configuration of the electronic device 500 illustrated in FIG. 13 includes a main body portion 910, a display portion 920, and an operation portion 930. The main body 910 includes the processing unit 510, the storage unit 512, and the like in FIG. The display unit 920 corresponds to the display unit 516 in FIG. 13, and its function is realized by, for example, a liquid crystal display panel. The operation unit 930 corresponds to the operation unit 514 in FIG. 13 and its function is realized by buttons and the like. The operation information via the operation unit 930 is analyzed by the processing unit 510 of the main body unit 910, and an image is displayed on the display unit 920 according to the operation information. Accordingly, a nonvolatile semiconductor memory device that can read data accurately without being affected by switching noise or the like is applied, and a mobile phone 900 that achieves low power consumption can be provided.

  Note that the electronic device 500 in FIG. 13 is not limited to the electronic device 500 illustrated in FIGS. 14A and 14B. For example, personal digital assistants (PDAs), digital still cameras, televisions, video cameras, car navigation devices, pagers, electronic notebooks, electronic paper, calculators, word processors, workstations, video phones, POS (Point of sale systems ) Devices such as terminals, printers, scanners, copiers, video players and touch panels.

  As described above, the nonvolatile memory device, the integrated circuit device, the electronic device, and the like according to the present invention have been described based on any one of the above embodiments. However, the present invention is not limited to any one of the above embodiments. Absent. For example, the present invention can be implemented in various modes without departing from the gist thereof, and the following modifications are possible.

  (1) In any of the above embodiments, the nonvolatile semiconductor memory device has been described as an example of the nonvolatile memory device according to the present invention. However, the present invention is not limited to this. The present invention can be applied to a nonvolatile memory device having a differential latch circuit when reading data.

  (2) In any of the above embodiments, the example in which the reference current generating circuit is configured by a nonvolatile memory cell or a MOS transistor has been described. However, the present invention is not limited to this. For example, the reference current generation circuit may include a current source, and when the selection voltage is supplied to the word line, the current source may be connected to a predetermined node of the differential latch circuit.

  (3) In any of the above embodiments, for example, binary of data 1 or data 0, binary of program state or erase state has been described as an example, but a nonvolatile memory cell that stores multi-value data is provided. You may apply also to a non-volatile memory | storage device.

  (4) In any of the above embodiments, the phrase “gate” means a gate terminal, a gate region, or a gate electrode. Similarly, the phrase “drain” means a drain terminal, a drain region, or a drain electrode. The phrase “source” means a source terminal, a source region, or a source electrode.

  (5) In any of the above embodiments, a MOS transistor has been described as an example of a transistor. However, the present invention is not limited to this.

  (6) In any of the above embodiments, the present invention has been described as a nonvolatile memory device, an integrated circuit device, an electronic device, and the like, but the present invention is not limited to this. For example, a data reading method in a nonvolatile memory device including the differential latch circuit in any of the above embodiments may be used.

10 ... Memory cell array, 20 ... Regular memory cell array,
30 ... Redundant memory cell array, 40 ... Fuse memory cell array,
100, 100a, 100b ... non-volatile semiconductor memory device (non-volatile memory device),
110: a reference current generation circuit, 120: a differential latch circuit,
130, 130a, 130b ... word line drive circuit, 140 ... output buffer,
400 ... microcomputer, 410 ... CPU, 412 ... ROM,
414 ... RAM, 416 ... display driver, 418 ... timer circuit,
420 ... I / O circuit, 422 ... power supply circuit, 424 ... bus, 500 ... electronic device,
510 ... Processing unit (processing device), 512 ... Storage unit, 514 ... Operation unit,
516, 820, 920 ... display unit, 800 ... personal computer,
810, 910 ... main body, 830, 930 ... operation part, 900 ... mobile phone,
BL ... bit line, INV1, INV2, INV3, INV4, INV5 ... inverter circuit, Dout, XDout ... node, DTr1 ... first drive transistor,
DTr2 ... second drive transistor, DTr3 ... third drive transistor,
DTr4 ... fourth drive transistor, MC1 ... first nonvolatile memory cell,
MC2 ... second non-volatile memory cell, MCE ... defective memory cell,
NR1 ... NAND circuit, NTr, Tr5 ... MOS transistor,
R1 ... resistance element, RE ... driving capability switching signal, VDD ... logic power supply voltage,
VD0: power supply voltage, VSS: ground voltage, VWL: selection voltage, WL: word line,
WLsel: Word line selection signal, XAC: Gate signal

Claims (11)

A first non-volatile memory cell;
A word line driving circuit for supplying a selection voltage to a word line for selecting the first nonvolatile memory cell;
A reference current generating circuit for generating a reference current when the selection voltage is supplied to the word line;
A differential latch circuit that latches data according to a difference between a current flowing through the first nonvolatile memory cell and the reference current when the selection voltage is supplied to the word line;
The word line driving circuit includes:
Nonvolatile driving the word line so that the time for the word line to transition from the selected state to the unselected state is longer than the time for the word line to transition from the unselected state to the selected state. Sex memory device. In claim 1,
The word line driving circuit includes:
A period in which a current flows in one of the first nonvolatile memory cell and the reference current generation circuit when the word line transitions from the selected state to the non-selected state is a response period of the differential latch circuit The nonvolatile memory device is characterized in that the word line is driven as described above. In claim 2,
The word line driving circuit includes:
Only during a read operation, a period in which a current flows through one of the first nonvolatile memory cell and the reference current generation circuit when the word line transitions from the selected state to the non-selected state is the response period. The nonvolatile memory device is characterized in that the word line is driven as described above. In claim 3,
The word line driving circuit includes:
A p-type first driving transistor having the drain electrically connected to the word line;
An n-type second drive transistor having the drain electrically connected to the word line;
An n-type third drive transistor having a drain electrically connected to a drain of the second drive transistor and a source supplied with a ground voltage;
The third driving transistor is:
A non-volatile memory device that is gate-controlled by a given drive capability switching signal. In claim 3,
The word line driving circuit includes:
A p-type first driving transistor having the drain electrically connected to the word line;
An n-type second drive transistor having the drain electrically connected to the word line;
An n-type third drive transistor having a drain electrically connected to the drain of the second drive transistor and a ground voltage supplied to the source;
A resistor element having one end electrically connected to the drain of the third driving transistor and the other end supplied with the ground voltage;
The third driving transistor is:
A non-volatile memory device that is gate-controlled by a given drive capability switching signal. In claim 5,
The resistance element is
A non-volatile memory device comprising a metal oxide semiconductor transistor. In any one of Claims 1 thru | or 6.
The reference current generation circuit includes:
A nonvolatile memory device, wherein the nonvolatile memory device is a second nonvolatile memory cell having a threshold voltage different from a threshold voltage of the first nonvolatile memory cell. In any one of Claims 1 thru | or 6.
The reference current generation circuit includes:
A nonvolatile memory device comprising a metal oxide semiconductor transistor having a threshold voltage different from a threshold voltage of the first nonvolatile memory cell. The nonvolatile memory device according to any one of claims 1 to 8,
And a processing device controlled based on data read from the nonvolatile memory device.   An electronic device comprising the nonvolatile memory device according to claim 1.   An electronic device comprising the integrated circuit device according to claim 9.

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