JP5533264B2 - Semiconductor memory - Google Patents

Description

The present invention relates to a semiconductor memory, and more particularly, an SRAM (Static Random) capable of high speed operation with low power consumption.
Access Memory).

  In recent years, not only system LSIs but also memories have been demanded for lower voltage and lower power consumption. Among the memories, the most frequently used and indispensable memory is SRAM. However, this SRAM is easily affected by process variations and is the most difficult memory to lower the voltage. At present, by reducing the threshold voltage of the transistor as much as possible, the operation margin of the SRAM is secured and the voltage is reduced.

JP 7-2111079 A

  However, when the threshold voltage of the transistor is lowered in order to reduce the power supply voltage of the SRAM, a leakage current (hereinafter referred to as off-leakage) that flows through the transistor when the transistor is OFF increases, and this off-leakage reduces the power consumption of the SRAM. increase. For this reason, there is a limit to lowering the threshold voltage of the transistor. At present, when the power supply voltage of the SRAM is set to 0.5 V, the operation of the SRAM can no longer be guaranteed.

  The present invention has been made in view of the circumstances described above, and an object of the present invention is to provide an SRAM capable of avoiding the problem of off-leakage and operating at a low voltage.

  In the present invention, a cell array in which memory cells are arranged in a matrix and a row selection voltage associated with a row to which a memory cell to be accessed belongs are set to an active level, and the memory cell belonging to the row is connected to a bit line In a semiconductor memory that accesses a memory cell that is an access target through a bit line, each row of memory cells that belong to the row when the row selection voltage for the row to which the memory cell that is the access target is set to an active level There is provided a semiconductor memory characterized by comprising power supply voltage control means for increasing the power supply voltage with respect to the power supply voltage for other rows.

  According to this invention, since the power supply voltage for the row to which the memory cell to be accessed belongs increases, the operation margin of the memory cell to be accessed is widened, and a stable access operation can be obtained. On the other hand, since a normal power supply voltage is applied to a row to which a memory cell to be accessed does not belong, there is no problem in holding stored information in the memory cell of each row.

It is a block diagram which shows the general structural example of SRAM which is an example to which this invention is applied. 3 is a circuit diagram showing a specific circuit configuration of the SRAM. FIG. It is a circuit diagram which shows the structural example of one memory cell in the SRAM cell array of the SRAM. It is a figure which illustrates the measuring method of SNM (Static Noise Margin; static noise margin) of a memory cell. It is a figure which illustrates the measurement result of SNM of a memory cell. 1 is a circuit diagram showing a configuration of an SRAM according to a first embodiment of the present invention. FIG. 3 is a circuit diagram showing a configuration example of a row selection circuit in the same embodiment. It is a circuit diagram which shows the structural example of the level shifter in the embodiment. It is a figure showing an example of composition of a power circuit in the embodiment. It is a circuit diagram which shows the structure of SRAM which is 2nd Embodiment of this invention. FIG. 3 is a circuit diagram showing a configuration example of a row selection circuit in the same embodiment. It is a circuit diagram which shows the structural example of the level shifter in the embodiment. It is a circuit diagram which shows the structure of SRAM which is 2nd Embodiment of this invention. FIG. 3 is a circuit diagram showing a configuration example of a row selection circuit in the same embodiment. It is a circuit diagram which shows the structural example of the level shifter in the embodiment.

Embodiments of the present invention will be described below with reference to the drawings.
<Application examples of the present invention>
FIG. 1 is a block diagram showing a configuration of an SRAM which is an application target example of the present invention. In FIG. 1, an SRAM cell array 100 is a circuit in which memory cells each storing 1-bit information are arranged in a matrix. The control circuit 900 is a circuit that generates various internal control signals for performing write access and read access to a desired memory cell in accordance with various control signals given from the outside. The SRAM is roughly classified into an asynchronous SRAM and a synchronous SRAM. In the case of an asynchronous SRAM, the control circuit 900 is supplied with, for example, a chip enable signal CEB, an output enable signal OEB, and a write enable signal WEB. In this case, the control circuit 900 generates an internal control signal for executing write access in response to both the write enable signal WEB and the chip enable signal CEB becoming active levels (in this example, L level). In addition, the control circuit 900 generates an internal control signal for executing read access in response to both the output enable signal OEB and the chip enable signal CEB becoming active levels (in this example, L level). In the case of a synchronous SRAM, a clock CLK instructing the synchronization timing is given to the control circuit 900. The control circuit 900 generates various internal control signals for write access and read access based on the clock CLK.

  The input / output buffer 500 is a 16-bit input / output circuit having both an input buffer function and an output buffer function. Input / output buffer 500 functions as an input buffer under the control of control circuit 900 at the time of write access, and writes 16-bit write data input via data input / output terminals I / O0 to I / O15. Supply to circuit 600. In read access, the input / output buffer 500 functions as an output buffer under the control of the control circuit 900, and the 16-bit read data output from the sense amplifier 400 is used as data input / output terminals I / O0 to I / O15. Output from.

  The column gate 700 is an aggregate of a plurality of switches interposed between the write circuit 600 and the sense amplifier 400 and the SRAM cell array 100, and includes 16 memory cells corresponding to arbitrary addresses in the SRAM cell array 100. It serves to interconnect the write circuit 600 and the sense amplifier 400.

  Write circuit 600 applies 16-bit write data supplied via input / output buffer 500 to 16-bit memory cells in SRAM cell array 100 connected via column gate 700 at the time of write access. A circuit for writing. The sense amplifier 400 is a circuit that reads data from 16-bit memory cells in the SRAM cell array 100 connected via the column gate 700 and outputs the data to the input / output buffer 500 during read access.

  The address input circuit 800 is supplied with 24-bit address data A0 to A23 for specifying the addresses of the 16 memory cells to be accessed at the time of write access and read access. When a write access or a read access is performed, the address input circuit 800 holds address data A0 to A23 for specifying a memory cell to be accessed under the control of the control circuit 900.

  The address data A0 to A23 output from the address input circuit 800 are separated into row address data (upper bit data) and column address data (lower bit data), the row address data is sent to the row decoder 200, and the column address data is sent to the column address data. This is supplied to the column decoder 300. The row decoder 200 selects each memory cell belonging to the row specified by the row address among the memory cells constituting the SRAM cell array 100. The column decoder 300 causes the column gate 700 to select a memory cell belonging to the column specified by the column address among the memory cells belonging to the row selected by the row decoder 200 in the SRAM cell array 100, and the write circuit 600 and the sense amplifier 400 is a circuit to be connected to 400.

  FIG. 2 is a circuit diagram illustrating a detailed internal configuration of the SRAM shown in FIG. In FIG. 2, in order to prevent the drawing from becoming complicated, not all the memory cells of the SRAM cell array 100 shown in FIG. 1, but the data input / output terminals I / O0 to I / O15 shown in FIG. The memory cell matrix Mmn-0 in the range of the storage destination of the 0th bit of the 16-bit data inputted / outputted through the index (the index “0” in Mmn-0 is the 0th to 15th bits). Only 0) is shown. 2, in order to prevent the drawing from becoming complicated, among all the switches constituting the column gate 700, the memory cell matrix Mmn-0, the write circuit 600, and the sense amplifier 400 are interposed. Only the switch to be shown is shown.

  As shown in FIG. 2, the memory cell matrix Mmn-0 used as the 0th bit storage area is configured by m + 1 rows and n + 1 columns of memory cells Mij (i = 0 to m, j = 0 to n). Yes. In the memory cell matrix Mmn-0, for each column, a pair of bit lines BITj and BITjB are wired along the arrangement direction of m + 1 memory cells Mij (i = 0 to m) belonging to the column. Each time, word lines are wired along the direction in which n + 1 memory cells Mij (j = 0 to n) belonging to the row are arranged.

  The row decoder 200 in FIG. 1 includes m + 1 row selection circuits 200-i (i = 0 to m) shown in FIG. Each of the row selection circuits 200-i (i = 0 to m) is connected to a word line of each row of the memory cell matrix Mmn-0. Each of the row selection circuits 200-i (i = 0 to m) has an active level when the row number i ′ indicated by the row address matches the row number i associated with the row selection circuit 200-i. A NAND gate 201 that outputs (L level) and an inverter 202 that outputs a row selection voltage WLi obtained by inverting the output signal of the NAND gate 201 to a word line. By the action of these row selection circuits 200-i (i = 0 to m), the row selection voltage corresponding to the row number i ′ indicated by the row address among the row selection voltages WLi (i = 0 to m) corresponding to each row. Only WLi ′ is set to the H level, and the other row selection voltages WL-i (i ≠ i ′) are set to the L level. This is a row selection operation performed by the row decoder 200.

  The column gate 700 has n + 1 pairs of switches CGj and CGjB (j = 0 to n) as a switch group corresponding to the memory cell matrix Mmn-0. The n + 1 pairs of switches CGj and CGjB (j = 0 to n) are each configured by an n-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor; field effect transistor having a metal oxide semiconductor structure; hereinafter simply referred to as a transistor). Has been. One end of each of the switch pair CGj and CGjB (j = 0 to n) is connected to the bit line pair BITj and BITjB (j = 0 to n) corresponding to each column of the memory cell matrix Mmn-0. The other end is commonly connected to a global bit line pair DL and DLB corresponding to the 0th bit.

  The column decoder 300 in FIG. 1 is composed of n + 1 column selection circuits 300-j (j = 0 to n) shown in FIG. This column selection circuit 300-j (j = 0 to n) is associated with each column of the memory cell matrix Mmn-0, and the switch pair (transistor pair) CGj and CGjB (j = 0 to n). A column selection voltage COLj (j = 0 to n) is supplied to each gate. Each of the column selection circuits 300-j (j = 0 to n) has an active level when the column number j ′ indicated by the column address matches the column number j associated with the column selection circuit 300-j. A NAND gate 301 that outputs (L level) and an inverter 302 that inverts the output signal of the NAND gate 301 and outputs the inverted signal to the gates of the switch pair CGj and CGjB as the column selection voltage COLj. By the operation of these column selection circuits 300-j (j = 0 to n), the switch pair corresponding to the column number j ′ indicated by the column address among the switch pairs (transistor pairs) CGj and CGjB (j = 0 to n). Only (transistor pair) CGj ′ and CGj′B are ON, and the other switch pair (transistor pair) CGj and CGjB (j ≠ j ′) are OFF. Accordingly, only the bit line pair BITj ′ and BITj′B in the column corresponding to the column number j ′ indicated by the column address is connected to the global bit line pair DL and DLB via the switch pair (transistor pair) CGj ′ and CGj′B. Is done.

At the time of write access, the write circuit 600 is connected to the bit line pair BITj ′ and BITj′B through the bit line pair BITj ′ and BITj′B thus connected to the global bit line pair DL and DLB. Write data (the 0th bit here) is written to one memory cell selected based on the row address among the m + 1 memory cells. In read access, the sense amplifier 400 is connected to the bit line pair BITj ′ and BITj′B via the bit line pair BITj ′ and BITj′B thus connected to the global bit line pair DL and DLB. Data (here, the 0th bit) is read out from one memory cell selected based on the row address among the m + 1 memory cells that have been output, and output to the input / output buffer 500.
Although only the configuration of the portion related to the storage of the 0th bit has been described above, the configuration of the portion related to the storage of the other 1st to 15th bits is the same.

  FIG. 3 is a circuit diagram showing a specific configuration example of one memory cell in the SRAM cell array 100. In FIG. 3, BL and BLB are any bit line pair in the bit line pair BITj and BITjB (j = 0 to n) in FIG. 2, and WL is the row selection voltage WLi (i = 0 to m).

  As shown in FIG. 3, the memory cell has P-channel transistors P1 and P2 and N-channel transistors N1, N2, Ta1, and Ta2. Here, the P-channel transistor P1 and the N-channel transistor N1 are inserted in series between the high-potential-side power supply VDD and the low-potential-side power supply VSS, and constitute a CMOS inverter. The P-channel transistor P2 and the N-channel transistor N2 are also inserted in series between the high potential side power supply VDD and the low potential side power supply VSS, and constitute a CMOS inverter. These CMOS inverters use each other's output signal as an input signal, and constitute a flip-flop. The N channel transistor Ta1 is interposed between the bit line BL and a connection point between both drains of the P channel transistor P1 and the N channel transistor N1. The N channel transistor Ta2 is interposed between the bit line BLB and a connection point between both drains of the P channel transistor P2 and the N channel transistor N2. These N-channel transistors Ta1 and Ta2 are turned on when a row selection voltage WL of H level is applied to the gate through the word line at the time of write access and read access, and the bit line BL and bit line BLB are turned on by the transistor P1. And N1 and a common connection point of the transistors P2 and N2, respectively.

Write access to this memory cell is performed as follows.
(1) The column decoder 300 shown in FIGS. 1 and 2 connects the bit line pair corresponding to the column to which the memory cell belongs to the write circuit 600 via the column gate 700.
(2) A pair of bit lines in which the write circuit 600 shown in FIGS. 1 and 2 applies a positive / reverse two-phase bit signal corresponding to the write data “1” / “0” via the column gate 700. Output to BL and BLB. More specifically, when the write data is “1”, the write circuit 600 outputs an H-level positive-phase bit signal to the bit line BL and an L-level negative-phase bit signal to the bit line BLB. When the write data is “0”, an L level positive phase bit signal is output to the bit line BL and an H level negative phase bit signal is output to the bit line BLB.
(3) The row decoder 200 shown in FIGS. 1 and 2 sets the row selection voltage WL for the memory cell to the H level, and then returns to the L level. As a result, the potential at the connection point of both drains of the transistors P1 and N1 becomes the potential of the bit line BL, and the potential at the connection point of both drains of the transistors P2 and N2 becomes the potential of the bit line BLB. Maintained in the memory cell.

On the other hand, read access to the memory cell is performed as follows.
(1) The column decoder 300 shown in FIGS. 1 and 2 connects the bit line pair corresponding to the column to which the memory cell belongs to the global bit line pair DL and DLB via the column gate 700.
(2) A precharge circuit (not shown) applies a precharge potential to the global bit line pair DL and DLB and the bit line pair BL and BLB connected to the global bit line pair DL and DLB via the column gate 700.
(3) The row decoder 200 shown in FIGS. 1 and 2 sets the row selection voltage WL for the memory cell to the H level, and turns on the transistors Ta1 and Ta2 of the memory cell. Here, when the memory cell stores “1”, since the transistor N1 is OFF and the transistor N2 is ON, the potentials of the bit line BLB and the global bit line DLB decrease from the precharge potential. To do. On the other hand, when the memory cell stores “0”, since the transistor N1 is ON and the transistor N2 is OFF, the potentials of the bit line BL and the global bit line DL are decreased from the precharge potential. .
(4) The sense amplifier 400 shown in FIGS. 1 and 2 differentially amplifies the potential difference between the global bit lines DL and DLB, thereby outputting a signal Dout corresponding to the data stored in the memory cell.

  In the access operation to the memory cell described above, there are variations in parameters or electrical characteristics of each transistor constituting the memory cell, specifically, threshold voltage Vt, mutual conductance gm, mobility μ, or beta value β of each transistor. Influence. In addition, since both the source and the drain of the transistors Ta1 and Ta2 are not fixed, the variation in the back gate bias characteristics of these transistors affects the access operation to the memory cell.

  Among the characteristics of each part of the SRAM, there is a memory cell SNM that is easily affected by transistor characteristic variations (characteristic variations caused by process parameter variations). FIG. 4 is a diagram illustrating an example of an SNM measurement method. FIGS. 5A to 5D illustrate SNM measurement results. 5A to 5D, the horizontal axis indicates the voltage V0 at the common connection point of the transistors P1 and N1, and the vertical axis indicates the voltage V1 at the common connection point of the transistors P2 and N2.

  In the measurement method illustrated in FIG. 4, in the memory cell shown in FIG. 3, the high potential side power supply voltage VDD of the SRAM is 1.0 V, the voltage of the N well to which the P channel transistors P1 and P2 belong is 1.0 V, and the low potential side The power supply voltage VSS is 0V, the voltage of the P well to which the N channel transistors N1 and N2 belong is 0V, the row selection voltage for the word line WL is the same voltage as the power supply voltage VDD, and the P well to which the N channel transistors Ta1 and Ta2 as transfer gates belong. Measurements 1 and 2 are performed with a voltage of 0V. Here, in measurement 1, the bit line BL is opened, the bit line BLB is fixed to the same voltage as the power supply voltage VDD, and the voltage V0 at the connection point between both drains of the transistors P1 and N1 is changed from 0 V to VDD (in FIG. 4). In the example, the change in the voltage V1 at the common connection point of the transistors P2 and N2 when the voltage is raised to 1.0 V) is observed. The broken lines in FIGS. 5A to 5D show how the voltage V1 changes in accordance with the change in the voltage V0 obtained in the measurement 1. FIG. In measurement 2, the bit line BLB is opened, the bit line BL is fixed to the same voltage as the power supply voltage VDD, and the voltage V1 at the connection point of both drains of the transistors P2 and N2 is changed from 0 V to VDD (example in FIG. 4). The voltage V0 at the common connection point of the transistors P1 and N1 when the voltage is raised to 1.0V) is observed. The solid lines in FIGS. 5A and 5C show how the voltage V0 changes in accordance with the change in the voltage V1 obtained in the measurement 2. FIG.

  In FIGS. 5A to 5D, the dashed curve and the solid curve are each called a butterfly curve. These two butterfly curves cross each other on the way, and the positional relationship between the top and bottom and the left and right is switched. In each of FIGS. 5A to 5D, two squares are drawn that fit in two regions sandwiched between the broken butterfly curve and the solid butterfly curve. The size of this square is the size of the SNM. More specifically, the square between the two butterfly curves in the region where the broken butterfly curve is at the upper right and the solid butterfly curve is at the lower left is a noise that increases the voltage V0 at the connection point of the drains of the transistors P1 and N1. When this occurs, it is an SNM (hereinafter referred to as a first SNM for convenience) indicating an allowable value of the noise level that does not invert the stored contents of the memory cell. The square between the two butterfly curves in the region where the solid butterfly curve is at the upper right and the broken butterfly curve is at the lower left is when noise that raises the voltage V1 at the connection point of the drains of the transistors P2 and N2 occurs. , An SNM (hereinafter referred to as a second SNM for convenience) indicating an allowable value of the noise level that does not invert the stored contents of the memory cell.

  FIGS. 5A and 5C illustrate the SNM characteristics when the power supply voltage VDD of the SRAM is 1.0 V, respectively. In the example shown in FIG. 5 (a), the beta value β and the threshold voltage Vt of each transistor constituting the memory cell are balanced, and the first SNM and the second SNM are approximately the same. Is also large enough. Therefore, in this memory cell, stable write access and read access are possible.

  However, the butterfly curve depends on the balance of the beta values and the threshold voltage of each of the transistors P1, N1, P2, and N2. For example, in FIG. 5A, when the beta ratio βp / βn between the transistor P2 and the beta value βn of the transistor N2 having the beta value βp increases, the broken butterfly curve projects in the upper right direction. Conversely, when the beta ratio βp / βn decreases, the broken butterfly curve retreats in the lower left direction. Further, when the transistor N2 and the threshold voltage Vtn increase and the threshold voltage Vtp of the transistor P2 decreases, the voltage V0 at which the broken butterfly curve rapidly falls increases. Conversely, when the transistor N2 and the threshold voltage Vtn decrease and the threshold voltage Vtp of the transistor P2 increases, the voltage V0 at which the broken butterfly curve suddenly falls decreases.

  Further, in the process of increasing the voltage V0 from 0V to VDD, when the transistor N2 is turned on, a current flows into the transistor N2 via the transistor Ta2. Therefore, the voltage V1 does not fall down to the VSS level (0V), but the VSS level. Float from. If the current flowing through the transistor Ta2 is constant, the floating of the voltage V1 from the VSS level at this time increases as the threshold voltage Vtn of the transistor N2 is higher or the beta value βn of the transistor N2 is lower.

  Thus, the broken butterfly curve is affected by changes in threshold voltages and beta values of the transistors P2 and N2. On the other hand, the solid butterfly curve is mainly affected by changes in the balance of the beta values and the balance of the threshold voltages of the transistors P1 and N1. Thus, since the butterfly curve is affected by changes in the threshold voltage and beta value of each transistor, the first and second SNMs are also affected by changes in the threshold voltage and beta value of each transistor.

  In the example shown in FIG. 5C, an imbalance occurs between the threshold voltage Vt or the beta value of each transistor constituting the memory cell, and the first SNM is sufficiently large, but the second SNM Is slightly smaller.

  As described above, when the characteristics (specifically, the threshold voltage VT and the beta value) of the transistors constituting the memory cell vary, the sizes of the first and second SNMs vary. However, when the power supply voltage VDD of the SRAM is as high as 1.0 V, the degree of influence on the first and second SNMs of the characteristic variation of each transistor constituting the memory cell is relatively small. For this reason, it is relatively easy to suppress the characteristic variation of each transistor constituting the memory cell so that both the first and second SNMs are sufficiently large.

  However, as the power supply voltage VDD of the SRAM decreases, the degree of influence on the first and second SNMs of the characteristic variation of each transistor constituting the memory cell increases. FIGS. 5B and 5D show an example of this. In the example of FIGS. 5B and 5D, the power supply voltage VDD of the SRAM is 0.5V. In the example shown in FIG. 5B, since the power supply voltage VDD is 0.5 V, the first and second SNMs are considerably small, but the characteristics of the transistors constituting the memory cell are balanced. Therefore, the first and second SNMs are sized to enable normal write access and read access. However, in the example shown in FIG. 5D, there is a subtle imbalance in the characteristics of the transistors constituting the memory cell, and the second SNM is almost eliminated due to the influence. As described above, when the operation margin is insufficient, the write access and the read access are hindered.

  Thus, when the power supply voltage VDD of the SRAM decreases, the degree of influence of the transistor characteristic variation on the SNM increases, and the first SNM and the first SNM having a sufficiently large size due to a slight deviation from the ideal state of the transistor characteristics. 2 SNM cannot be obtained, and malfunction is likely to occur. For this reason, conventionally, when the power supply voltage VDD of the SRAM is set to 0.5 V, normal operation can no longer be guaranteed. Each embodiment described below solves this problem.

<First Embodiment>
FIG. 6 is a circuit diagram showing a configuration of the SRAM according to the first embodiment of the present invention. In the SRAM according to the present embodiment, the row selection circuit 200-i (i = 0 to m) in FIG. 2 is replaced with a row selection circuit 260-i (i = 0 to m). These row selection circuits 260-i (i = 0 to m) control the high-potential-side power supply voltage for each row in addition to the function of outputting the row selection voltage WLi (i = 0 to m). Thus, when the row selection voltage WLi for the row to which the memory cell to be accessed belongs is set to the active level, the power supply voltage control means for increasing the power supply voltage for each memory cell belonging to the row more than the power supply voltage for the other row It has the function of.

  More specifically, in all memory cells Mij (i = 0 to m, j = 0 to n), both sources of N channel transistors N1 and N2 (see FIG. 3) and P formed by N channel transistors N1 and N2 are formed. The low-potential-side power supply voltage VSS (VSS = 0 V in this example) is applied to the type semiconductor substrate. Further, in all the memory cells Mij (i = 0 to m, j = 0 to n), the first high potential side power supply voltage VDD is applied to the N well in which the P channel transistors P1 and P2 (see FIG. 3) are formed. It is done. In each row i, both sources of the P channel transistors P1 and P2 of all the memory cells Mij (j = 0 to n) belonging to the row i are connected to the row selection circuit 260-i corresponding to the row i. ing. Each row selection circuit 260-i (i = 0 to m) has a first high-potential-side power supply voltage VDD and a higher second-potential-side power supply voltage VDP as the high-potential-side power supply voltage. At the same time, a low-potential-side power supply voltage VSS (= 0 V) lower than the first high-potential-side power supply voltage VDD is applied. Here, the power supply voltage VDD is 0.5 V, for example, and the power supply voltage VDP is 0.8 V, for example.

  The row selection circuit 260-i corresponding to an arbitrary row i selects the first high potential side power supply voltage VDD or the second high potential side power supply voltage VDP, and the high potential side power supply for each memory cell in the row i. A high potential side power supply switching circuit that outputs the voltage VDDCi is included. When the row address does not indicate row i, the row selection circuit 260-i corresponding to row i sets the row selection voltage WLi for row i to an inactive level (0 V that is the low-potential side power supply voltage VSS), and The high-potential-side power supply voltage VDDCi applied to the sources of the P-channel transistors P1 and P2 of all the memory cells Mij (j = 0 to n) belonging to the row i is supplied to the first high-potential-side power supply voltage VDD by the high-potential-side switching circuit. And On the other hand, when the row address indicates row i, row selection circuit 260-i corresponding to row i sets row selection voltage WLi for row i to an active level, more specifically, to the level of power supply voltage VDP, and During the period when the row selection voltage WLi = VDP is output, the high-potential-side power supply voltage VDDCi applied to the sources (see FIG. 3) of the P-channel transistors P1 and P2 of all the memory cells Mij (j = 0 to n) in the row i. Is set to the second high potential side power supply voltage VDP by the high potential side switching circuit.

  In each memory cell Mij (j = 0 to n) corresponding to row i indicated by the row address, it is interposed between the sources of P channel transistors P1 and P2 and the N well to which P channel transistors P1 and P2 belong. The forward voltage of VDP−VDD = 0.8V−0.5V = 0.3V is applied to the parasitic diode, but if the forward voltage is about this level, the parasitic diode does not turn on, so no problem occurs. If the potential of the N well to which the P channel transistors P1 and P2 belong is set to the second high potential side power supply voltage VDP, 0.3 V is applied to the P channel transistors P1 and P2 of the memory cells belonging to the inactive row. As a result, the off-leakage can be reduced.

  FIG. 7 is a circuit diagram showing a configuration example of the row selection circuit 260-i in the present embodiment. In FIG. 7, the NAND gate 261 outputs an active level signal (L level = VSS = 0V) when the row address indicates a row associated with the row selection circuit 260-i, and is inactive when they do not match. This is an address determination circuit that outputs a level (H level = VDD = 0.5 V) signal. The high-potential side level shifter 262 is a circuit that inverts the logic of the output signal of the NAND gate 261 as the address determination circuit and performs level shift and outputs it, and the low-potential-side power supply voltage VSS is 0 V as the L level. Is set to the H level, and the second high potential side power supply voltage VDP of 0.8 V is output. The output signal of the high potential side level shifter 262 becomes the row selection voltage WL for all the memory cells Mij (i = 0 to m, j = 0 to n) in the row i. The inverter 263 is a circuit that inverts and outputs the logic of the row selection voltage WL output from the high potential side level shifter 262. The inverter 263 outputs 0V as the L level and the second high potential side power supply voltage VDP as the H level. Outputs 8V.

  P channel transistors 264 and 265 constitute a high potential side switching circuit. Here, in the P-channel transistor 264, the first high potential side power supply voltage VDD is applied to the source, and the row selection voltage WL is applied to the gate. Further, the source of the P-channel transistor 265 is connected to the power supply VDP, and the output signal of the inverter 263 is given to the gate. A second high potential side power supply voltage VDP is applied to the N well in which P channel transistors 264 and 265 are formed. P channel transistors 264 and 265 have their drains connected in common. The voltage at the connection point between the drains of the P-channel transistors 264 and 265 becomes the high potential side power supply voltage VDDC for all the memory cells Mij (i = 0 to m, j = 0 to n) in the row i.

  According to this configuration, when the row selection voltage WL is at an inactive level (L level = VSS = 0V), the P-channel transistor 264 is turned on and the P-channel transistor 265 is turned off, and the high potential for all the memory cells in the row i. As the side power supply voltage VDDC, 0.5 V that is the first high potential side power supply voltage VDD is output. On the other hand, when the row selection voltage WL is at the active level (H level = VDP = 0.8 V), the P channel transistor 264 is turned off and the P channel transistor 265 is turned on, and the high potential side for all the memory cells in row i. As the power supply voltage VDDC, 0.8V that is the second high potential side power supply voltage VDP is output.

  FIG. 8 is a circuit diagram showing a configuration example of the high potential side level shifter 262 in FIG. This level shifter 262 includes N channel transistors 266 and 268 and P channel transistors 267 and 269. Here, in the N-channel transistor 266, the low-potential-side power supply voltage VSS is supplied to the source, and the output signal of the NAND gate 261 (address determination circuit) in FIG. 7 is supplied to the gate. The drain of the P-channel transistor 267 is connected to the drain of the N-channel transistor 266, and the second high potential side power supply voltage VDP is applied to the source. A connection point between the drains of the N-channel transistor 266 and the P-channel transistor 267 is a node for outputting the row selection voltage WL. The N-channel transistor 268 has a gate supplied with the first high-potential-side power supply voltage VDD, and serves as a transfer gate that supplies the output signal of the NAND gate 261 (address determination circuit) in FIG. 7 to the gate of the P-channel transistor 267. Function. In the P-channel transistor 269, the second high-potential-side power supply voltage VDP is applied to the source, the drain is connected to the gate of the P-channel transistor 267, and the row selection voltage WL is applied to the gate.

  In this configuration, when the output signal of the NAND gate 261 that is an address determination circuit is at an inactive level (VDD), the N-channel transistor 266 is turned on, so that the P-channel transistor 269 is turned on, and the P-channel transistor 267 is turned on. Turn it off. For this reason, the row selection voltage WL becomes an inactive level (VSS). On the other hand, when the output signal of the NAND gate 261 becomes the active level (VSS), the N-channel transistor 266 is turned OFF and the P-channel transistor 267 is turned ON, and the row selection voltage WL is at the active level, that is, the second high potential side power supply voltage. VDP. Then, when the row selection voltage WL becomes the second high potential side power supply voltage VDP, the P-channel transistor 269 is turned off. As described above, in the level shifter 262 shown in FIG. 8, the logic of the output signal of the NAND gate 261 is inverted and output, and 0 V is output as the L level and VDP = 0.8 V is output as the H level.

FIG. 9 is a circuit diagram showing a configuration of a power supply circuit for generating the second high potential side power supply voltage VDP in the present embodiment. In FIG. 9, a charge pump circuit 51 as a booster circuit boosts and outputs a power supply voltage VDD. The operational amplifier 52a is an operational amplifier that operates using the voltage boosted by the charge pump 51 as a power supply voltage. A reference voltage VREF generated by a reference voltage source such as a band gap reference is applied to the positive phase input terminal of the operational amplifier 52a. In addition, a voltage dividing circuit including resistors R2 and R1 is interposed between the output terminal of the operational amplifier 52a and the low-potential-side power supply VSS (= 0V). Then, the divided output obtained from the common connection point of the resistors R1 and R2 is fed back to the negative phase input terminal of the operational amplifier 52a. According to this configuration, negative feedback control is performed so that the voltage at the common connection point of the resistors R2 and R1 matches the reference voltage VREF, and a boosted voltage of {(R2 + R1) / R1} VREF is obtained from the operational amplifier 52a. This boosted voltage {(R2 + R1) / R1} VREF is used as the second high potential side power supply voltage VDP.
The above is the details of the configuration of the present embodiment.

  According to this embodiment, at the time of write access or read access to a certain memory cell, the row selection voltage WL for the row to which the memory cell belongs is set to WL = VDP, and the power supply voltage ( The power supply voltage VDP is higher than the power supply voltage VDD (power supply voltage between both sources of P channels P1 and P2 and the sources of both N channel transistors N1 and N2) shown in FIG. Therefore, normal write access and read access are possible even in a situation where the power supply voltage VDD applied to the SRAM is low. On the other hand, at the time of write access or read access to a certain memory cell, the power supply voltage VDD is supplied to all memory cells in each row other than the row to which the memory cell to be accessed belongs. Therefore, the memory information is normally held in the memory cells in those rows.

  In the present embodiment, the second high-potential-side power supply voltage VDP is generated by a booster circuit built in the SRAM. However, a dedicated power supply terminal is provided in the SRAM, and a row selection circuit is provided from outside the SRAM via this dedicated power supply terminal. The second high potential side power supply voltage VDP may be supplied to 260-i (i = 0 to m).

Second Embodiment
FIG. 10 is a circuit diagram showing a configuration of an SRAM according to the second embodiment of the present invention. In the SRAM according to the present embodiment, the row selection circuit 200-i (i = 0 to m) in FIG. 2 is replaced with a row selection circuit 270-i (i = 0 to m). These row selection circuits 270-i (i = 0 to m) control the low-potential-side power supply voltage for each row in addition to the function of outputting the row selection voltage WLi (i = 0 to m). Thus, when the row selection voltage WLi for the row to which the memory cell to be accessed belongs is set to the active level, the power supply voltage control means for increasing the power supply voltage for each memory cell belonging to the row more than the power supply voltage for the other row It has the function of.

  More specifically, in all memory cells Mij (i = 0 to m, j = 0 to n), both sources of P channel transistors P1 and P2 (see FIG. 3) and N formed by P channel transistors P1 and P2 are formed. The well is connected to the high potential side power supply VDD = 0.5V. Further, in all memory cells Mij (i = 0 to m, j = 0 to n), the first low-potential-side power supply voltage VSS is applied to the P-type semiconductor substrate on which the N-channel transistors N1 and N2 (see FIG. 3) are formed. Is given. In each row i, both sources of the N channel transistors N1 and N2 of all the memory cells Mij (j = 0 to n) belonging to the row i are connected to a row selection circuit 270-i corresponding to the row i. ing. On the other hand, in each row selection circuit 270-i (i = 0 to m), as the low potential side power supply voltage, the first low potential side power supply voltage VSS and the second low potential side power supply voltage VSP having a potential lower than the first low potential side power supply voltage VSP. And a high potential side power supply voltage VDD = 0.5, which is higher than the first low potential side power supply voltage VSS. Here, the power supply voltage VSS is 0 V, for example, and the power supply voltage VSP is -0.3 V, for example.

  A row selection circuit 270-i corresponding to an arbitrary row i selects the first low-potential-side power supply voltage VSS or the second low-potential-side power supply voltage VSP, and the low-potential-side power supply for each memory cell in the row i. A low-potential-side power supply switching circuit that outputs the voltage VSSCi is included. When the row address does not indicate row i, row selection voltage WLi for row i is set to an inactive level (L level), and N channel transistors of all memory cells Mij (j = 0 to n) belonging to row i The low potential side power supply voltage VSSCi applied to the sources of N1 and N2 is set to the first low potential side power supply voltage VSS by the low potential side power supply switching circuit. On the other hand, when the row address indicates row i, the row selection circuit 260-i corresponding to row i sets the row selection voltage WLi for row i to the active level (H level = VDD) and this row selection voltage. During the period during which WLi = VDD is output, the low-potential-side power supply voltage VSSCi applied to the sources (see FIG. 3) of the N-channel transistors N1 and N2 of all the memory cells Mij (j = 0 to n) belonging to the row i The power supply switching circuit sets the second low potential side power supply voltage VSP.

  In each memory cell Mij (j = 0 to n) corresponding to row i indicated by the row address, between each source of N-channel transistors N1 and N2 and the P-type semiconductor substrate to which N-channel transistors N1 and N2 belong is provided. A forward voltage of VSS−VSP = 0V − (− 0.3V) = 0.3V is applied to the parasitic diode interposed in the capacitor. However, if the forward voltage is about this level, the parasitic diode does not turn on, so no problem occurs. . Further, by adopting a triple well structure, which will be described later, if the P well of the memory cell is separated from the P well of other peripheral circuits (decoders, etc.) and set to the lowest potential VSP, it becomes an inactive row. A back gate voltage of 0.3 V is applied to the N channel transistors N1 and N2 of the memory cell to which the memory cell belongs, and off-leakage can be reduced.

  FIGS. 11A and 11B are circuit diagrams each showing a configuration example of the row selection circuit 270-i in the present embodiment. In the example shown in FIG. 11A, the NAND gate 271 outputs an active level (L level = VSS = 0V) signal when the row address indicates a row associated with the row selection circuit 270-i. The address determination circuit outputs an inactive level (H level = VDD = 0.5 V) signal when they do not match. The inverter 272 is a circuit that inverts and outputs the logic of the output signal of the NAND gate 271 and outputs VSS = 0V as the L level and VDD = 0.5V as the H level. The output signal of the inverter 272 becomes the row selection voltage WL for all the memory cells Mij (i = 0 to m, j = 0 to n) in the row i.

  N-channel transistors 273 and 274 constitute a low-potential side power supply switching circuit. Here, in the N-channel transistor 274, the first low-potential-side power supply voltage VSS is supplied to the source, and the output signal of the NAND gate 271 that is an address determination circuit is supplied to the gate. The N-channel transistor 273 is supplied with the second low-potential-side power supply voltage VSP at the source and the output signal of the inverter 272 at the gate. The N-channel transistors 273 and 274 are formed in a P-well fixed to the second low potential side power supply voltage VSP, and their drains are connected in common. The voltage at the connection point between the drains of the N-channel transistors 273 and 274 is the low-potential-side power supply voltage VSSC for all the memory cells Mij (i = 0 to m, j = 0 to n) in the row i.

  In the SRAM according to the present embodiment, an N well is formed in a P type semiconductor substrate, a P well is formed in the N well, and N channel transistors 273 and 274 are formed in the P well. By adopting this triple well structure, the P well to which N channel transistors 273 and 274 belong can be isolated from the P type semiconductor substrate.

  According to the configuration shown in FIG. 11A, the output signal of the NAND gate 271 becomes inactive level (H level = VDD), and the row selection voltage WL becomes inactive level (L level = VSS = 0V). At this time, the N-channel transistor 274 is turned ON. In this example, the threshold voltages of the N-channel transistors 273 and 274 are higher than 0.3 V, and are turned off when the row selection voltage WL is at an inactive level (L level = VSS = 0 V). Therefore, the power supply voltage VSS = 0V is output as the power supply voltage VSSC for all the memory cells in the row i. On the other hand, when the output signal of the NAND gate 271 becomes active level (L level = VSS = 0V) and the row selection voltage WL becomes active level (H level = VDD = 0.5V), the N-channel transistor 273 Is turned ON and the N-channel transistor 274 is turned OFF, and the power supply voltage VSP = −0.3 V is output as the power supply voltage VSSC for all the memory cells in the row i.

  In the configuration shown in FIG. 11A, since the second low-potential-side power supply voltage VSP = −0.3V is applied to the source of the N-channel transistor 273, the threshold voltage of the N-channel transistor 273 is 0.3V. Is lower than the N channel transistor 273 when the row selection voltage WL is 0V, and the N channel transistor 273 is not OFF when the output signal of the NAND gate 271 which is the address determination circuit becomes 0V. Can occur. In the configuration shown in FIG. 11B, the inverter 271 in FIG. 11A is replaced with a low potential level shifter 275 in order to solve this problem. The low-potential side level shifter 275 is a circuit that inverts the logic of the output signal of the NAND gate 271 and performs level shift to output the high-potential-side power supply voltage VDD as the H level and the second level as the L level. The low potential side power supply voltage VSP is output.

  FIG. 12 is a circuit diagram showing a configuration example of the low potential side level shifter 275 in FIG. The low potential side level shifter 275 includes P-channel transistors 276 and 278 and N-channel transistors 277 and 279. Here, the P-channel transistor 276 is supplied with the high-potential-side power supply voltage VDD at the source and the output signal of the NAND gate 271 (see FIG. 11B) as an address determination circuit at the gate. The N-channel transistor 277 has a drain connected to the drain of the P-channel transistor 276, and a second low-potential-side power supply voltage VSP is applied to the source. The connection point between the drains of the P-channel transistor 276 and the P-channel transistor 277 is a node for outputting the output signal OUT of the low-potential side level shifter 275, and is connected to the gate of the P-channel transistor 273 in FIG. Is done. In the P-channel transistor 278, the first low-potential-side power supply voltage VSS is applied to the gate, and the output signal of the NAND gate 271 (see FIG. 11B) which is an address determination circuit is supplied to the gate of the N-channel transistor 277. Functions as a transfer gate to supply. In the N-channel transistor 279, the drain is connected to the gate of the N-channel transistor 277, the second low-potential-side power supply voltage VSP is applied to the source, and the output signal OUT of the low-potential-side level shifter 275 is applied to the gate.

In this configuration, when the output signal of the NAND gate 271 is at the inactive level (VDD), the P-channel transistor 276 is turned OFF and the N-channel transistor 277 is turned ON, and the output signal OUT becomes VSP = −0.3V. Further, since the output signal OUT becomes VSP, the N-channel transistor 279 is turned off. On the other hand, when the output signal of the NAND gate 271 becomes the active level (VSS), the P-channel transistor 276 is turned on, so that the N-channel transistor 279 is turned on and the N-channel transistor 277 is turned off. As a result, the output signal OUT becomes VDD. As described above, in the level shifter 275 shown in FIG. 12, the logic of the output signal of the NAND gate 271 is inverted and output, and the second low-potential-side power supply voltage VSP = −0.3 V is set to the L level and set to the H level. The high potential side power supply voltage VDD = 0.5V is output.
The above is the details of the configuration of the present embodiment.

  According to the present embodiment, at the time of write access or read access to a certain memory cell, the row selection voltage WL for the row to which the memory cell belongs is set to WL = VDD, and the low potential side for all the memory cells in that row The power supply voltage is set to a power supply VSP = −0.3V lower than the power supply voltage VSS = 0V, and the power supply is provided between both sources of the P-channels P1 and P2 and both sources of the N-channel transistors N1 and N2 of the memory cell in the row. The voltage VDD−VSP = 0.5V − (− 0.3V) = 0.8V is supplied. Therefore, normal write access and read access are possible even in a situation where the power supply voltage VDD-VSS applied to the SRAM is low. On the other hand, at the time of write access or read access to a certain memory cell, the normal power supply voltage VDD-VSS = 0.5 V is supplied to all memory cells in each row other than the row to which the memory cell to be accessed belongs. . Therefore, the memory information is normally held in the memory cells in those rows.

  In the present embodiment, the second low-potential-side power supply voltage VSP may be generated by a booster circuit built in the SRAM, and the row selection circuit 270-i (i) from the outside of the SRAM via a dedicated power supply terminal. = 0 to m). 11B is an inverter that inverts the logic of the output signal of the level shifter 276 and outputs the inverted signal. The second low-potential-side power supply voltage VSP is set to the H level and the high potential is set to the L level. An inverter that outputs the side power supply voltage VDD may be provided, and the output signal of this inverter may be applied to the gate of the N-channel transistor 274 instead of the output signal of the NAND gate 271.

<Third Embodiment>
FIG. 13 is a circuit diagram showing a configuration of an SRAM according to the third embodiment of the present invention. In the SRAM according to the present embodiment, the row selection circuit 200-i (i = 0 to m) in FIG. 2 is replaced with a row selection circuit 280-i (i = 0 to m). These row selection circuits 280-i (i = 0 to m) output the row selection voltage WLi (i = 0 to m), and, for each row, the high potential side power supply voltage and the low potential side for each row. By controlling the power supply voltage, when the row selection voltage WLi for the row to which the memory cell to be accessed belongs is set to the active level, the power supply voltage for each memory cell belonging to the row is increased from the power supply voltage for the other rows. It has a function as power supply voltage control means.

  More specifically, in all memory cells Mij (i = 0 to m, j = 0 to n), an N well in which P channel transistors P1 and P2 (see FIG. 3) are formed has a first high potential side power supply VDD. Is given. Further, in all memory cells Mij (i = 0 to m, j = 0 to n), the first low-potential-side power supply voltage VSS is applied to the P-type semiconductor substrate on which the N-channel transistors N1 and N2 (see FIG. 3) are formed. Is given. In each row i, the sources of P channel transistors P1 and P2 and the sources of N channel transistors N1 and N2 of all memory cells Mij (j = 0 to n) belonging to row i are placed in row i. It is connected to the corresponding row selection circuit 270-i. On the other hand, each row selection circuit 270-i (i = 0 to m) has a first high-potential-side power supply voltage VDD and a second high-potential-side power supply voltage VDP having a higher potential as the high-potential-side power supply voltage. , And the first low-potential-side power supply voltage VSS and the second low-potential-side power supply voltage VSP having a lower potential than the first low-potential-side power supply voltage VSS. Here, the first high potential side power supply voltage VDD is, for example, 0.5V, the second high potential side power supply voltage VDP is, for example, 0.8V, the first low potential side power supply voltage VSS is, for example, 0V, and the second low potential side power supply voltage VSS is, for example, 0V. The potential side power supply voltage VSP is, for example, −0.3V.

  The row selection circuit 280-i corresponding to an arbitrary row i selects the first high potential side power supply voltage VDD or the second high potential side power supply voltage VDP, and the high potential side power supply for each memory cell in the row i. The high potential side power supply switching circuit that outputs the voltage VDDCi and the first low potential side power supply voltage VSS or the second low potential side power supply voltage VSP are selected, and the low potential side power supply voltage VSSCi for each memory cell in the row i is selected. And a low potential side power supply switching circuit.

  When the row address does not indicate row i, row selection circuit 280-i corresponding to row i sets row selection voltage WLi for row i to an inactive level (L level = VSS) and belongs to row i. The high-potential-side power supply voltage VDDCi applied to the sources of the P-channel transistors P1 and P2 of all memory cells Mij (j = 0 to n) is changed to the second high-potential-side power supply voltage VDD by the high-potential-side power supply switching circuit. The low potential power supply voltage VSSCi applied to the sources of the transistors N1 and N2 is set to the first low potential power supply voltage VSS by the low potential power supply switching circuit.

  On the other hand, when the row address indicates row i, the row selection circuit 280-i corresponding to row i sets the row selection voltage WLi for row i to the active level (H level), more specifically, the power supply voltage VDP. The high-potential-side power supply voltage VDDCi applied to the sources of the P-channel transistors P1 and P2 of all memory cells Mij (j = 0 to n) belonging to the row i during the period when the row selection voltage WLi = VDP is output. Is set to the second high potential side power supply voltage VDP by the high potential side power supply switching circuit, and the low potential side power supply voltage VSSCi applied to the sources of the N-channel transistors N1 and N2 (see FIG. 3) is 2 is a low-potential-side power supply voltage VSP.

  In each memory cell Mij (j = 0 to n) corresponding to row i indicated by the row address, it is interposed between the sources of P channel transistors P1 and P2 and the N well to which P channel transistors P1 and P2 belong. The forward voltage of VDP−VDD = 0.8V−0.5V = 0.3V is applied to the parasitic diode, but if the forward voltage is about this level, the parasitic diode does not turn on, so no problem occurs. Further, VSS-VSP = 0V-(-0.3V) = 0.3V is applied to a parasitic diode interposed between the sources of the N-channel transistors N1 and N2 and the P-type semiconductor substrate to which the N-channel transistors N1 and N2 belong. However, if the forward voltage is about this level, the parasitic diode does not turn on, and no problem occurs. As described above, if the N well of the memory cell is VDP and the P well is VSP, the P channel transistors P1 and P2 and the N channel transistors N1 and N2 of the memory cell belonging to the inactive row have 0 A back gate voltage of .3 V is applied, and off-leakage can be reduced.

  FIG. 14 is a circuit diagram showing a configuration example of the row selection circuit 280-i in the present embodiment. In FIG. 14, a NAND gate 281 outputs a signal of an active level (L level = VSS = 0V) when the row address indicates a row associated with the row selection circuit 280-i, and is not otherwise. This is an address determination circuit that outputs a signal of an active level (H level = VDD = 0.5 V). The level shifter 282 is a circuit that inverts the logic of the output signal of the NAND gate 282 that is the address determination circuit and performs level shift and outputs it, and the second low potential side power supply voltage VSP = −0 as the L level. The second high potential side power supply voltage VDP = 0.8 V is output with 3 V as the H level. The output signal of the level shifter 282 becomes the row selection voltage WL for all the memory cells Mij (j = 0 to n) in the row i. The inverter 283 is a circuit that inverts and outputs the logic of the output signal of the level shifter 282. The L level is the second low potential side power supply voltage VSP = −0.3V, and the H level is the second high potential side power source. The voltage VDP = 0.8V is output.

  P-channel transistors 284 and 285 constitute a high potential side power supply switching circuit. Here, in the P-channel transistor 284, the first high-potential-side power supply voltage VDD is supplied to the source, and the output signal of the level shifter 282 is supplied to the gate. In addition, the P-channel transistor 285 is supplied with the second high potential side power supply voltage VDP at the source and the output signal of the inverter 283 at the gate. The second high potential side power supply voltage VDP is applied to the N well in which these P channel transistors 284 and 285 are formed. The drains of the P channel transistors 284 and 285 are connected in common, and the voltage at the common connection point is the high potential side power supply for all the memory cells Mij (i = 0 to m, j = 0 to n) in the row i. The voltage becomes VDDC. N-channel transistors 286 and 287 constitute a low potential side power supply switching circuit. Here, in the N-channel transistor 287, the first low-potential-side power supply voltage VSS is supplied to the source, and the output signal of the NAND gate 281 that is an address determination circuit is supplied to the gate. The N-channel transistor 286 is supplied with the second low-potential-side power supply voltage VSP at the source and the output signal of the level shifter 282 at the gate.

  Also in the present embodiment, a triple well structure is adopted as in the second embodiment, and the N-channel transistors 286 and 287 are formed in a P well fixed to the second low potential side power supply voltage VSP. Yes. The drains of the N-channel transistors 286 and 287 are connected in common, and the voltage at this common connection point becomes the low potential side power supply voltage VSSC for all the memory cells Mij (j = 0 to n) in the row i.

  According to the configuration shown in FIG. 14, when the output signal of the NAND gate 281 serving as the address determination circuit becomes an inactive level (H level = VDD), the row selection voltage WL is changed to the second low potential side power supply voltage VSP (= − 0.3V), the output signal of the inverter 283 becomes the second high potential side power supply voltage VDP (= 0.8V). Therefore, the P-channel transistor 284 is turned ON and the P-channel transistor 285 is turned OFF, and the first high-potential-side power supply voltage VDD = 0.5 V is output as the high-potential-side power supply voltage VDDC for all the memory cells in the row i. Is done. Further, the N-channel transistor 287 is turned ON and the N-channel transistor 286 is turned OFF, and the first low-potential-side power supply voltage VSS = 0V is output as the low-potential-side power supply voltage VSSC to all the memory cells in the row i. On the other hand, when the output signal of the NAND gate 281 serving as the address determination circuit becomes an active level (L level = VSS = 0V), the row selection voltage WL is set to the second high potential side power supply voltage VDP (= 0.8V), The output signal of the inverter 283 becomes the second low potential side power supply voltage VSP (= −0.3 V). Therefore, the P-channel transistor 284 is turned OFF and the P-channel transistor 285 is turned ON, and the second high-potential-side power supply voltage VDP = 0.8 V is output as the high-potential-side power supply voltage VDDC for all the memory cells in row i. Is done. Further, the N-channel transistor 287 is turned OFF and the N-channel transistor 286 is turned ON, and the second low-potential-side power supply voltage VSP = −0.3 V is output as the low-potential-side power supply voltage VSSC for all the memory cells in the row i. Is done.

  FIG. 15 is a circuit diagram showing a configuration example of the level shifter 282 in FIG. The level shifter 282 includes P channel transistors 291, 294 and 296 and N channel transistors 292, 293 and 295. Here, the P-channel transistor 294 is supplied with the second high-potential-side power supply voltage VDP at the source. The N-channel transistor 293 is supplied with the second low-potential-side power supply voltage VSP at the source. A connection point between the drains of the P-channel transistor 294 and the N-channel transistor 293 is a node that outputs the output signal OUT (that is, the row selection voltage WL) of the level shifter 282. In the P-channel transistor 296, the drain is connected to the gate of the P-channel transistor 294, the second high potential side power supply voltage VDP is applied to the source, and the output signal OUT of the level shifter 282 is applied to the gate. In the N-channel transistor 295, the drain is connected to the gate of the N-channel transistor 293, the second low-potential-side power supply voltage VSP is applied to the source, and the output signal OUT of the level shifter 282 is applied to the gate. The N-channel transistor 292 is supplied with the first high-potential-side power supply voltage VDD at its gate, and transfers the output signal of the NAND gate 281 (see FIG. 14), which is an address determination circuit, to the gate of the P-channel transistor 294. Acts as a gate. The P-channel transistor 291 is supplied with the first low-potential-side power supply voltage VSS at its gate, and supplies the output signal of the NAND gate 281 (see FIG. 14), which is an address determination circuit, to the gate of the N-channel transistor 293. Functions as a transfer gate.

In this configuration, when the output signal of the NAND gate 281 that is an address determination circuit is at an inactive level (VDD), the N-channel transistor 293 is turned on, so that the P-channel transistor 296 is turned on and the P-channel transistor 294 is turned off. Thus, the N-channel transistor 295 is turned off. As a result, the output signal OUT becomes VSP. Further, when the output signal of the NAND gate 281 is at the active level (VSS), the P-channel transistor 294 is turned on, so that the P-channel transistor 296 is turned off, the N-channel transistor 295 is turned on, and the N-channel transistor 293 is turned off. Become. As a result, the output signal OUT becomes VDP. As described above, in the level shifter 282 shown in FIG. 15, the logic of the output signal of the NAND gate 281 is inverted and output, and the second low-potential-side power supply voltage VSP = −0.3 V is set to the L level and the H level is set. The second high potential side power supply voltage VDP = 0.8V is output.
The above is the details of the configuration of the present embodiment.

  According to the present embodiment, at the time of write access or read access to a memory cell, the row selection voltage WL for the row to which the memory cell belongs is set to the second high potential side power supply voltage VDP, and all the rows The high-potential-side power supply voltage for the memory cell is the second high-potential-side power supply voltage VDP = 0.8 V, and the low-potential-side power supply voltage for all the memory cells in the row is the second low-potential-side power supply voltage VSP = −0.3V, and the power supply voltage VDP−VSP = 0.8V − (− 0.3V) between the sources of the P-channels P1 and P2 and the sources of the N-channel transistors N1 and N2 of the memory cell in the row ) = 1.1V is supplied. Therefore, normal write access and read access are possible even in a situation where the power supply voltage VDD-VSS applied to the SRAM is low.

  On the other hand, at the time of write access or read access to a certain memory cell, the normal power supply voltage VDD-VSS = 0.5 V is supplied to all memory cells in each row other than the row to which the memory cell to be accessed belongs. . Therefore, the memory information is normally held in the memory cells in those rows. Further, the second low potential side power supply voltage VSP = −0.3 is supplied as the row selection voltage WL to all the memory cells in each row other than the row to which the memory cell to be accessed belongs. Therefore, in these memory cells, the N-channel transistors Ta1 and Ta2 which are transfer gates are surely turned off, and the information holding operation is stabilized.

  In the present embodiment, the second high-potential-side power supply voltage VDP and the second low-potential-side power supply voltage VSP may be generated by a booster circuit built in the SRAM, and each is a dedicated power supply terminal from outside the SRAM. May be supplied to the row selection circuit 280-i (i = 0 to m). In the row selection circuit shown in FIG. 14, the output signal of the inverter 283 may be supplied to the gate of the N-channel transistor 287 instead of the output signal of the NAND gate 281.

Although the first to third embodiments of the present invention have been described above, other embodiments are conceivable for the present invention. For example:
(1) In the first and third embodiments, the N wells to which the P channel transistors P1 and P2 of the memory cell belong are separated between the rows, and all the memory cells in the row having the row selection voltage WL as the active level (VDP) The high potential side power supply voltage VDDC applied to both sources of the P channel transistors P1 and P2 may be set to VDP, and the potential of the N well to which the P channel transistors P1 and P2 in that row belong may be set to VDP.
(2) In the row selection circuit of FIG. 7, the output voltage VDDC of the row selection circuit may be supplied to the high potential side level shifter 262 as the high potential side power supply voltage instead of the second high potential side power supply voltage VDP.
(3) In the row selection circuit of FIG. 11B, the output voltage VSSSC of the row selection circuit is supplied to the low potential side level shifter 275 as the low potential side power supply voltage instead of the second low potential side power supply voltage VDP. Also good.

100... SRAM cell array, 200... Row decoder, 200-i (i = 0 to m), 260-i (i = 0 to m), 270-i (i = 0 to m), 280-i (i = 0 to m) ... row selection circuit, 300 ... column decoder, 300-j (j = 0 to n) ... column selection circuit, 400 ... sense amplifier, 500 ... input / output buffer, 600 ... write Embedded circuit, 700 ... column gate, 800 ... address input circuit, 900 ... control circuit, 100-0 to 100-n ... data storage area, Mij (i = 0 to m, j = 0 to n) ... ... Memory cells, CGj (j = 0 to n), CGjB (j = 0 to n) ... Switches, BITj (j = 0 to n), BITjB (j = 0 to n), BL, BLB ... Bit lines DL, DLB... Global bit lines 201, 261, 271, 81 ...... NAND gate, 262,275,282 ...... level shifter, 263,272,283 ...... inverter, 264,265,284,285 ...... P-channel transistor, 273,274,286,287 ...... N-channel transistor.

Claims (13)

A cell array having memory cells arranged in a matrix, the row selection voltage associated with the row to which the memory cell to be accessed belongs is set to an active level, and the memory cell belonging to the row is connected to a bit line; In a semiconductor memory that accesses a memory cell to be accessed through a bit line,
A plurality of row selection circuits provided for each row of the matrix of memory cells, each of which outputs a row selection voltage for each memory cell of the row;
Each of the plurality of row selection circuits provided for each row is
The first high-potential-side power supply voltage or the second high-potential-side power-supply voltage having a higher potential than the first high-potential-side power supply voltage is selected and output as the high-potential-side power supply voltage for each memory cell in the row. A high potential side power supply switching circuit;
As a signal indicating whether or not a row address specifying a memory cell to be accessed indicates the row, the first high-potential-side power supply voltage or a potential that is a predetermined voltage or higher than the first high-potential-side power supply voltage An address determination circuit that outputs a signal of the same level as any of the low-potential-side power supply voltages;
A level shifter for performing a level shift of an output signal of the address determination circuit and outputting as a signal having the same level as the low-potential-side power supply voltage or the second high-potential-side power supply voltage;
When the address determination circuit outputs a signal indicating that the row address specifying the memory cell to be accessed does not indicate the row, the high-potential-side power supply switching circuit receives the signal based on the output signal of the high-potential-side level shifter. When the address determination circuit outputs a signal indicating that the row address specifying the memory cell to be accessed indicates the row, by selecting the first high potential side power supply voltage, the output signal of the high potential side level shifter The semiconductor memory according to claim 1, wherein the second high potential side power supply voltage is selected by the high potential side power supply switching circuit. In the high potential side power supply switching circuit, the drain is connected to the output terminal of the high potential side power supply switching circuit, the first high potential side power supply voltage is applied to the source, and the first high potential side power supply switching circuit is ON when the first high potential side power supply switching circuit is ON. A first P-channel field effect transistor that outputs a potential-side power supply voltage from a drain; a drain connected to an output terminal of the high-potential-side power supply switching circuit; and a second high-potential-side power supply voltage applied to a source; A second P-channel field effect transistor that outputs the second high-potential power supply voltage from the drain when ON,
When the address determination circuit outputs a signal indicating that a row address specifying a memory cell to be accessed does not indicate the row, the first P-channel field effect transistor is based on the output signal of the high potential side level shifter A gate voltage having the same level as the low-potential side power supply voltage is applied to the second P-channel field effect transistor, and a gate voltage having the same level as the second high-potential side power supply voltage is applied to the memory to be accessed. When the address determination circuit outputs a signal indicating that a row address specifying a cell indicates the row, the second P-channel field effect transistor receives the second high-level signal based on the output signal of the high-potential side level shifter. A gate voltage of the same level as the potential side power supply voltage is applied, and the low power is supplied to the second P-channel field effect transistor. The semiconductor memory according to claim 1, characterized in that it has to give a gate voltage side power supply voltage of the same level. The high potential side level shifter is
A third N-channel field effect transistor in which the low-potential-side power supply voltage is applied to the source and the output signal of the address determination circuit is applied to the gate;
The second high potential side power supply voltage is applied to the source, the drain is connected to the drain of the third N-channel field effect transistor, and the output signal of the high potential side level shifter is generated from the connection point between the drains. A third P-channel field effect transistor;
A fourth P-channel in which the second high-potential-side power supply voltage is applied to the source, a drain is connected to the gate of the third P-channel field effect transistor, and an output signal of the high-potential-side level shifter is applied to the gate A field effect transistor;
A fourth N-channel field effect transistor functioning as a transfer gate for supplying an output signal of the address determination circuit to a gate of the third P-channel field effect transistor;
The semiconductor memory according to claim 1, further comprising: A cell array having memory cells arranged in a matrix, the row selection voltage associated with the row to which the memory cell to be accessed belongs is set to an active level, and the memory cell belonging to the row is connected to a bit line; In a semiconductor memory that accesses a memory cell to be accessed through a bit line,
A plurality of row selection circuits provided for each row of the matrix of memory cells, each of which outputs a row selection voltage for each memory cell of the row;
Each of the plurality of row selection circuits provided for each row is
The first low-potential side power supply voltage or the second low-potential-side power supply voltage having a lower potential than the first low-potential-side power supply voltage is selected and output as the low-potential-side power supply voltage for each memory cell in the row. A low potential side power supply switching circuit;
As a signal indicating whether or not a row address specifying a memory cell to be accessed indicates the row, a high-potential-side power supply voltage having a potential higher than a predetermined voltage by the first low-potential-side power supply voltage or the first An address determination circuit that outputs a signal of the same level as any of the low-potential-side power supply voltages of
A level shifter that performs a level shift of the output signal of the address determination circuit and outputs as a signal having the same level as the high potential power supply voltage or the second low potential power supply voltage;
When the address determination circuit outputs a signal indicating that the row address specifying the memory cell to be accessed does not indicate the row, the low-potential-side power supply is based on the output signal of the address determination circuit or the low-potential-side level shifter When the switching circuit selects the first low-potential-side power supply voltage and the address determination circuit outputs a signal indicating that a row address specifying a memory cell to be accessed indicates the row, the address determination circuit or A semiconductor memory characterized in that the low potential side power supply switching circuit is made to select the second low potential side power supply voltage based on an output signal of a low potential side level shifter. In the low potential side power supply switching circuit, the drain is connected to the output terminal of the low potential side power supply switching circuit, the first low potential side power supply voltage is applied to the source, and the first low potential side power supply switching circuit is turned on when the source is ON. A first N-channel field effect transistor that outputs a potential-side power supply voltage from the drain; a drain connected to the output terminal of the low-potential-side power supply switching circuit; and the second low-potential-side power supply voltage applied to the source. A second N-channel field effect transistor that outputs the second low-potential-side power supply voltage from the drain when ON,
When the address determination circuit outputs a signal indicating that the row address specifying the memory cell to be accessed does not indicate the row, the first N-th signal is output based on the output signal of the address determination circuit or the low potential level shifter. A gate voltage having the same level as the high potential side power supply voltage is applied to the channel field effect transistor, and a gate voltage having the same level as the second low potential side power supply voltage is applied to the second N channel field effect transistor. When the address determination circuit outputs a signal indicating that a row address specifying a target memory cell indicates the row, the first N-channel field effect is generated based on the output signal of the address determination circuit or the lower level shifter. A gate voltage having the same level as the first low-potential power supply voltage is applied to the transistor, and the second The semiconductor memory according to claim 4, characterized in that it has to give a gate voltage of the high potential power supply voltage and the same level in the N-channel field effect transistor. The low potential side level shifter is
A fifth P-channel field effect transistor in which the high-potential-side power supply voltage is applied to the source and the output signal of the address determination circuit is applied to the gate;
The second low-potential side power supply voltage is applied to the source, the drain is connected to the drain of the fifth P-channel field effect transistor, and the output signal of the low-potential side level shifter is generated from the connection point between the drains. A fifth N-channel field effect transistor;
A sixth N-channel in which the second low-potential-side power supply voltage is applied to the source, the drain is connected to the gate of the fifth N-channel field effect transistor, and the output signal of the low-potential-side level shifter is applied to the gate A field effect transistor;
A sixth P-channel field effect transistor functioning as a transfer gate for supplying an output signal of the address determination circuit to a gate of the fifth N-channel field effect transistor;
The semiconductor memory according to claim 4, further comprising: A cell array having memory cells arranged in a matrix, the row selection voltage associated with the row to which the memory cell to be accessed belongs is set to an active level, and the memory cell belonging to the row is connected to a bit line; In a semiconductor memory that accesses a memory cell to be accessed through a bit line,
A plurality of row selection circuits provided for each row of the matrix of memory cells, each of which outputs a row selection voltage for each memory cell of the row;
Each of the plurality of row selection circuits provided for each row is
The first high-potential-side power supply voltage or the second high-potential-side power-supply voltage having a higher potential than the first high-potential-side power supply voltage is selected and output as the high-potential-side power supply voltage for each memory cell in the row. A high potential side power supply switching circuit;
The first low-potential side power supply voltage or the second low-potential-side power supply voltage having a lower potential than the first low-potential-side power supply voltage is selected and output as the low-potential-side power supply voltage for each memory cell in the row. A low potential side power supply switching circuit;
A signal having the same level as either the first high-potential-side power supply voltage or the first low-potential-side power supply voltage as a signal indicating whether or not a row address specifying a memory cell to be accessed indicates the row An address determination circuit for outputting
A level shifter that performs a level shift of an output signal of the address determination circuit and outputs a signal having the same level as the second high potential power supply voltage or the second low potential power supply voltage;
When the address determination circuit outputs a signal that the row address specifying the memory cell to be accessed does not indicate the row, the high-potential-side power supply switching circuit is based on the output signal of the address determination circuit or the level shifter. The first high-potential-side power supply voltage is selected, and the low-potential-side power supply switching circuit is selected to select the first low-potential-side power supply voltage. A row address for specifying a memory cell to be accessed is When the address determination circuit outputs a signal indicating that the second high-potential-side power supply voltage is selected by the high-potential-side power supply switching circuit based on the output signal of the address determination circuit or the level shifter, A semiconductor memory characterized in that a potential-side power supply switching circuit is made to select the second low-potential-side power supply voltage. In the high potential side power supply switching circuit, the drain is connected to the output terminal of the high potential side power supply switching circuit, the first high potential side power supply voltage is applied to the source, and the first high potential side power supply switching circuit is ON when the first high potential side power supply switching circuit is ON. A first P-channel field effect transistor that outputs a potential-side power supply voltage from a drain; a drain connected to an output terminal of the high-potential-side power supply switching circuit; and a second high-potential-side power supply voltage applied to a source; A second P-channel field effect transistor that outputs the second high-potential power supply voltage from the drain when ON,
In the low potential side power supply switching circuit, the drain is connected to the output terminal of the low potential side power supply switching circuit, the first low potential side power supply voltage is applied to the source, and the first low potential side power supply switching circuit is turned on when the source is ON. A first N-channel field effect transistor that outputs a potential-side power supply voltage from the drain; a drain connected to the output terminal of the low-potential-side power supply switching circuit; and the second low-potential-side power supply voltage applied to the source. A second N-channel field effect transistor that outputs the second low-potential-side power supply voltage from the drain when ON,
When the address determination circuit outputs a signal indicating that a row address specifying a memory cell to be accessed does not indicate the row, the first P-channel field effect is generated based on the output signal of the address determination circuit or the level shifter. A gate voltage having the same level as the second low-potential side power supply voltage is applied to the transistor, a gate voltage having the same level as the second high-potential side power supply voltage is applied to the second P-channel field effect transistor, and the second A gate voltage having the same level as the first high-potential side power supply voltage is applied to one N-channel field effect transistor, and the same level as the second low-potential side power supply voltage is applied to the second N-channel field effect transistor. The address determination circuit outputs a signal indicating that the row address specifying the memory cell to be accessed indicates the row. A gate voltage having the same level as the second high-potential-side power supply voltage is applied to the first P-channel field effect transistor based on the output signal of the address determination circuit or the level shifter. A gate voltage having the same level as the second low potential side power supply voltage is applied to the effect transistor, a gate voltage having the same level as the first low potential side power supply voltage is applied to the first N-channel field effect transistor, and 8. The semiconductor memory according to claim 7, wherein a gate voltage of the same level as the second high potential side power supply voltage is applied to the second N-channel field effect transistor. The level shifter is
A seventh P-channel field effect transistor in which the second high-potential-side power supply voltage is applied to the source;
The second low-potential-side power supply voltage is applied to the source, the drain is connected to the drain of the seventh P-channel field effect transistor, and the output signal of the level shifter is generated from the connection point of the drains. An N-channel field effect transistor;
An eighth P-channel field effect transistor in which the second high-potential side power supply voltage is applied to the source, the drain is connected to the gate of the seventh P-channel field effect transistor, and the output signal of the level shifter is applied to the gate When,
An eighth N-channel field effect transistor in which the second low-potential power supply voltage is applied to the source, the drain is connected to the gate of the seventh N-channel field effect transistor, and the output signal of the level shifter is applied to the gate When,
A ninth N-channel field effect transistor functioning as a transfer gate for supplying an output signal of the address determination circuit to a gate of the seventh P-channel field effect transistor;
A ninth P-channel field effect transistor functioning as a transfer gate for supplying an output signal of the address determination circuit to a gate of the seventh N-channel field effect transistor;
The semiconductor memory according to claim 7, further comprising: 4. The semiconductor memory according to claim 1, wherein the second high-potential side power supply voltage is supplied from outside the semiconductor memory. 7. The semiconductor memory according to claim 4, wherein the second low potential side power supply voltage is supplied from outside the semiconductor memory. 4. The semiconductor memory according to claim 1, further comprising a booster circuit that generates the second high potential side power supply voltage. 7. The semiconductor memory according to claim 4, further comprising a booster circuit that generates the second low potential side power supply voltage.

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