JP2008262613A - Nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve such a problem that increment of a rewriting time and deterioration of reliability are caused by occurrence of variation of rewriting speed in accordance with a position of a memory cell in a nonvolatile memory cell array. <P>SOLUTION: When reduction of drain voltage is caused in the center of a memory cell array 101 due to voltage drop in bit lines B0 to B4, a voltage correcting circuit 102 correcting gate voltage applied to the memory cells 103a, 103b in accordance with a position of a memory cell is arranged between the memory cell array 101 and a word line driving circuit 104. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device such as a flash memory, and more particularly to a nonvolatile semiconductor memory device in which variation in rewrite speed is reduced when data is rewritten in a memory cell.

  In general, a flash memory has a nonvolatile memory cell including a gate electrode connected to a word line, a drain connected to a bit line, a source connected to the source line, and a floating gate or a charge trap layer. The memory cell array includes a plurality of nonvolatile memory cells arranged in a matrix.

For example, in a nonvolatile memory having a trap layer, a discrete trap layer (SiN film or SiN film / top SiO ₂ film interface) existing in an insulating film (SiO ₂ ) between the channel region of the memory cell and the gate electrode The charge is trapped by injecting charges (electrons or holes) into the transition region), and data “0” or “1” is determined by the memory cell threshold voltage, and information is stored.

  In the following description, electron injection is assumed to be writing (program) and hole injection is assumed to be erasure. Note that “rewriting” in the present application includes writing and erasing.

  FIG. 8 is a cross-sectional structure diagram of a nonvolatile memory having a trap layer with the horizontal axis as the channel direction. The configuration and operation of a conventional nonvolatile memory having a trap layer will be described with reference to FIG.

  In FIG. 8, 801 is a semiconductor substrate made of P-type silicon, 802 is a P-type channel region provided on the semiconductor substrate 801, and 803 is an N-type semiconductor provided on the semiconductor substrate 801 on one side of the channel region 802. 804 is a second impurity region (for example, source) made of an N-type semiconductor provided on the semiconductor substrate 801 on one side of the channel region 802, and 807 is on the semiconductor substrate 801. A bottom insulating film made of a silicon oxide film provided on the bottom insulating film 806, a trap layer made of a silicon oxynitride film provided on the bottom insulating film 807, and 805 from a silicon oxide film provided on the trap layer 806. A top insulating film 808 is a gate electrode made of N-type polysilicon provided on the top insulating film 805.

  At the time of writing, about 9 V is applied to the gate electrode 808, about 5 V is applied to the first impurity region (drain) 803, about 1 V is applied to the second impurity region (source) 804, and 0 V is applied to the semiconductor substrate 801. As a result, some of the electrons traveling from the second impurity region 804 toward the first impurity region 803 become hot due to a high electric field in the vicinity of the first impurity region 803, and are locally injected into the trap layer 806. The threshold voltage is in a high state.

  At the time of erasing, about -3V is applied to the gate electrode 808, about 5V is applied to the first impurity region (drain) 803, and 0V is applied to the semiconductor substrate 801, and the second impurity region (source) 804 is brought into a floating state. As a result, a part of the holes generated by the band-to-band tunnel in the first impurity region 803 becomes hot due to a high electric field in the vicinity of the first impurity region 803, and is locally injected into the trap layer 806, and the memory cell threshold voltage Becomes low.

  At the time of reading, about 4 V is applied to the gate electrode 808, 0 V is applied to the first impurity region (drain) 803, about 1.5 V is applied to the second impurity region (source) 804, and 0 V is applied to the semiconductor substrate 801. As a result, data “0” or “1” is obtained depending on the presence or absence of charge in the trap layer 806.

  However, in recent years, the area of the memory cell array has increased with the increase in capacity of the flash memory, and the length of the bit lines provided in the memory cell array has also increased accordingly. Therefore, the voltage drop in the bit line caused by the current flowing through the memory cell during rewriting is also increasing.

  In particular, those using impurity regions as bit lines and source lines in order to reduce the cell area generally have a large resistance value and increase in voltage drop compared to metal wiring. In order to prevent this, increasing the backing of the metal wiring requires a contact, which increases the area. For this reason, in all the memory cells in the memory cell array, the level of the drain voltage at the time of rewriting varies depending on the position of the memory cell in the memory cell array, causing a problem that the rewriting speed varies.

To solve this problem, according to a certain prior art, the level of the bit line voltage supplied to the bit line in the memory cell array at the time of writing is changed according to the write address (see Patent Document 1).
JP 2003-109389 A

  However, in the above prior art, there is a difficulty that voltage application must be controlled according to the address.

  In particular, in the flash memory, since erasing is performed in a certain block unit, the above prior art cannot be applied at the time of erasing. If the erasing speed differs depending on the position of the memory cell in the memory cell array during erasing, the cell having a small voltage drop is applied with excessive stress for erasing the cell having a large voltage drop even though it has already been erased. Erasing will be performed. This stress is called over-erasing. For example, in the above-described nonvolatile memory, excessive holes are injected into the trap layer. This state is known to deteriorate basic characteristics and reliability characteristics, that is, data retention characteristics and rewrite endurance in a flash memory that is repeatedly rewritten.

  In addition, when data is written to an erased memory cell, the memory cell threshold voltage is high immediately after the data is written by electron injection. It moves to the injected region and combines with the electrons that have determined the memory cell threshold voltage. As a result, the memory cell threshold voltage decreases with time, and eventually erroneous determination of data occurs. In addition, flash memories in recent years are required to be rewritten a large number of times, and even if over-erasure is slight, the amount of excessive hole accumulation increases in repeated rewriting.

  Thus, the variation in the rewrite speed in the memory cell array causes deterioration in basic performance such as increase in rewrite time and deterioration in reliability.

  As described above, the variation in the rewrite speed in the memory cell array has been described due to the voltage drop due to the resistance of the bit line. However, other than this cause, the layout of the peripheral circuit and wiring of the memory cell, the process variation, etc. Something that is not done occurs.

  An object of the present invention is to solve the above-described conventional problems, and an object of the present invention is to suppress variations in rewrite speed depending on memory cell positions in a memory cell array in a nonvolatile semiconductor memory device.

  In order to achieve the above object, the present invention includes a voltage correction circuit that corrects a gate voltage or the like of a memory cell with a resistance, a capacitance, or the like in accordance with the position of the memory cell in the memory cell array, or a transistor constituting the memory cell By making the channel widths different from each other, the rewriting speed of a large number of memory cells is made the same regardless of the memory cell position in the memory cell array.

  According to the present invention, variation in the rewrite speed in the memory cell array can be reduced, shortening the rewrite time that has been increased due to the variation, reduction of the power supply circuit due to narrowing of the power supply range necessary for rewrite, and occurrence due to speed variation As a result, it is possible to reduce the phenomenon such as over-erasing that has been performed, and to improve data retention characteristics and rewriting durability.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 shows a configuration example of a nonvolatile semiconductor memory device according to the present invention. In FIG. 1, 101 is a memory cell array, 102 is a voltage correction circuit, and 104 is a word line driving circuit. The voltage correction circuit 102 is interposed on n (n is an integer) number of word lines W1 to Wn driven by the word line driving circuit 104, and includes resistors R1 to Rn having different resistance values. The resistance value regularly changes up to Rn / 2, and the resistance value changes regularly from Rn / 2 + 1 to Rn.

  The memory cell array 101 has n gate lines G1 to Gn corresponding to the word lines W1 to Wn, and a number of bit lines. However, for simplification of the drawing, only five bit lines B0 to B4 are shown in FIG. These bit lines B0 to B4 are each formed of an impurity region, and are connected to metal wirings by upper contacts CA0 to CA4 and lower contacts CB0 to CB4, respectively. One memory cell 103a in the memory cell array 101 is configured with a bit line B0 as a source, a bit line B1 as a drain, and a gate line G1 as a gate. The other memory cell 103b in the memory cell array 101 is configured with the bit line B0 as a source, the bit line B1 as a drain, and the gate line Gn / 2 as a gate. A required voltage is applied to the sources and drains of these memory cells 103a and 103b via bit lines B0 and B1. However, the central memory cell 103b is located far from the contacts CA0 and CA1 compared to the end memory cell 103a.

  When erasing data stored in the memory cell array 101, when the memory cells 103a and 103b have the memory cell structure having the trap layer shown in FIG. 8, for example, -3V is applied to all the gate lines G1 to Gn and the bit line. 5V is applied to B1 (drain), and 0V is applied to the bit line B0 (source). At this time, the drain voltage of the end memory cell 103a and the drain voltage of the central memory cell 103b are caused by the consumption current and the resistance component of the bit line due to the difference in distance from the contacts CA0 and CA1. The difference occurs because of the voltage drop that occurs.

  In order to correct the difference in drain voltage, the voltage correction circuit 102 applies different potentials to the gate line G0 at the end and the gate line Gn / 2 at the center. When, for example, −3 V is applied to the gate line Gn / 2 of the memory cell 103b in which the drain voltage is decreased, the absolute value is smaller than −3 V in the gate line G1 of the memory cell 103a in which the drain voltage is not decreased. For example, −2.5V is applied. Therefore, the resistance values of the resistors R1 to Rn provided as the voltage correction circuit 102 in FIG. 1 are determined so as to correct the drain voltage drop due to the bit line voltage drop, and -3V is uniformly applied from the word line driving circuit 104. Thus, −2.5V to −3V can be applied to the gate lines G1 to Gn / 2, and −3V to −2.5V can be applied to the gate lines Gn / 2 + 1 to Gn, respectively.

  As a result, the time required for erasing the memory cells 103a and 103b becomes the same, and variations in the erasing speed in the memory cell array 101 are reduced. Similarly, the variation in the writing speed in the memory cell array 101 is also reduced. However, as the applied voltage value, an optimum value is given from the drain voltage dependency and the gate voltage dependency of the memory cell. Therefore, depending on the structure of the memory cell, the absolute value of the potential of the gate line G1 of the end memory cell 103a May increase.

  For example, the gate voltage can be corrected by changing the length of the wiring from the word line driving circuit 104 to the gate line end.

  Further, by setting the resistors R1 to Rn in FIG. 1 to an impurity region that is the same material as the bit lines B0 to B4, for example, even when the voltage drop of the bit lines B0 to B4 differs due to variations in the manufacturing process. It is possible to follow.

  Similarly, the resistors R1 to Rn can be formed of transistors having different channel widths, and this can be realized without increasing the area by changing the transistor channel width of the word line driving circuit 104. .

  The voltage correction circuit 102 may be configured by a switch that turns on / off at different timings. The gate voltage application time (pulse width) is varied by these switches, and the voltage drop due to the memory cell position in the memory cell array 101 is corrected.

  The voltage correction circuit 102 may be formed by capacitors having different capacitance values. By setting the capacitances to different capacitance values, the gate voltage application time (pulse width) is varied, and the voltage drop due to the memory cell position in the memory cell array 101 is corrected. Further, the capacitors having different capacitance values can be realized, for example, by changing the length and width of the wiring from the word line driving circuit 104 to the gate line end to make the wiring capacitance.

  FIG. 2 shows another configuration example of the nonvolatile semiconductor memory device according to the present invention. 2, the arrangement of the voltage correction circuit 102 in FIG. 1 is omitted, and the channel of the transistors constituting the memory cells 203a and 203b is suppressed so that the variation in the rewrite speed depending on the memory cell position in the memory cell array 101 is suppressed. The width is set to be different depending on the memory cell position. That is, the channel width of the transistors constituting the memory cells 203a and 203b regularly changes from the position of the gate line G1 to the position of Gn / 2, and regularly from the position of Gn / 2 + 1 to the position of Gn. It has changed.

  When erasing data stored in the memory cell array 101, when the memory cells 203a and 203b have the memory cell structure having the trap layer shown in FIG. 8, for example, −3V is applied to all the gate lines G1 to Gn and the bit line B1 ( 5V is applied to the drain), and 0V is applied to the bit line B0 (source). At this time, the drain voltage of the memory cell 203a at the end and the drain voltage of the central memory cell 203b are caused by the consumption current and the resistance component of the bit line due to the difference in distance from the contacts CA0 and CA1. The difference occurs because of the voltage drop that occurs.

  However, since the channel widths of the transistors constituting the memory cells 203a and 203b are different according to the decrease in the drain voltage, the time required for erasing the memory cells 203a and 203b regardless of the position in the memory cell array 101. And the variation in the erase speed in the memory cell array 101 is reduced.

  FIG. 3 shows a modification of the voltage correction circuit 102 in FIG. According to FIG. 3, the resistance value is made variable by changing the wiring layer by the resistance switching mask 301, and the output voltage of the voltage correction circuit 102 is changed. This makes it possible to obtain the effects of the present invention in a short period even when a characteristic difference occurs in the memory cell array 101 due to manufacturing or circuit layout, which is not assumed at the time of design.

  It should be noted that, as another mechanism for physically changing the output voltage of the voltage correction circuit 102, it is possible to employ an electrically disconnectable fuse or the like.

  FIG. 4 shows another modification of the voltage correction circuit 102 in FIG. According to FIG. 4, the voltage correction circuit 102 has a plurality of output switching mechanisms 402 for changing the output voltage, and the output voltage of the voltage correction circuit 102 is electrically variable in accordance with the signal input 401 from the external terminal. .

  FIG. 5 shows still another modification of the voltage correction circuit 102 in FIG. In FIG. 5, reference numeral 501 denotes a circuit for detecting the ambient temperature, a circuit for detecting the number of rewrites of the nonvolatile semiconductor memory device, or a nonvolatile memory. The control circuit 503 receives the control signal 502 from the detection circuit / memory 501 and controls the operations of the plurality of output switching mechanisms 504 that change the output voltage. As a result, it is possible to correct the difference in characteristics depending on the memory cell position in the memory cell array 101 that changes depending on the ambient temperature and the number of rewrites, and also feeds back lot information and inspection information to the nonvolatile memory 501 for correction. Thus, higher effects can be obtained.

  FIG. 6 shows a configuration example of an electronic device using the nonvolatile semiconductor memory device according to the present invention. The electronic device of FIG. 6 includes a first memory cell array 601 having a mechanism that eliminates the characteristic difference that occurs according to the memory cell position as described above, and a mechanism that eliminates the characteristic difference that occurs according to the memory cell position. A memory core 603 having a second memory cell array 602 that does not include data, data input / output paths 604 and 605 connected to the respective memory cell arrays 601 and 602, and each memory via these data input / output paths 604 and 605 This is composed of a cell array 601 and 602 and a system 606 connected thereto.

  With this configuration, the system 606 connected to the first and second memory cell arrays 601 and 602 via the data input / output paths 604 and 605 has a function of selecting a recording destination memory cell array according to the type of data to be recorded. For example, data that is frequently rewritten or data that requires longer-term data retention characteristics requires data that is hardly rewritten or high-speed access to the first memory cell array 601. By recording the data to be recorded in the second memory cell array 602, different data can be recorded in one memory core 603.

  FIG. 7 shows another configuration example of an electronic apparatus using the nonvolatile semiconductor memory device according to the present invention. The electronic device in FIG. 7 includes a memory cell array 701 that can turn on / off a mechanism for eliminating the characteristic difference that occurs according to the memory cell position as described above, and a memory core 702 that includes the memory cell array 701. An on / off signal line 703 connected to the memory cell array 701 and a system 704 connected to the memory cell array 701 through the on / off signal line 703 are configured.

  The system 704 can turn on / off a mechanism that eliminates a characteristic difference that occurs according to the memory cell position in the memory cell array 701. Since this mechanism can be turned on / off, the system 704 can handle the data of the memory core 702 in accordance with the purpose of the data. For example, when data is rewritten, it can be turned on to improve rewrite characteristics, and when data is read, it can be turned off to perform high-speed access.

  As described above, an example has been given of the case where a characteristic difference due to the memory cell position along the bit line in the memory cell array occurs. However, the present invention eliminates the position dependency along the word line due to, for example, layout or manufacturing process. Alternatively, it can be applied to suppression of random characteristic variation in the memory cell array.

  As described above, the nonvolatile semiconductor memory device according to the present invention can increase the rewrite time, improve the data retention characteristics of the memory cells, and the rewrite endurance, for example, a trap layer in which a bit line is formed in an impurity region. It is useful as a non-volatile memory having

1 is a block diagram illustrating a configuration example of a nonvolatile semiconductor memory device according to the present invention. It is a block diagram which shows the other structural example of the non-volatile semiconductor memory device based on this invention. It is a block diagram which shows the modification of the voltage correction circuit in FIG. It is a block diagram which shows the other modification of the voltage correction circuit in FIG. It is a block diagram which shows the further another modification of the voltage correction circuit in FIG. It is a block diagram which shows the structural example of the electronic device using the non-volatile semiconductor memory device which concerns on this invention. It is a block diagram which shows the other structural example of the electronic device using the non-volatile semiconductor memory device which concerns on this invention. It is sectional drawing which shows the memory cell structure of the conventional non-volatile semiconductor memory device.

Explanation of symbols

101 memory cell array 102 voltage correction circuit 103a, 103b memory cell 104 word line driving circuit 203a, 203b memory cell 301 resistance switching mask 401 signal input from external terminal 402 output switching mechanism 501 detection circuit / memory 502 control signal 503 control circuit 504 output Switching mechanism 601 First memory cell array 602 Second memory cell array 603 Memory core 604, 605 Data input / output path 606 System 701 Memory cell array 702 Memory core 703 On / off signal line 704 System 801 Semiconductor substrate 802 Channel region 803 First Impurity region (drain)
804 Second impurity region (source)
805 Top insulating film 806 Trap layer 807 Bottom insulating film 808 Gate electrodes B0 to B4 Bit lines CA0 to CA4 Contacts CB0 to CB4 Contacts G1 to Gn Gate lines R1 to Rn Resistors W1 to Wn Word lines

Claims (29)

A memory cell array having a plurality of memory cells arranged at intersections of a plurality of bit lines and a plurality of word lines;
A function of simultaneously correcting applied voltages to a plurality of memory cells in the memory cell array according to the memory cell positions in the memory cell array so that a variation in rewriting speed depending on the memory cell positions in the memory cell array is suppressed; A nonvolatile semiconductor memory device comprising: a voltage correction circuit having the same. The nonvolatile semiconductor memory device according to claim 1,
The non-volatile semiconductor memory device, wherein each of the plurality of bit lines is formed of an impurity region. A memory cell array having a plurality of memory cells arranged at intersections of a plurality of bit lines and a plurality of word lines;
The channel width of a transistor constituting each of the plurality of memory cells differs depending on the memory cell position in the memory cell array so that variation in rewrite speed depending on the memory cell position in the memory cell array is suppressed. A nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device according to claim 1,
The nonvolatile semiconductor memory device, wherein the voltage correction circuit is connected to the plurality of word lines. The nonvolatile semiconductor memory device according to claim 1,
The nonvolatile semiconductor memory device, wherein the voltage correction circuit is connected to source lines of the plurality of memory cells. The nonvolatile semiconductor memory device according to claim 4.
The non-volatile semiconductor memory device, wherein the voltage correction circuit varies the absolute value levels of the voltages of the plurality of word lines according to a wiring distance of the plurality of bit lines to the memory cell position. The nonvolatile semiconductor memory device according to claim 4.
The non-volatile semiconductor memory device, wherein the voltage correction circuit varies the voltage application time of the plurality of word lines according to the wiring distance of the plurality of bit lines to the memory cell position. The nonvolatile semiconductor memory device according to claim 6,
The non-volatile semiconductor memory device, wherein the voltage correction circuit is formed by a plurality of resistance elements having different resistance values. The nonvolatile semiconductor memory device according to claim 8,
The non-volatile semiconductor memory device, wherein each of the plurality of resistance elements is formed by a wiring. The nonvolatile semiconductor memory device according to claim 8,
The non-volatile semiconductor memory device, wherein each of the plurality of resistance elements is formed of an impurity region. The nonvolatile semiconductor memory device according to claim 8,
The non-volatile semiconductor memory device, wherein the plurality of resistance elements are formed of transistors having different channel widths. The nonvolatile semiconductor memory device according to claim 7,
The nonvolatile semiconductor memory device, wherein the voltage correction circuit is formed by a plurality of capacitive elements having different capacitance values. The nonvolatile semiconductor memory device according to claim 12,
The non-volatile semiconductor memory device, wherein each of the plurality of capacitive elements is formed by a wiring. The nonvolatile semiconductor memory device according to claim 1,
A nonvolatile semiconductor memory device having an output switching mechanism for changing an output voltage of the voltage correction circuit. 15. The nonvolatile semiconductor memory device according to claim 14,
The non-volatile semiconductor memory device, wherein the output switching mechanism changes a wiring layer. 15. The nonvolatile semiconductor memory device according to claim 14,
The non-volatile semiconductor memory device, wherein the output switching mechanism is for cutting with a laser or the like. 15. The nonvolatile semiconductor memory device according to claim 14,
The non-volatile semiconductor memory device, wherein the output switching mechanism is an electric fuse. 15. The nonvolatile semiconductor memory device according to claim 14,
The non-volatile semiconductor memory device, wherein the output switching mechanism is a non-volatile memory. 15. The nonvolatile semiconductor memory device according to claim 14,
The non-volatile semiconductor memory device, wherein the output switching mechanism operates in response to a signal input. The nonvolatile semiconductor memory device according to claim 19,
The nonvolatile semiconductor memory device, wherein the signal input is a signal from a temperature detection circuit. The nonvolatile semiconductor memory device according to claim 19,
The nonvolatile semiconductor memory device, wherein the signal input is a signal from a circuit that detects the number of rewrites of the nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device according to claim 19,
The nonvolatile semiconductor memory device, wherein the signal input is based on information recorded in a nonvolatile memory. The nonvolatile semiconductor memory device according to claim 22,
A non-volatile semiconductor memory device, wherein information recorded in the non-volatile memory is set in a manufacturing unit in an inspection process. The nonvolatile semiconductor memory device according to claim 22,
A non-volatile semiconductor memory device, wherein information recorded in the non-volatile memory is set in units of rewrite areas in an inspection process. The nonvolatile semiconductor memory device according to claim 22,
A non-volatile semiconductor memory device, wherein information recorded in the non-volatile memory is set based on a characteristic at the time of previous rewriting. The nonvolatile semiconductor memory device according to claim 1,
The nonvolatile semiconductor memory device, wherein the voltage correction circuit is changed for each batch erase unit of the memory cell array. The nonvolatile semiconductor memory device according to claim 1,
A nonvolatile semiconductor memory device comprising: at least one batch erase unit including the voltage correction circuit; and at least one batch erase unit not including the voltage correction circuit.   28. An electronic apparatus comprising the nonvolatile semiconductor memory device according to claim 27, and further comprising a mechanism for selecting a batch erase unit for performing data recording.   An electronic apparatus comprising the nonvolatile semiconductor memory device according to claim 1, and further comprising a mechanism for determining operation or non-operation of the voltage correction circuit.

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