JP2017107626A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of suppressing program disturbance.SOLUTION: A semiconductor device includes: a memory cell unit; a bit line; a source line; a plurality of word lines WL0 through WLn; and a row control circuit 202. The memory cell unit includes a plurality of memory cells connected in series. The bit line is electrically connected to one end of a current path of the memory cell unit. The source line is electrically connected to the other end of the current path of the memory cell unit. The plurality of word lines WL0 through WLn is electrically connected to individual gate electrodes of the plurality of memory cells. The row control circuit 202 outputs write pulses to the plurality of word lines WL0 through WLn. Waveforms of the write pulses output to the plurality of word lines WL0 through WLn by the row control circuit 202 are different from one another according as positions of the word lines WL0 through WLn.SELECTED DRAWING: Figure 10

Description

  Embodiments described herein relate generally to a semiconductor device.

  A memory device with a three-dimensional structure is proposed in which a memory hole is formed in a stacked body in which a plurality of electrode layers are stacked, and a charge storage film and a semiconductor film extend in the stacking direction of the stacked body in the memory hole. Has been. Memory holes have a large aspect ratio. For this reason, it is difficult to process the memory hole vertically to the lower layer. The diameter of the memory hole is small in the lower layer and large in the upper layer. As a result, the resistance value of the word line is large in the upper layer and small in the lower layer. The difference in the resistance value of the word line becomes a factor that causes erroneous write such as program disturb during the write operation, for example. It is desirable to suppress program disturb.

JP 2011-96340 A

  Embodiments provide a semiconductor device capable of suppressing program disturb.

  The semiconductor device of the embodiment includes a memory cell unit, a bit line, a source line, a plurality of word lines, and a row control circuit. The memory cell unit includes a plurality of memory cells connected in series. The bit line is electrically connected to one end of the current path of the memory cell unit. The source line is electrically connected to the other end of the current path of the memory cell unit. The plurality of word lines are electrically connected to the gate electrodes of the plurality of memory cells. The row control circuit outputs a write pulse to a plurality of word lines. The waveform of the write pulse output from the row control circuit to the plurality of word lines differs depending on the position of the word line.

FIG. 1 is a schematic block diagram of a semiconductor device according to an embodiment. FIG. 2 is a schematic perspective view of the memory cell array of the semiconductor device of the embodiment. FIG. 3 is an equivalent circuit diagram of the memory string MS. FIG. 4 is a schematic cross-sectional view of a columnar portion of the semiconductor device of the embodiment. FIG. 5 is a schematic perspective view of the uppermost word line and the lowermost word line. FIG. 6 is an enlarged schematic cross-sectional view of the inside of the broken line frame 6 in FIG. FIG. 7 is an equivalent circuit diagram of the memory cell array. FIG. 8 is a schematic diagram showing the waveform of the write pulse. FIG. 9 is a schematic diagram showing the waveform of the write pulse. FIG. 10 is a schematic circuit diagram schematically illustrating a first circuit example of the semiconductor device of the embodiment. FIG. 11 is a schematic circuit diagram schematically illustrating a second circuit example of the semiconductor device of the embodiment.

  Hereinafter, embodiments will be described with reference to the drawings. In addition, the same code | symbol is attached | subjected to the same element in each drawing. The semiconductor device of the embodiment is a semiconductor memory device having a memory cell array.

FIG. 1 is a schematic block diagram of a semiconductor device according to an embodiment.
As shown in FIG. 1, the semiconductor device includes a memory cell array 1. In the memory cell array 1, for example, a bit line BL, a word line WL, a source line SL, a drain side selection transistor STD, a memory cell MC, and a source side selection transistor STS are provided.

  A column control circuit 201 and a row control circuit 202 are provided around the memory cell array 1. The column control circuit 201 controls the bit line BL and the source line SL, and erases data from the memory cell MC, writes data to the memory cell MC, and reads data from the memory cell MC.

  The row control circuit 202 selects a word line WL, and supplies a potential required for erasing data from the memory cell MC, writing data to the memory cell MC, and reading data from the memory cell MC, to the drain-side selection transistor STD. To the gate electrodes of the memory cell MC and the source side select transistor STS.

  The data input / output buffer 203 receives external I / O data from the external host 204. The data input / output buffer 203 receives write data, receives command data, receives address data, and outputs read data to the outside.

  The data input / output buffer 203 sends the received write data to the column control circuit 201. The column control circuit 201 sends read data from the memory cell array 1 to the data input / output buffer 203. The data input / output buffer 203 outputs the received read data to the outside.

  The data input / output buffer 203 sends the received address data to the address register 205. The address register 205 sends the received address data to the column control circuit 201 and the row control circuit 202.

  A command interface (command I / F) 206 receives an external control signal from the host 204. Based on the received external control signal, the command interface (command I / F) 206 determines whether the data received by the data input / output buffer 203 is write data, command data, or address data. If the data received by the data input / output buffer 203 is command data, the command interface 206 sends it to the state machine 207 as a command signal.

  The state machine 207 manages the overall operation of the semiconductor device. The state machine 207 receives command data from the host 204 via the command interface 206 and outputs an internal control signal. Thus, for example, writing, reading, erasing, and data input / output management are performed. The voltage generation circuit 208 generates an internal voltage necessary for a write operation, a read operation, and an erase operation based on the internal control signal. The state machine 207 manages status information. Status information can also be sent to the host 204. The host 204 can determine the operation status and operation result of the semiconductor device by receiving the status information.

FIG. 2 is a schematic perspective view of the memory cell array 1 of the semiconductor device according to the embodiment.
As shown in FIG. 2, the memory cell array 1 includes a stacked body 100, a plurality of columnar portions CL, and a plurality of slits ST. The stacked body 100 includes a drain side select gate SGD, a plurality of word lines WL, and a source side select gate SGS.

  The source side selection gate SGS is provided on the substrate 10. The substrate 10 is, for example, a semiconductor substrate. The semiconductor substrate includes, for example, silicon. The plurality of word lines WL are provided on the source side selection gate SGS. The drain side select gate SGD is provided on the plurality of word lines WL. The drain side selection gate SGD, the plurality of word lines WL, and the source side selection gate SGS are electrode layers. The number of electrode layers stacked is arbitrary.

  The electrode layers (SGD, WL, SGS) are stacked apart. An insulator 40 is disposed between the electrode layers (SGD, WL, SGS). The insulator 40 may be an insulator such as a silicon oxide film or an air gap. The stacked body 100 includes the insulators 40 and electrode layers (SGD, WL, SGS) alternately.

  The drain side select transistor STD uses at least one of the drain side select gates SGD as a gate electrode. The source side select transistor STS uses at least one of the source side select gates SGS as a gate electrode. A plurality of memory cells MC are connected in series between the drain side select transistor STD and the source side select transistor STS. The memory cell MC uses one of the word lines WL as a gate electrode.

FIG. 3 is an equivalent circuit diagram of the memory string MS.
As shown in FIG. 3, the memory string MS is a memory cell unit including a plurality of memory cells MC. The memory string MS includes a drain side select transistor STD, a source side select transistor STS, and a plurality of memory cells MC connected in series between the drain side select transistor STD and the source side select transistor STS. The bit line BL is electrically connected to one end of the current path of the memory string MS, and the source line SL is electrically connected to the other end of the current path of the memory string MS. In the case of the semiconductor device shown in FIG. 2, the memory string MS is provided in the stacked body 100.

  The slit ST is provided in the stacked body 100. The slit ST extends in the stacked body 100 in the stacking direction (Z direction) and the X direction. The slit ST separates the stacked body 100 into a plurality of pieces in the Y direction. The region separated by the slit ST is called “block”.

  A source line SL is disposed in the slit ST. The source line SL is a conductor. The source line SL is insulated from the stacked body 100 and extends, for example, in a plate shape in the Z direction and the X direction. An upper layer wiring 80 is arranged above the source line SL. The upper layer wiring 80 extends in the Y direction. The upper layer wiring 80 is electrically connected to the plurality of source lines SL arranged in the Y direction.

  The columnar part CL is provided in the stacked body 100 separated by the slits ST. The columnar portion CL extends in the stacking direction (Z direction). The columnar part CL is formed in, for example, a columnar shape or an elliptical columnar shape. The columnar portions CL are arranged in the memory cell array 1 in, for example, a staggered lattice shape or a square lattice shape. The drain side select transistor STD, the plurality of memory cells MC, and the source side select transistor STS are arranged in the columnar portion CL.

  A plurality of bit lines BL are arranged above the upper end of the columnar part CL. The plurality of bit lines BL extend in the Y direction. The upper end portion of the columnar portion CL is electrically connected to one of the bit lines BL via the contact portion Cb. One bit line BL is electrically connected to a columnar portion CL selected one by one from each block.

  FIG. 4 is a schematic cross-sectional view of the columnar portion CL of the semiconductor device of the embodiment. FIG. 5 is a schematic perspective view of the uppermost word line WLn and the lowermost word line WL0. FIG. 6 is an enlarged schematic cross-sectional view of the inside of the broken line frame 6 in FIG. FIG. 4 corresponds to a cross section parallel to the YZ plane in FIG.

  As shown in FIGS. 4 to 6, the columnar portion CL is provided in the memory hole (opening) MH. The memory hole MH is provided in the memory cell array 1 of the stacked body 100. The memory hole MH extends along the stacking direction (Z direction) of the stacked body 100 in the stacked body 100. The columnar part CL includes the memory film 30, the semiconductor body 20, and the core layer 50.

  The memory film 30 is provided on the inner wall of the memory hole MH. The shape of the memory film 30 is, for example, a cylindrical shape. The memory film 30 includes a cover insulating film 31, a charge storage film 32, and a tunnel insulating film 33.

  The cover insulating film 31 is provided on the inner wall of the memory hole MH. The cover insulating film 31 includes, for example, silicon oxide. The cover insulating film 31 protects, for example, the charge storage film 32 from etching when the word line WL is formed.

  The charge storage film 32 is provided on the cover insulating film 31. The charge storage film 32 includes, for example, silicon nitride. The charge storage film 32 has a trap site for trapping charges in the film, and traps charges. The threshold value of the memory cell MC varies depending on the presence / absence of trapped charges and the amount of trapped charges. Thereby, the memory cell MC holds information.

  The tunnel insulating film 33 is provided on the charge storage film 32. The tunnel insulating film 33 includes, for example, silicon oxide or silicon oxide and silicon nitride. The tunnel insulating film 33 is a potential barrier between the charge storage film 32 and the semiconductor body 20. The tunnel insulating film 33 tunnels charges when injecting charges from the semiconductor body 20 to the charge storage film 32 (write operation) and discharging charges from the charge storage film 32 to the semiconductor body 20 (erase operation).

  In the stacked body 100, the electrode layers (SGD, WL, SGS) are provided on the memory film 30. The electrode layer (SGD, WL, SGS) includes, for example, tungsten.

  The semiconductor body 20 is provided on the memory film 30 on the side opposite to the electrode layers (SGD, WL, SGS). The semiconductor body 20 includes, for example, silicon. Silicon is, for example, polysilicon obtained by crystallizing amorphous silicon. The conductivity type of silicon is, for example, P type. The shape of the semiconductor body 20 is, for example, a cylinder having a bottom. The semiconductor body 20 is electrically connected to the substrate 10, for example.

  A core layer 50 is provided on the semiconductor body 20. The core layer 50 is insulative. The core layer 50 includes, for example, silicon oxide. The core layer 50 has a columnar shape, for example. A cap layer 51 is provided on the upper surface of the core layer 50. The cap layer 51 includes, for example, silicon. Silicon is, for example, polysilicon obtained by crystallizing amorphous silicon. The conductivity type of silicon is, for example, N type. The cap layer 51 is electrically connected to the semiconductor body 20 above the memory hole MH.

  The memory hole MH is filled with the memory film 30, the semiconductor body 20, the core layer 50, and the cap layer 51.

  A first insulating film 81 and a second insulating film 82 are provided on the upper surface of the stacked body 100. The first insulating film 81 is provided on the stacked body 100. The second insulating film 82 is provided on the first insulating film 81. A contact portion Cb is provided in the second insulating film 82. The contact portion Cb is electrically connected to the semiconductor body 20 and the cap layer 51, for example.

  The memory hole MH has a large aspect ratio. For this reason, it is difficult to process the memory hole MH vertically to the lower layer. Therefore, as shown in FIG. 5, the diameter of the memory hole MH is small on the lower layer side of the stacked body 100 and larger on the upper layer of the stacked body 100. As a result, the resistance value of the word line WL is, for example, the highest in the uppermost word line WLn and the lowest in the lowermost word line WL0. In the word line WL having a low resistance value, when the potential difference between the word line WL and the channel (hereinafter referred to as the voltage of the word line WL) is raised from the pass voltage Vpass to the write voltage Vpgm, A strong electric field is likely to be generated between them. A strong electric field is temporarily generated, for example, at the moment when the voltage of the word line WL is increased. The word line WL whose voltage is raised to the write voltage Vpgm is called a selected word line. A word line whose voltage maintains the pass voltage Vpass is called a non-selected word line.

  In the write operation, writing that shifts the threshold voltage of the memory cell MC (for example, data “0” writing) and writing that does not shift (for example, data “1” writing) are performed in units of pages (word lines). Done at the same time.

  For writing data “0”, the voltage of the bit line BL is set to, for example, “0V”. The bit line BL whose voltage is set to “0V” is called a selected bit line. A memory cell electrically connected to the selected bit line and the selected word line is called a write selected memory cell. In the write selected memory cell, charges (electrons) are injected into the charge storage film 32, and the threshold voltage shifts in the positive direction. Thereby, for example, data “0” is written in the write selection memory cell.

  For writing data “1”, the voltage of the bit line BL is set to, for example, “Vcc”. The voltage Vcc is, for example, an in-circuit power supply voltage. The bit line BL whose voltage is set to “Vcc” is called a non-selected bit line. A memory cell electrically connected to the unselected bit line and the selected word line is called a write unselected memory cell. In the write non-selected memory cell, charges (electrons) are not injected into the charge storage film 32. For this reason, the threshold voltage maintains the original state. Thereby, the write non-selected memory cell maintains, for example, data “1” (for example, erased state).

  Thus, in the write non-selected memory cell, charges (electrons) must not be injected into the charge storage film 32 in the write operation. However, if the write non-selected memory cell is connected to a word line having a low resistance value (for example, word line WL0), charges (electrons) may be injected into the charge storage film 32. There is a possibility that a strong electric field is generated between the word line WL having a low resistance value, for example, between the word line WL0 and the channel at the moment when the voltage of the word line WL0 is increased to the write voltage Vpgm. Because there is. In the write operation, a phenomenon in which unintended charges (electrons) are injected into the charge value storage film of the write unselected memory cell and the threshold voltage shifts in the positive direction is called program disturb. Program disturb is one of erroneous writing.

  FIG. 7 is an equivalent circuit diagram of the memory cell array 1. FIG. 7 shows a voltage example in the write operation.

As shown in FIG. 7, the selected word line is, for example, the lowermost word line WL0. For example, the lowermost word line WL0 is connected to the gate electrodes of the memory cells MCa to MCc.
The selected bit line is, for example, the bit line BLm. A voltage of 0 V is supplied to the selected bit line BLm.
The non-selected bit lines are, for example, bit lines BLm + 1 and BLm−1. The unselected bit lines BLm + 1 and BLm−1 are supplied with a voltage Vcc higher than the voltage 0V.
The write selection memory cell is the memory cell MCb. For example, data “0” is written in the write selection memory cell MCb.
Write non-selected memory cells are memory cells MCa and MCc. The write unselected memory cells MCa and MCc maintain, for example, data “1” (for example, erased state).

  When the voltage of the lowermost word line WL0 is increased from the pass voltage Vpass to the write voltage Vpgm, a large potential difference is applied between the gate electrode and the channel of the memory cell MCb. Therefore, electrons are injected into the charge storage film 32 of the memory cell MCb.

  On the other hand, a potential difference as large as that of the memory cell MCb is not applied between the gate electrodes and the channels of the memory cells MCa and MCc. For this reason, electrons are not injected into the charge storage film 32 of the memory cells MCa and MCc.

  However, the resistance value of the lowermost word line WL0 is low. Therefore, at the moment when the voltage of the word line WL0 is increased from the pass voltage Vpass to the write voltage Vpgm, a strong electric field is temporarily applied between the gate electrodes (WL0) of the memory cells MCa and MCc and the channel. there is a possibility. When a strong electric field is applied to the data “1” or the memory cells MCa and MCc that maintain the current threshold voltage even temporarily, electrons are injected into the charge storage film 32 and the threshold voltage is Shift higher. Program disturb.

  Therefore, in the embodiment, the word lines WL0 to WLn are divided into at least two groups according to the position of the word line WL in the stacked body 100. In the embodiment, for example, it is divided into a group G0 and a group G1. The group G0 is on the lower layer side of the stacked body 100. The group G1 is on the upper layer side of the stacked body 100 with respect to the group G0. The resistance value of the word line WL belonging to the group G0 on the lower layer side of the stacked body 100 is lower than that of the group G1. The resistance value of the word line WL belonging to the group G1 on the upper layer side of the stacked body 100 is higher than that of the group G0. The resistance value of the word line WL is a resistance value including, for example, resistance value variations caused by processing variations.

  In the group G0, a plurality of word lines WL belong from the lowermost word line WL0 to the upper layer. In the embodiment, the word lines WL0 to WL3 belong. In the group G1, a plurality of word lines WL belong from the uppermost word line WLn to the lower layer. In the embodiment, the word lines WLn, WLn−1,... WL4 belong. The number of word lines WL belonging to the group is arbitrary. The number of word lines WL belonging to the group may be one or more.

  An example of the grouping is a group including a word line WL whose resistance value is 5% or more lower than the average value of resistance values of all the word lines WL0 to WLn included in the memory string MS, and other word lines. It is a group that includes WL. However, the number of groups is not limited to two. The number of groups may be three or more. For example, from the average value, for example, a group including a word line WL having a low resistance value in a range of 5% to 7%, and from the average value, for example, a group including a word line WL having a resistance value of 7% or more lower. Other word lines WL may be divided into three groups.

  FIG. 8 is a schematic diagram showing the waveform of the write pulse of group G1. FIG. 9 is a schematic diagram showing the waveform of the write pulse of group G0.

  As shown in FIGS. 8 and 9, in the embodiment, the waveform of the voltage (the waveform of the write pulse) applied to the word line WL during the data write operation is changed between the group G0 and the group G1. Therefore, the waveform of the write pulse differs between the group G0 and the group G1. The write pulse is output from the row control circuit 202 shown in FIG. 1 to the word lines WL0 to WLn, for example. The waveforms shown in FIGS. 8 and 9 are waveforms of write pulses in the word line selected for writing. In the non-programmed word line, for example, the pass voltage Vpass is maintained without increasing the write voltage Vpgm.

  The waveform of the write pulse is changed, for example, by changing the rise time tb until the voltage of the word line WL reaches the write voltage Vpgm from the pass voltage Vpass. The value of the finally reached write voltage Vpgm is, for example, the same in the group G1 and the group G2.

  In the embodiment, the rise time tb0 of the group G0 is longer than the rise time tb1 of the group G1. In the waveform of the write pulse of the group G0, the rise from the pass voltage Vpass to the write voltage Vpgm is gentle compared to the group G1.

  Group G0 includes a word line WL having a low resistance value. Group G1 includes word lines WL having a high resistance value. In the group G0 including the word line WL having a low resistance value, the rise time tb is delayed (tb0> tb1) compared to the group G1 including the word line having a high resistance value. An example of the rise time tb0 is, for example, 20% or more later than the rise time tb1 (tb0 ≧ 1.2 × tb1). However, if the rise time tb0 is set too late, electrons are injected into the charge storage film 32 in the memory cell MC in which data “0” is written or the threshold voltage is shifted in a direction higher than the current value. It becomes difficult. Therefore, the maximum delay time of the rise time tb0 is such that data “0” is written or electrons are sufficiently applied to the charge storage film 32 of the memory cell MC that shifts the threshold voltage in a direction higher than the current value. Up to the value that can be injected.

  In this way, by changing the rise time tb0 of the group G0, the memory cell MC connected to the word line WL having a lower resistance value, for example, the lowermost word line WL0, compared to the case where the rise time tb0 is not changed. , The possibility of applying a strong electric field temporarily can be reduced.

  Therefore, according to the embodiment, compared to a semiconductor device in which the waveform of the write pulse is not changed, the word line WL having a low resistance value, for example, the lowermost word line WL0 is connected to the data “1” or the current state. It is possible to suppress the occurrence of program disturb for the memory cell MC that maintains the threshold voltage.

  FIG. 10 is a schematic circuit diagram schematically illustrating a first circuit example of the semiconductor device of the embodiment. The first circuit example is an example in which the boosting speed of the pump circuit is changed.

  As shown in FIG. 10, the voltage generation circuit 208 includes a pump circuit 210. The pump circuit 210 generates a boosted voltage used for the write pulse. The pump circuit 210 includes a first pump circuit 210a and a second pump circuit 210 circuit. The boosting speed of the first pump circuit 210a is faster than the boosting speed of the second pump circuit 210b. The boosting speed of the second pump circuit 210b is slower than the boosting speed of the first pump circuit 210a.

  The first pump circuit 210a supplies the boosted voltage used for the write pulse to the word lines WL4 to WLn belonging to the group G1 via the row control circuit 202. The second pump circuit 210b supplies the boosted voltage used for the write pulse to the word lines WL0 to WL3 belonging to the group G0 via the row control circuit 202.

  In the first circuit example, as one circuit example, the boosted voltage from the first pump circuit 210 a and the second pump circuit 210 b is supplied to the decode circuit unit 211 included in the row control circuit 202. The decode circuit unit 211 decodes the address data (row address) and changes the voltage of the selected word line WL from, for example, the pass voltage Vpass to the write voltage Vpgm. The write voltage Vpgm is supplied to the selected word line WL via, for example, the block selection transistor unit 212 that receives the block selection signal BLKSEL at the gate.

  In the first circuit example, the boosting speed of the second pump circuit 210b is slower than the boosting speed of the first pump circuit 210a. Therefore, a write pulse as shown in FIG. 9 is applied to the word lines WL0 to WL3 belonging to the loop G0, and a write pulse as shown in FIG. 8 is applied to the word lines WL4 to WLn belonging to the group G1. It can be supplied via the control circuit 202.

  FIG. 11 is a schematic circuit diagram schematically illustrating a second circuit example of the semiconductor device of the embodiment. The second circuit example is an example in which the time constant between the row control circuit 202 and the word line WL is changed.

  As shown in FIG. 11, the row control circuit voltage generation circuit 208 includes a delay circuit 213. The delay circuit 213 is, for example, an RC circuit. In FIG. 11, the resistor R is omitted and only the capacitor C is shown. In the second circuit example, the delay circuit 213 is provided between the decode circuit unit 211 and the block selection transistor unit 212. Delay circuit 213 is electrically connected to word lines WL0 to WL3 belonging to group G0. The delay circuit 213 includes a capacitor C, for example. One electrode of the capacitor C is electrically connected to the wiring 214. The wiring 214 connects the output of the decoding circuit unit 211 and one end of the current path of the block selection transistor unit 212. The other electrode of the capacitor C is electrically connected to, for example, an in-circuit ground potential Vss (for example, 0 V).

  The write potential Vpgm output from the output of the decode circuit unit 211 charges the capacitor C of the delay circuit 213 before being transmitted to the word lines WL0 to WL3. For example, the rising time tb0 is delayed from the rising time tb1 according to the charging period. Therefore, also in the second circuit example, the write pulses as shown in FIG. 9 are applied to the word lines WL0 to WL3 belonging to the group G0, and the word lines WL4 to WLn belonging to the group G1 are applied as shown in FIG. Each write pulse can be supplied via the row control circuit 202.

  In the second circuit example, the delay circuit 213 is provided for the word lines WL0 to WL3. However, the delay circuit 213 can be provided for all of the word lines WL0 to WLn. In this case, the delay amount by the delay circuit 213 is set so that the first group G1 is larger than the second group G1. In order to increase the delay amount, for example, the capacitance of the capacitor C connected to the word line WL may be increased. In order to increase the capacitance of the capacitor C, the planar area of the capacitor C may be increased. Alternatively, if the planar area of the capacitor C is the same, the number of capacitors C connected in parallel between the word line WL and the in-circuit ground potential Vss may be increased.

  In the second circuit example, the delay circuit 213 is provided in the wiring 214 that connects the output of the decoding circuit unit 211 and one end of the current path of the block selection transistor unit 212. However, the delay circuit 213 may be provided between the other end of the current path of the block selection transistor unit 212 and the memory cell array 1.

According to the embodiment, it is possible to provide a semiconductor device capable of suppressing erroneous writing, in particular, program disturb.
In addition, the resistance value of the word line WL according to the embodiment includes a variation in resistance value due to processing variation. For this reason, according to the embodiment, it is possible to provide a semiconductor device that is robust against processing variations.

  The embodiment has been described above. However, the embodiment is not limited to the above embodiment, and the above embodiment is not the only one. The embodiment can also be applied to a planar memory device.

  The embodiment that can suppress the increase in the threshold voltage of the memory cell MC due to program disturb is particularly effective for a multi-level memory that stores information exceeding two values in one memory cell MC.

  BL ... bit line, WL ... word line, SL ... source line, STD ... drain side select transistor, SGD ... drain side select gate, MC ... memory cell, STS ... source side select transistor, SGS ... source side select gate, MS ... Memory string, CL ... columnar portion, Cb ... contact portion, MH ... memory hole, ST ... slit, 1 ... memory cell array, 10 ... substrate, 20 ... semiconductor body, 30 ... memory film, 31 ... cover insulating film, 32 ... charge Storage film 33 ... Tunnel insulating film, 40 ... Insulator, 51 ... Cap layer, 80 ... Upper layer wiring, 100 ... Laminate, 201 ... Column control circuit, 202 ... Row control circuit, 203 ... Data input / output buffer, 204 ... Host 205 ... Address register 206 ... Command interface 207 ... State machine 208 ... Pressure generating circuit, 210 ... pump circuit, 210a ... first pump circuit, 210 b ... second pump circuit, 211 ... decoding circuit portion, 212 ... block selection transistor section, 213 ... delay circuit

Claims (11)

A memory cell unit including a plurality of memory cells connected in series;
A bit line electrically connected to one end of a current path of the memory cell unit;
A source line electrically connected to the other end of the current path of the memory cell unit;
A plurality of word lines electrically connected to each of the gate electrodes of the plurality of memory cells;
A row control circuit for outputting a write pulse to the plurality of word lines;
With
The semiconductor device, wherein a waveform of the write pulse output from the row control circuit to the plurality of word lines differs according to a position of the word line. The plurality of word lines are divided into at least two groups according to the position of the word lines,
The semiconductor device according to claim 1, wherein a waveform of the write pulse is different for each group.   The semiconductor device according to claim 2, wherein a rise time of the write pulse from the pass voltage to the write voltage is different for each group. The group includes a first group and a second group;
The first group of word lines has a lower resistance value than the second group of word lines,
The semiconductor device according to claim 3, wherein a rise time of the first group is slower than a rise time of the second group.   The semiconductor device according to claim 4, wherein a rise time of the first group is 20% or more later than that of the second group.   6. The semiconductor device according to claim 4, wherein the first group includes a word line having a resistance value lower by 5% or more than an average resistance value of all the word lines included in the memory cell unit. The memory unit is provided in a stacked body in which electrode layers and insulators are alternately stacked,
The semiconductor device according to claim 1, wherein the plurality of memory cells are provided in the stacked body along a stacking direction of the stacked body. The memory unit is provided in a stacked body in which electrode layers and insulators are alternately stacked,
The plurality of memory cells are provided in the stacked body along a stacking direction of the stacked body,
The first group is on the lower layer side of the laminate,
The semiconductor device according to claim 4, wherein the second group is on an upper layer side of the stacked body than the first group.   The semiconductor device according to claim 1, wherein the resistance value of the word line includes a variation in resistance value caused by processing variation. A voltage generation circuit;
The voltage generation circuit includes a pump circuit that generates a boosted voltage used for the write pulse,
The pump circuit includes a first pump circuit, and a second pump circuit whose boosting speed is slower than that of the first pump circuit,
The first pump circuit supplies a boosted voltage used for the write pulse to the second group via the row control circuit,
10. The semiconductor device according to claim 4, wherein the second pump circuit supplies a boosted voltage used for the write pulse to the first group via the row control circuit. 11. The row control circuit includes a delay circuit electrically connected to the word line,
10. The semiconductor device according to claim 4, wherein a delay amount of the delay circuit is larger in the first group than in the second group.

Images