JP2011044187A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device which can suppress variations in the threshold voltages of memory cells caused depending on a distance from a row decoder to a memory cell. <P>SOLUTION: The semiconductor memory device includes: a plurality of word lines extending in a first direction; a plurality of bit lines extending in a second direction crossing with the first direction; a memory cell array containing the memory cells provided corresponding to the intersections of the word lines and the bit lines; the row decoder which drives a word line selected from among the word lines; a sense amplifier for detecting data in the memory cells via the bit lines; a voltage generation part for generating first to n-th (n is an even number ≥2) voltages increasing in ascending order; and a voltage selection part which when writing data into the memory cells, respectively connects the first to n-th voltages in order from a bit line near the row decoder toward a bit line distant from the row decoder on the basis of the row address designating one of the word lines. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device.

  In the flash memory, in order to reduce the bit cost, a multi-value technique for storing data of 2 bits or more in one memory cell is widely used. In addition, in order to reduce the chip size, memory cells have been miniaturized. Thereby, the wiring width of the word line and the bit line is reduced. In addition, the lengths of word lines and bit lines are increasing due to an increase in storage capacity.

  As the word line width decreases and the word line length increases, the resistance of the word line increases. When the resistance of the word line increases, the voltage level of the word line differs at a position close to the row decoder and a position far from the row decoder during a write operation. In this case, even if the same data is written, the threshold voltage of the memory cell after the data writing varies depending on the distance from the row decoder to the memory cell. That is, after data writing, the threshold distribution of each data in the memory cell is widened. This leads to degradation of reliability and performance.

Japanese translation of PCT publication No. 2008-524772

  Provided is a semiconductor memory device capable of suppressing variations in threshold voltage of a memory cell caused by a distance from a row decoder to a memory cell.

  A semiconductor memory device according to an embodiment of the present invention includes a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction intersecting the first direction, and the word A memory cell array including a plurality of memory cells provided corresponding to the intersections of a line and the bit line, a row decoder for driving a selected word line among the plurality of word lines, and the bit line A sense amplifier that detects data of the memory cell; a voltage generator that generates first to n-th (n is an even number greater than or equal to 2) voltages that increase in ascending order; and data writing to the memory cell. Based on a row address designating one of the word lines, the first to nth bits in order from the bit line close to the row decoder to the bit line far from the row decoder. And a voltage selecting unit for connecting the pressure respectively.

  The semiconductor memory device according to the present invention can suppress variations in the threshold voltage of the memory cell caused by the distance from the row decoder to the memory cell.

1 is a block diagram showing a main configuration of a NAND flash memory 100 according to a first embodiment. FIG. 2 is a circuit diagram showing a circuit configuration of a NAND string NS in the column direction in the memory cell array MCA of FIG. 1. The figure which shows the concept of the block, page, etc. of the memory cell array MCA. FIG. 3 is a schematic diagram showing the arrangement of row decoders RD and word lines WL for a memory cell array MCA. FIG. 9 is a timing chart showing a write operation. The conceptual diagram of the selection cell string NS. The conceptual diagram of the selection cell string NS. The graph which shows the voltage of the selection word line WL at the time of writing of data "0", and the voltage of bit line BL0. The circuit diagram which shows the internal structure of the voltage generation selection circuit VGSC. The circuit diagram which shows the internal structure of the voltage generation selection circuit VGSC. The figure which shows the arrangement | positioning relationship between the voltage selection circuit VSC and sense amplifier S / A. The circuit diagram which shows an example of the internal structure of sense amplifier S / A. The block diagram of the sense amplifier S / A and voltage selection circuit VSC in 2nd Embodiment. The circuit diagram which shows the structure of the voltage generation circuit VGC in 2nd Embodiment. The block diagram of the control signal generation circuit SCG which produces | generates the control signal Sa. The graph which shows the voltage of the selection word line WLm at the time of writing of data "0", and the voltage of bit line BL0.

  Embodiments according to the present invention will be described below with reference to the drawings. This embodiment does not limit the present invention.

(First embodiment)
FIG. 1 is a block diagram showing a main configuration of a NAND flash memory 100 according to the first embodiment which is an aspect of the present invention. FIG. 2 is a circuit diagram showing a circuit configuration of the NAND string NS in the column direction in the memory cell array MCA of FIG. Note that this embodiment can be easily applied to a NOR flash memory.

  The NAND string NS includes a plurality of memory cells M connected in series and two select gate transistors SGSTr and SGDTr connected to both ends thereof. The source side select gate transistor SGSTr is connected to the source line SRC, and the drain side select gate transistor SGDTr is connected to the bit line BL.

  As shown in FIG. 1, the NAND flash memory 100 includes a memory cell array MCA, a row decoder RD, a bit line control circuit BLC, a column decoder CD, a data input / output buffer IOB, an internal potential generation circuit IVG, An operation control circuit OC, an address buffer ADB, a word line potential control circuit WLC, a source / well potential control circuit SWC, a command buffer CMB, a collective verify circuit VFC, a page buffer PB, an input / output pad IOP, An input / output control circuit IOC and a voltage generation selection circuit VGSC are provided.

  The memory cell array MCA includes a plurality of memory cells respectively connected to a plurality of word lines WL extending in the row direction as the first direction and a plurality of bit lines BL extending in the column direction as the second direction. . The memory cell is provided corresponding to the intersection of the word line WL and the bit line BL. As shown in FIG. 2, a plurality of memory cells M are connected in series to form a NAND string.

  The row decoder RD includes a word line driving circuit, selects a word line of the memory cell array MCA according to the input address, and drives it.

  The bit line control circuit BLC includes a circuit that controls the potential of the bit line BL, and a sense amplifier S / A that senses the voltage of the bit line or the current flowing through the bit line during the verify read and read operations. The bit line control circuit BLC performs write control, verify read, and read operations by controlling the potential of the bit line BL. A NAND flash memory normally performs a write operation and a read operation in units of pages from 512 bytes to 8 Kbytes. That is, the bit line control circuit BLC can simultaneously control the bit lines BL corresponding to 512 bytes to 8 K bytes in the page. The memory cell M can store n-bit data (n is an integer of 2 or more). That is, the flash memory according to the present embodiment uses a multi-value technology. The sense amplifier S / A detects data in the memory cell M via the bit line BL.

  The page buffer PB includes a data latch circuit DL that stores read data or write data. The data latch circuit DL is a latch circuit that stores data stored in each of the memory cells M connected to the selected word line WL.

  The column decoder CD selects the bit line control circuit BLC connected to the bit line of the memory cell array MCA according to the input address. Normally, selection is performed in units of 1 byte. That is, the column decoder CD selects a bit line control circuit BLC connected to eight adjacent bit lines.

  The voltage generation selection circuit VGSC is configured to apply a voltage corresponding to the distance from the row decoder RD to the bit line BL to each bit line BL based on the row address during a data write operation. The voltage generation selection circuit VGSC includes a voltage generation circuit VGC and a voltage selection circuit VSC. Detailed descriptions of the voltage generation circuit VGC and the voltage selection circuit VSC will be described later.

  At the time of data reading, the data read to the bit line control circuit BLC is stored in the page buffer PB and further output from the input / output pad IOP via the data input / output buffer IOB.

  The internal potential generation circuit IVG boosts or lowers the power supply voltage to generate a voltage to be supplied to the bit line control circuit BLC, the control gate potential control circuit 9, the source / well potential control circuit SWC, and the like.

  The word line potential control circuit WLC controls the voltage applied to the word line WL (control gate of the memory cell) and supplies the voltage to the row decoder RD.

  The source / well potential control circuit SWC controls the potential of the cell well 103 on the semiconductor substrate and also controls the potential of the source line SRC.

  External control signals such as a chip enable signal CE, a write enable signal WE, a read enable signal RE, an address latch enable signal ALE, a command latch enable signal CLE are input to the input / output pad IOP from the outside of the chip, and a command code Is input, the command code is supplied to the command buffer CMB via the input / output control circuit IOC. The command buffer CMB decodes this command code and supplies it as a command signal to the operation control circuit OC.

  The operation control circuit OC performs data write / erase sequence control and data read control based on a command signal supplied according to the operation mode.

  The operation control circuit OC outputs signals for controlling various operations such as reading, writing, and erasing, whereby the bit line control circuit BLC, the internal potential generation circuit IVG, the word line potential control circuit WLC, and the source / well potential control The circuit SWC performs various operations. In addition, when the operation control circuit OC outputs a signal for controlling the verify operation, the verify circuit 12 performs the verify operation.

  The address of the memory cell M supplied from the input / output control circuit IOC is transferred to the row decoder RD and the column decoder CD via the address buffer ADB.

  The collective verify circuit VFC, based on the data stored in the page buffer PB at the time of verify read, sets the threshold value of all memory cells M in a page to be written or a block to be erased with respect to a predetermined memory cell M. It is determined whether the voltage has reached the verify level (whether it has been written or erased). The collective verify circuit VFC outputs the determined result to the operation control circuit OC. The operation control circuit OC controls the bit line control circuit BLC, the internal potential generation circuit IVG, the word line potential control circuit WLC, and the source / well potential control circuit SWC based on the result of the verification, and in the page to be written The write operation or the erase operation is continued until the threshold voltages of all the memory cells M in the erase target block reach the verify level (pass).

  FIG. 3 is a diagram illustrating the concept of blocks, pages, and the like of the memory cell array MCA. The memory cell array MCA is divided into memory cell blocks (hereinafter also referred to as blocks) BLOCK0 to BLOCKm. In this example, the blocks BLOCK0 to BLOCKm are the minimum units for data erasure. Each block BLOCK0 to BLOCKm is composed of a plurality of pages. A page is a unit of data reading or data writing. Each page corresponds to a word line and is configured by data of a plurality of memory cells specified by a certain row address. The ROM 120 stores setting information necessary for operations such as a write voltage set during a die sort test.

  FIG. 4 is a schematic diagram showing the arrangement of row decoders RD and word lines WL for memory cell array MCA. A plurality of row decoders RD are provided for each block on both sides of one memory cell array MCA. A row decoder disposed on the right side of the memory cell array MCA is referred to as RD_R, and a row decoder disposed on the left side thereof is referred to as RD_L (hereinafter, collectively referred to as RD). In FIG. 4, the word lines WL of one block, that is, 64 word lines WL0 to WL63 extend from the row decoders RD_R and RD_L. The NAND string NS extends in the column direction so that the gate of each memory cell M is connected to the word lines WL0 to WL63, respectively. The NAND string NS is connected to a bit line BL (not shown in FIG. 4) via select gate transistors SGSTr and SGDTr.

  As shown in FIG. 4, when the row decoder RD is arranged on both sides of the memory cell array MCA, the row decoder RD and the memory cell M are selected depending on which side of the row decoder RD is selected. The relationship between the distances is reversed.

  For example, when the right row decoder RD_R is selected, the rightmost bit line BL or memory cell M of the memory cell array MCA is closest to the row decoder RD_R. However, when the left row decoder RD_L is selected, the rightmost bit line BL or memory cell M of the memory cell array MCA is farthest from the row decoder RD_L. Therefore, the gradient of the voltage level of the word line WL varies depending on the arrangement position of the selected row decoder RD.

  In the following description, it is assumed that the row decoder RD_R is selected.

  Immediately after the start of writing, the gate voltage of the memory cell M near the row decoder RD_R is relatively high, and the gate voltage of the memory cell M far from the row decoder RD_R is relatively low. This is because the rise of the voltage of the word line WL is delayed (RC delay) at a position far from the row decoder RD_R because the word line WL has a resistance.

  Therefore, in the present embodiment, the voltage generation selection circuit VGSC applies a higher voltage to the bit line closer to the row decoder RD_R than to the bit line far from the row decoder RD_R based on the row address when data is written to the memory cell M. Apply. Thereby, the voltage difference of the word line WL caused by the difference in distance from the row decoder RD_R to the bit line BL (memory cell M) can be reduced.

  The write operation will be described with reference to FIGS. FIG. 5 is a timing diagram showing a write operation when the bit line BL0 is close to the row decoder RD_R. FIG. 6 is a conceptual diagram showing the NAND string NS selected in the write operation. FIG. 7 is a conceptual diagram showing a non-selected NAND string NS in the write operation.

  As shown in FIG. 5, at t0, the selection gate SGD is boosted to Vsg (for example, 4V). At this time, the selection gate transistor SGDTr is turned on. From t1 to t2, 0 V is applied to the bit line BL connected to the selected NAND string NS to be written. Vdd (for example, 2.5 V) is applied to the bit line BL connected to the non-selected NAND string NS that is not a write target. As a result, the channel region of the unselected NAND string NS is charged to Vdd. Note that 1.5 V is applied to the source line SRC, but it is disconnected from any NAND string NS.

  At t3, the selection gate SGD is set to Vsgd (for example, 2.5 V). Vsgd is a voltage closer to Vdd than Vsg. Thereby, the selection gate transistor SGDTr of the non-selected NAND string NS is turned off (see FIG. 7) while the selection gate transistor SGDTr of the selected NAND string NS is kept in the on state (see FIG. 6). As a result, the cell channel region of the unselected NAND string NS shown in FIG. 7 is in a floating state.

  Under this state, at t4, all word lines WL in the selected block are boosted to Vpass (for example, 10V). At this time, since the selected NAND string NS shown in FIG. 6 is connected to the bit line BL0, the potential of the cell channel region is maintained at 0V. At this time, all the memory cells MC in the selected NAND string NS are turned on.

  On the other hand, since the unselected NAND string NS shown in FIG. 7 is disconnected from the bit line BL1, the potential of the cell channel region rises due to capacitive coupling between the word line WL and the cell channel region. For example, the potential of the cell channel region of the unselected NAND string NS rises to 7V.

  At t5, the selected word line WLm is boosted to Vpgm (for example, 20V). At this time, in the selected NAND string NS shown in FIG. 6, the potential of the cell channel region is still maintained at 0V. As a result, a potential difference of Vpgm is applied between the selected word line WLm and the channel region of the selected memory cell MC0, and electrons are injected into the floating gate FG. As a result, data “0” is written into the selected memory cell MC0.

  On the other hand, in the non-selected NAND string NS shown in FIG. 7, since the potential of the cell channel region is increased, the larger the potential difference becomes as the electrons are injected into the floating gate FG, the cell channel region of the selected word line WLm and the memory cell MC1. Not applied between. As a result, data “0” is not written in the unselected NAND string NS. That is, data is maintained in the non-selected NAND string NS.

  In FIG. 6, the unselected memory cell to which Vpass is applied is turned on. However, a voltage difference that is so large that writing is executed is not applied between the control gates of the non-selected memory cells other than MC0 and the channel region. Since the non-selected memory cell between the selected bit line BL0 and the selected memory cell MC0 is turned on, the voltage (ground potential) of the selected bit line BL0 passes through the non-selected memory cell and the drain of the selected memory cell M. Can be applied.

  When such a write operation is executed for all bit lines, the rising of the selected word line WLm is delayed as the distance between the row decoder RD and the selected bit line BL (selected memory cell M) increases.

  If the voltages of all the bit lines BL0 are fixed to the ground potential as before, when the selected memory cell M is close to the row decoder RD_R, the program voltage Vpgm is set between the control gate (word line WL) and the channel immediately after the start of writing. It can be applied in between. However, when the selected memory cell M is far from the row decoder RD_R, immediately after the start of writing, a voltage smaller than the program voltage Vpgm is applied between the control gate (word line WL) and the channel. As a result, data “0” is sufficiently written in the memory cell M close to the row decoder RD_R, but data “0” may not be sufficiently written in the memory cell M far from the row decoder RD_R. In particular, this problem becomes significant when the write operation is performed at high speed (in a short time).

  In this embodiment, as shown in FIG. 8, the voltage generation selection circuit VGSC applies a ground potential to the bit line BL close to the row decoder RD_R and is higher than the ground potential to the bit line BL far from the row decoder RD_R. Apply voltage.

  FIG. 8 is a graph showing the voltage of the selected word line WL and the voltage of the bit line BL0 when data “0” is written. The horizontal axis is time. Although only two types of voltages of the bit line BL0 are shown, n types (n is an even number of 2 or more) may be used. In this case, the voltage generation selection circuit VGSC generates first to nth voltages Vsrc_1 to Vsrc_n as will be described later.

  t = 0 indicates the start time of the write operation (when the write enable WE is activated). The solid line indicates the voltage of the word line WLm portion close to the row decoder RD_R and the voltage of the bit line BL0. A broken line indicates the voltage of the word line WLm portion far from the row decoder RD_R and the voltage of the bit line BL0.

  The voltage of the bit line BL0 far from the row decoder RD_R is set to Vbl of 0V or more. Vbl may be, for example, a voltage (for example, 0.4 V) applied to the bit line BL0 at the time of reading. As a result, variation in potential difference between the selected word line WLm and the bit line BL0 caused by the distance between the row decoder RD_R and the bit line BL can be reduced.

  9 and 10 are circuit diagrams showing the internal configuration of the voltage generation selection circuit VGSC. FIG. 9 shows the voltage generation circuit VGC, and FIG. 10 shows the voltage selection circuit VSC.

  The voltage generation circuit VGC includes a plurality of resistors R connected in series between an external power supply VDD as a first reference voltage source and a ground potential as a second reference voltage source. The constant current source CC supplies a constant current I from the external power supply VDD. The ground potential external power supply VDD is divided by a plurality of resistors R and converted into first to nth (n is an even number of 2 or more) voltages Vsrc_1 to Vsrc_n. As k (1 ≦ k ≦ n) increases, the voltage values of the first to n-th voltages Vsrc_1 to Vsrc_n increase. That is, the first to nth voltages Vsrc_1 to Vsrc_n increase in ascending order.

  The voltage selection circuit VSC shown in FIG. 10 includes first to n-th switching elements SW1 to SWn that output one of two inputs based on a row address designating a selected word line WLm. One input of each of the first to n-th switching elements SW1 to SWn receives the first to n-th voltages Vsrc_1 to Vsrc_n in ascending order, respectively. The other inputs of the first to n-th switching elements SW1 to SWn receive the first voltages Vsrc_n to Vsrc_1 in descending order from the n-th voltage, respectively. That is, the first switching element SW1 receives the first voltage Vsrc_1 and the nth voltage Vsrc_n, the second switching element SW2 receives the second voltage Vsrc_2 and the n−1th voltage Vsrc_n−1, The third switching element SW3 receives the third voltage Vsrc_3 and the (n-2) th voltage Vsrc_n-2. By repeating this similarly, the n-th switching element SWn receives the n-th voltage Vsrc_n and the first voltage Vsrc_1.

  The first to n-th switching elements SW1 to SWn output one of the two inputs as source ground voltages SRCGND_1 to SRCGND_n. The voltages SRCGND_1 to SRCGND_n are voltages applied to the bit line BL when data “0” is written.

  The voltage selection circuit VSC receives the first to nth voltages Vsrc_1 to Vsrc_n from the voltage generation circuit VGC, and in order from the bit line close to the row decoder RD_R to the bit line far from the row decoder RD_R based on the row address. Are connected to first to nth voltages Vsrc_1 to Vsrc_n, respectively.

  Each of the first to n-th switching elements SW1 to SWn is composed of two CMOS (Complementary Metal Oxide Semiconductor) switches. The two CMOS switches are controlled by the least significant bit ROWADD <0> of the row address and its inverted signal ROWADDn <0>. When one of the two CMOS switches in a switching element is in a conductive state, the other is in a non-conductive state, and the two have a complementary relationship.

  As shown in FIG. 4, the row decoders RD_R and RD_L are provided on both sides of the memory cell array MCA. For example, when the 10-bit row address is odd (the least significant bit ROWADD <0> is “0”), the right row decoder RD_R is selected and the row address is even (the least significant bit ROWADD <0> is “1”). In this case, the left row decoder RD_L is selected.

  When ROWADD <0> is “0” (LOW), the switching elements SW1 to SWn respectively output the first to nth voltages Vsrc_1 to Vsrc_n (in ascending order) as voltages SRCGND_1 to SRCGND_n. When ROWADD <0> is “1” (HIGH), the switching elements SW1 to SWn output the nth to first voltages Vsrc_n to Vsrc_1 as the voltages SRCGND_1 to SRCGND_n (in descending order), respectively.

  FIGS. 11A and 11B are diagrams showing an arrangement relationship between the voltage selection circuit VSC and the sense amplifier S / A. As shown in FIG. 11A, the voltage selection circuit VSC may supply the voltages SRCGND_1 to SRCGND_n from one side of the sense amplifier S / A. Alternatively, the voltage selection circuit VSC may supply the voltages SRCGND_1 to SRCGND_n from both sides of the sense amplifier S / A, as shown in FIG. In this case, the voltage selection circuit VSC is divided and arranged in half on both sides of the sense amplifier S / A. For example, if the switching elements SW1 to SW (n / 2) shown in FIG. 10 are arranged on the left side of the sense amplifier S / A and the switching elements SW (n / 2 + 1) to SWn are arranged on the right side of the sense amplifier S / A. Good.

  The voltages SRCGND_1 to SRCGND_n may be provided corresponding to each individual bit line BL. Alternatively, the voltages SRCGND_1 to SRCGND_n may be provided corresponding to a plurality of bit lines BL (for example, for each write block).

  FIG. 12 is a circuit diagram showing an example of the internal configuration of the sense amplifier S / A. The voltages SRCGND_1 to SRCGND_n are connected to the corresponding bit line BL via the transistor T1. The external power supply VDD having a high level potential is connected to the bit line BL via the transistor T2. The latch circuit LC stores the write data input from the BUS in the node LAT.

  The transistors T1 and T2 operate according to the data latched by the latch circuit LC. For example, when the data stored in the latch circuit LC is “1”, that is, when the node LAT is logic high, the node INV becomes logic low. Therefore, the transistor T1 is turned off and the transistor T2 is turned on. As a result, the power supply VDD is connected to the bit line BL, and data “1” is written into the memory cell M.

  On the contrary, when the data stored in the latch circuit LC is “0”, that is, when the node LAT is logic low, the node INV becomes logic high. Accordingly, the transistor T1 is turned on and the transistor T2 is turned off. As a result, the voltages RCGND_1 to SRCGND_n are connected to the bit line BL, and data “0” is written to the memory cell M. At this time, the voltage generation selection circuit VGSC described above determines the voltages RCGND_1 to SRCGND_n according to the distance between the row decoder RD_R and the bit line BL.

  With the above configuration, when driving the row decoder RD_R, the voltage selection circuit VSC sequentially increases from the first bit line BL toward the right bit line BL from the left bit line BL of the memory cell array MCA. n voltages Vsrc_1 to Vsrc_n are connected to the bit line BL. On the other hand, when driving the row decoder RD_L, the voltage selection circuit VSC sequentially increases from the first bit line BL to the left bit line BL from the right bit line BL of the memory cell array MCA. The voltages Vsrc_1 to Vsrc_n are connected to the bit line BL.

  According to the present embodiment, the potential level of the bit line BL can be changed in accordance with the distance between the selected memory cell and the row decoder RD in consideration of the rise of the voltage of the word line WL during data writing. it can. Thereby, variation in potential difference between the selected word line WLm and the bit line BL0 due to the distance between the row decoder RD and the bit line BL can be reduced. As a result, even if the resistance of the word line increases and the rise delay becomes significant, the spread (variation) of the threshold distribution of the memory cell M can be suppressed.

  When n is the minimum value 2, one resistor R in FIG. 9 is sufficient. Two switching elements (SW1 and SW2) in FIG. 10 are sufficient. Therefore, there are two types of bit line BL voltages at the time of writing, SRCGND_1 and SRCGND_2. In this case, the voltage generation selection circuit VGSC controls the voltage by dividing the plurality of bit lines BL into two, a side closer to the row decoder RD and a side far from the row decoder RD. Thus, when n is small, the circuit scale of the voltage generation selection circuit VGSC can be reduced.

(Second Embodiment)
FIGS. 13A and 13B are configuration diagrams of the sense amplifier S / A and the voltage selection circuit VSC in the second embodiment. In the second embodiment, short-circuit switches SW1 to SW (n−1) are provided between wires that transmit the source ground voltages SRCGND_1 to SRCGND_n. The short-circuit switches SW1 to SW (n−1) are controlled by a signal Sa as a first control signal. The signal Sa is a signal that is activated after a predetermined time t1 has elapsed since the activation of the write enable signal WE that permits data writing to the memory cell M.

  The short-circuit switches SW1 to SW (n−1) are arranged in the shunt region in the sense amplifier S / A. The shunt region is a region provided for connecting the select gates SGD and SGS and the source line SRC to a lower-resistance metal wiring (not shown) above it. Thereby, the short-circuit switches SW1 to SW (n-1) can be provided without increasing the chip size.

  FIG. 14 is a circuit diagram showing a configuration of the voltage generation circuit VGC in the second embodiment. The voltage generation circuit VGC includes a plurality of resistors R connected in series between the external voltage source VDD and the ground potential, and a power switch SWp connected between the external voltage source VDD and the plurality of resistors R. I have. The power switch SWp is controlled by a second control signal San having a logic opposite to that of the first control signal Sa. The power switch SWp can connect or disconnect between the external voltage source VDD (constant current source CC) and the resistor R. If the external voltage source VDD is disconnected from the resistor R by turning off the power switch SWp, the first to nth voltages Vsrc_1 to Vsrc_n all become the ground potential.

  FIG. 15 is a configuration diagram of the control signal generation circuit SCG that generates the control signal Sa. The control signal generation circuit SCG is configured by connecting a plurality of inverter circuits in series. The control signal generation circuit SCG receives the write enable signal WE, delays the write enable signal WE by a plurality of inverter circuits, and outputs the delayed signal as the control signal Sa. That is, the control signal generation circuit SCG is configured by a delay circuit.

  The control signal Sa is activated after a predetermined time t1 has elapsed since the start of writing (activation of the write enable signal WE). When the control signal Sa is activated (when the control signal San is deactivated), the short-circuit switches SW1 to SW (n−1) shown in FIG. 13 are turned on, and the power switch SWp shown in FIG. Non-conducting state. As a result, the voltages SRCGND_1 to SRCGND_n are all short-circuited and become the ground potential (0 V).

  Other configurations of the second embodiment may be the same as those of the first embodiment.

  FIG. 16 is a graph showing the voltage of the selected word line WLm and the voltage of the bit line BL0 when data “0” is written. The operations of the selected word line WLm and the bit line BL0 from 0 to t1 are the same as those operations shown in FIG.

  At t1, the control signal Sa is activated, so that the voltages SRCGND_1 to SRCGND_n all become the ground potential (0 V). At the beginning of writing, the difference between the voltage of the word line WLm near the row decoder and the voltage of the word line WLm far from the row decoder is large, but thereafter, the voltage of the word line WLm far from the row decoder with time. Approaches the program voltage Vpgm. When the voltage difference in the word line WLm portion becomes smaller than ΔV, it is not necessary to raise the voltage of the bit line BL close to the row decoder RD_R (or RD_L) to Vbl. Accordingly, at time t1 when the voltage difference in the word line WLm portion becomes smaller than ΔV, the short-circuit switches SW1 to SW (n−1) short-circuit the voltages of all the bit lines BL, and the power switch SWp is connected to all the bit lines. The voltage of BL is fixed to the ground potential. ΔV may be any voltage in the range of 0 to Vbl. The time point t1 is set according to the value of ΔV.

  With such a configuration and operation, variation in potential difference between the selected word line WLm and the bit line BL0 can be further suppressed. As a result, the spread of the threshold distribution of the memory cell M can be further narrowed. Further, the second embodiment can obtain the same effects as those of the first embodiment.

MCA ... memory cell array, RD ... row decoder, VGSC ... voltage generation selection circuit, VGC ... voltage generation circuit, VSC ... voltage selection circuit, BL ... bit line, WL ... word line, M ... memory cell, Vpgm ... program voltage, R ... Resistance, CC ... Constant current source, SW1 to SWn ... Switching element, SWs1 to SWs (n-1) ... Short-circuit switch, SWp ... Power switch, CSG ... Control signal generation circuit

Claims (5)

A plurality of word lines extending in a first direction;
A plurality of bit lines extending in a second direction intersecting the first direction;
A memory cell array including a plurality of memory cells provided corresponding to the intersections of the word lines and the bit lines;
A row decoder for driving a selected word line among the plurality of word lines;
A sense amplifier for detecting data of the memory cell via the bit line;
A voltage generator that generates first to nth (n is an even number of 2 or more) voltages that increase in ascending order;
At the time of data writing to the memory cell, based on a row address designating any one of the word lines, the first bit line in order from the bit line close to the row decoder to the bit line far from the row decoder. To a voltage selection section for connecting the nth voltage respectively. At least two of the row decoders are provided on both sides of the memory cell array;
The plurality of word lines extend from the two row decoders, respectively.
The row address determines which side of the memory cell array the row decoder is selected,
The voltage selection unit connects the first to nth voltages in order from the bit line close to the row decoder on the side selected by the row address to the bit line far from the row decoder. The semiconductor memory device according to claim 1. The voltage selection unit includes first to n-th switching elements that output one of two inputs based on the row address,
One input of each of the first to nth switching elements receives the nth voltage from the first voltage, respectively.
3. The semiconductor memory device according to claim 1, wherein the other input of each of the first to n-th switching elements receives the first voltage from the n-th voltage, respectively. A plurality of short-circuit switches for electrically short-circuiting the wiring for transmitting the n-th voltage from the first voltage;
A control signal generation unit that activates a first control signal for controlling the plurality of short-circuit switches after a predetermined time has elapsed since activation of a write enable signal that permits writing of data to the memory cell;
4. The semiconductor memory device according to claim 1, wherein the short-circuit switch is turned on when the first control signal is activated. 5. The voltage generator is connected between a plurality of resistors connected in series between a first reference voltage source and a second reference voltage source, and between the first reference voltage source and the plurality of resistors. A power switch controlled by a second control signal having an opposite logic to the first control signal,
5. The semiconductor memory device according to claim 4, wherein the power switch is brought into a non-conducting state by inactivation of the second control signal.

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