CN107045886A - 非易失性存储器 - Google Patents

非易失性存储器 Download PDF

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CN107045886A
CN107045886A CN201710025661.3A CN201710025661A CN107045886A CN 107045886 A CN107045886 A CN 107045886A CN 201710025661 A CN201710025661 A CN 201710025661A CN 107045886 A CN107045886 A CN 107045886A
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signal
circuit
pulse
nonvolatile memory
pmos transistor
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CN107045886B (zh
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赖子能
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eMemory Technology Inc
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eMemory Technology Inc
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    • G11C16/105—Circuits or methods for updating contents of nonvolatile memory, especially with 'security' features to ensure reliable replacement, i.e. preventing that old data is lost before new data is reliably written
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Abstract

本发明为一种非易失性存储器包括：一存储单元阵列与一控制电路。存储器阵列具有多条字线与多条位线。控制电路包括：一处理电路、一解码器、一驱动器、一时序控制器与一感测放大器。解码器连接至该处理电路。驱动器连接至该解码器与该多条字线。一时序控制器连接至该处理电路。感测放大器连接至该解码器、该时序控制器与该多条字线。

Description

非易失性存储器
技术领域
本发明关于一种非易失性存储器，且特别关于一种具时序控制器的非易失性存储器。
背景技术
众所周知，非易失性存储器中包括一存储单元阵列(memory array)，存储单元阵列由多个存储单元(memory cell)排列而成，而每个存储单元中均包含一浮动栅晶体管(floating gate transistor)。
另外，非易失性存储器中还包括一控制电路(controlling circuit)，用以控制存储单元阵列进行编程动作、读取动作、或者擦除动作。
因此，非易失性存储器在执行各种动作时，控制电路会依序产生各种信号至存储单元阵列。如果这些信号的时序出现错误，则会发生运作失败(fail)的状况。
发明内容
本发明的主要目的为提出一种非易失性存储器，包括：一存储单元阵列，具有多条字线与多条位线；以及一控制电路，连接至该多条字线与该多条位线，其中该控制电路包括：一处理电路，在一时钟信号的一第一信号沿产生一读取指令；一解码器，连接至该处理电路，用以接收该处理电路产生的该读取址令，并产生一地址信号；一驱动器，连接至该多条字线，并根据该地址信号来驱动该多条字线其中之一；一时序控制器，连接至该处理电路，在该处理电路产生该读取址令时，依序产生一预充电信号与一重置信号；以及一感测放大器，连接至该多条字线，其中，在该预充电信号动作时，将该多条位线调整至第一预定电压；且在该重置信号动作时，根据该地址信号从该多条位线中决定一选定位线组，并将该选定位线组调整至一第二预定电压；其中，该解码器由一第一类型元件所组成，该时序控制器由该第一类型元件与一第二类型元件所组成。
为了对本发明的上述及其他方面有更佳的了解，下文特举较佳实施例，并配合附图，详细说明如下：
附图说明
图1为本发明非易失性存储器示意图。
图2A所绘示为非易失性存储器中的相关信号示意图。
图2B为时序控制器示意图。
图2C为前级脉冲产生电路示意图。
图3为制程变化时非易失性存储器中的相关信号示意图。
图4A所绘示为本发明第二实施例的时序控制器。
图4B所绘示为本发明非易失性存储器中的相关信号示意图。
图5所绘示本发明第二脉冲产生器的一个范例。
符号说明
100：非易失性存储器
110：存储单元阵列
150：控制电路
152：处理电路
154：解码器
156：驱动器
160：时序控制器
161：前级脉冲产生电路
162：感测放大器
163、221、223：非门
164：或非门
165、220：延迟电路
168：次级脉冲产生电路
172：第一脉冲产生器
174：第二脉冲产生器
176：或门
210：逻辑电路
222：第一反相电路
224：第二反相电路
具体实施方式
请参照图1，其所绘示为本发明非易失性存储器示意图。非易失性存储器100包括：一存储单元阵列110与一控制电路150。再者，控制电路150中包括：一处理电路(processingcircuit)152、解码器(decoder)154、驱动器(driver)156、时序控制器(timingcontroller)160、与感测放大器(sense amplifier)162。
控制电路150中，处理电路152连接至解码器154，而解码器154连接至驱动器156与感测放大器162。另外，处理电路152连接至时序控制器160，而时序控制器160连接至感测放大器162。
再者，存储单元阵列110具有m条字线WL0～WLm-1以及n条位线BL0～BLn-1。其中，驱动器156连接至存储单元阵列110的位线WL0～WLm-1，感测放大器162连接至存储单元阵列110的字线BL0～BLn-1。
以下介绍非易失性存储器100的读取动作流程。基本上，非易失性存储器100会根据一时钟信号CLK来运作。在进行读取动作时，处理电路152会将读取指令(read command)传送至解码器154，而解码器154解码(decode)读取指令后产生一地址信号Addr。再者，驱动器156根据地址信号Addr来驱动m条字线WL0～WLm-1中的一特定字线。另外，感测放大器162根据地址信号Addr，在n条位线BL0～BLn-1中决定一选定位线组(selected bit lineset)，并且对选定位线组进行感测动作，以产生读取数据(read data)。
举例来说，当地址信号Addr产生后，驱动器156驱动字线WL1。因此，存储单元阵列110中连接至字线WL1上的n个存储单元会被驱动。而字线WL1上的n个存储单元对应地连接至n条位线BL0～BLn-1。
再者，感测放大器162根据地址信号Addr，决定位线BL0～BL7为选定位线组。因此，感测放大器162即感测位线BL0～BL7上的电压变化，并进而决定位线BL0～BL7上的逻辑电平作为读取数据。换言之，读取数据即代表连接至字线WL1上前八个存储单元的储存状态。
另外，在解码器154产生地址信号Addr的过程，感测放大器162需要根据时序控制器160的预充电信号Precharge以及重置信号Reset来动作位线，才可正确地产生读取数据。
请参照图2A，其所绘示为非易失性存储器中的相关信号示意图。图2B为时序控制器示意图。第2C图为前级脉冲产生电路示意图。
如图2A所示，在时间点t1，在时钟信号CLK的上升沿，处理电路152将读取指令传送至解码器154。同时，处理电路152控制时序控制器160产生预充电信号Precharge至感测放大器162。
时间点t1至时间点t2之间为预充电周期(precharge period)。在时间点t1，时序控制器160产生一个脉冲(pulse)的预充电信号Precharge至感测放大器162，且预充电信号Precharge的脉冲宽度(pulse width)即代表该预充电周期。
在预充电周期内，解码器154解码读取指令并产生地址信号Addr。而感测放大器162根据预充电信号Precharge，在预充电周期内将所有的位线BL0～BLn-1预充电至第一预定电压(first predetermined voltage)。举例来说，预充电周期为10ns，第一预定电压为3.0V。
时间点t2至时间点t3之间为重置周期(reset period)。在时间点t2，时序控制器160根据预充电信号Precharge的下降沿，产生一个脉冲的重置电信号Reset至感测放大器162，且重置信号Reset的脉冲宽度即代表该重置周期。
在重置周期内，而感测放大器162根据地址信号Addr在位线BL0～BLn-1之中决定选定位线组，并重置该选定位线组至一第二预定电压，而其他的位线则维持在第一预定电压。举例来说，重置周期为10ns。再者，第一预定电压不同于第二预定电压，且第二预定电压为，例如，接地电压(ground voltage)。
在时间点t3之后即为发展与感测周期(developing and sensing period)。在发展与感测周期，连接于选定位线组的对应存储单元会产生存储单元电流(cell current)至感测放大器162。而根据存储单元不同的储存状态，会有不同大小的存储单元电流作为充电电流(charge current)。
因此，在发展与感测周期，选定位线组上的电压会由第二电压(例如接地电压)开始变化，而感测电放大器162即根据每条位线的电压变化大小来决定选定位线组上的逻辑电平，并作为读取数据。
如图2B所示，为了让时序控制器160能够产生预充电信号Precharge以及重置信号Reset。本发明第一实施例的时序控制器160包括一前级脉冲产生电路(primary pulsegenerating circuit)161与次级脉冲产生电路(secondary pulse generating circuit)168。
前级脉冲产生电路161接收时钟信号CLK，并根据时钟信号CLK的上升沿(risingedge)产生预充电信号Precharge。另外，次级脉冲产生电路168接收预充电信号Precharge，并根据预充电信号Precharge的下降沿(falling edge)产生重置信号Reset。因此，时序控制器160即可依序产生一个脉冲的预充电信号Precharge以及一个脉冲的重置信号Reset。
图2C为前级脉冲产生电路161的一个范例。前级脉冲产生电路161包括一逻辑电路与一延迟电路(delaying circuit)165，而逻辑电路包括一非门163与一或非门164。其中，非门163接收时钟信号CLK产生反相的时钟信号CLKb；延迟电路(delaying circuit)165接收时钟信号CLK，延迟时间T之后，产生延迟的时钟信号CLKd。或非门164接收反相的时钟信号CLKb与延迟的时钟信号CLKd，并产生脉冲宽度为T的预充电信号Precharge。同理，次级脉冲产生电路168也可以利用类似的逻辑电路与延迟电路来产生重置信号Reset，此处不再赘述。
再者，由于存储单元阵列110需要较高的操作电压(operation voltage)，因此解码器154与驱动器156需要利用高耐压的元件(device)来实现，例如高耐压的PMOS晶体管与NMOS晶体管。而时序控制器160与感测放大器162则利用低耐压的元件来实现，例如低耐压的PMOS晶体管与NMOS晶体管。
另外，在半导体制程中，可制造出两种不同耐压类型的元件。第一种类型的元件为高耐压的元件，又称为I/O元件(I/O device)，其需要较高的第一操作电压，例如6V。另外，第二种类型的元件为低耐压的元件，又称为核心元件(core device)，其需要较低的第二操作电压，例如1.2V。换言之，I/O元件(I/O device)与核心元件(core device)需分别连接至不同的电源域(power domain)。
众所周知，由于集成电路的制程参数变化(variation of fabricationparameters)，会产生各种工艺角(process corner)的元件，并导致不同的运作速度。举例来说，快速-快速角(fast-fast corner，简称FF corner)的元件、典型-典型角(typical-typical corner，简称TT corner)的元件、或者慢速-慢速角(slow-slow corner，简称SScorner)的元件。
典型-典型角(TT corner)的元件，其NMOS晶体管与PMOS晶体管的运作速度(operation speed)符合设计的要求(requirement)。快速-快速角(FF corner)的元件，其NMOS晶体管与PMOS晶体管的运作速度较设计的要求还要快速。慢速-慢速角(SS corner)的元件，其NMOS晶体管与PMOS晶体管的运作速度较设计的要求还要慢速。
非易失性存储器100的控制电路150中包括I/O元件所组成的解码器154与驱动器165，以及核心元件所组成的时序控制器160、感测放大器162。而慢速-慢速角(SS corner)的I/O元件可能造成非易失性存储器100读取失败的发生。说明如下：
请参照图3，其所绘示为制程变化时非易失性存储器中的相关信号示意图。
假设解码器154的I/O元件为典型-典型角(TT corner)的元件时，解码器154可在预充电周期内(t1～t2)动作地址信号Addr，如曲线<I>。
再者，当解码器154的I/O元件为快速-快速角(FF corner)的元件时，则地址信号Addr的动作时间会往前移动。反之，当解码器154的I/O元件为慢速-慢速角(SS corner)的元件时，则地址信号Addr的动作时间会往后移动。
在正常运作时，解码器154会在预充电周期内产生地址信号Addr，而感测放大器162会在重置周期内，根据地址信号Addr进一步地决定选定位线组，并重置该选定位线组至一第二预定电压。而进入发展与感测周期时，感测放大器162即可产生读取数据。
然而，由于无法精准地控制集成电路的制程参数，如果解码器154由慢速-慢速角(SS corner)的I/O元件所组成，且解码器154在重置周期之后才产生地址信号Addr，如曲线<II>所示。则感测放大器162在重置周期会决定出错误的选定位线组，并导致感测放大器162在发展与感测周期中产生错误的读取数据，造成非易失性存储器100的读取失败(readfail)而无法正常运作。
由以上的说明可知，造成读取失败的原因在于制程变化，并使得解码器154由慢速-慢速角(SS corner)的元件所组成，导致解码器154无法在预定周期(预充电周期)产生地址信号Addr。再者，由于时序控制器160无法响应上述制程变化，进而导致读取失败。
请参照图4A，其所绘示为本发明第二实施例的时序控制器。时序控制器160包括一前级脉冲产生电路161与次级脉冲产生电路168。
相同的运作原理，前级脉冲产生电路161接收时钟信号CLK，并根据时钟信号CLK的上升沿(rising edge)产生预充电信号Precharge。次级脉冲产生电路168接收预充电信号Precharge，并根据预充电信号Precharge的下降沿(falling edge)产生重置信号Reset。因此，时序控制器160即依序产生一个脉冲的预充电信号Precharge以及一个脉冲的重置信号Reset。
本实施例的第二实施例在于前级脉冲产生电路161包括一第一脉冲产生器(pulsegenerator)172与第二脉冲产生器174。其中，第一脉冲产生器172由核心元件(coredevice)所组成，而第二脉冲产生器174由I/O元件(I/Odevice)所组成。另外，第一脉冲产生器172与第二脉冲产生器174的电路结构类似图2C，均具有一逻辑电路与一延迟电路，各自可产生脉冲宽度为T的脉冲。
由于控制电路150中的解码器154与时序控制器160制作于相同的集成电路(IC)上。因此，在制作I/O元件时，若发生制程变化时，则会同时影响到解码器154与时序控制器160中的第二脉冲产生器174。换言之，如果制程变化造成解码器154由慢速-慢速角(SScorner)的元件所组成，则第二脉冲产生器174也会由慢速-慢速角(SS corner)的元件所组成。
虽然第二脉冲产生器174预计产生脉冲宽度为T的脉冲，但由于第二脉冲产生器174由慢速-慢速角(SS corner)的元件所组成，将会使得第二脉冲产生器174的脉冲宽度大于T。而第二脉冲产生器174的脉冲宽度相关于慢速-慢速角(SS corner)的元件特性。即，当第二脉冲产生器174中的I/O元件特性越差时，其产生的脉冲宽度会越宽。
在上述的情况下，如图4A所示，第一脉冲产生器产生脉冲宽度为T的第一信号P1，第二脉冲产生器产生脉冲宽度为T’的第二信号P2。因此，经过或门176后，前级脉冲产生电路161即产生脉冲宽度为T’的预充电信号。换言之，或门176可视为一决定电路，将第一信号P1与第二信号P2中脉冲宽度较大的脉冲作为预充电信号Precharge。
请参照图4B，其所绘示为本发明非易失性存储器中的相关信号示意图。其中，解码器154与时序控制器160均由慢速-慢速角(SS corner)的元件所组成。
在时间点ta，在时钟信号CLK的上升沿，处理电路152将读取指令传送至解码器154。同时，处理电路152控制时序控制器160产生预充电信号Precharge至感测放大器162。
时间点ta至时间点tb之间为预充电周期(precharge period)。由于解码器154延后产生地址信号Addr，而时序控制器160也对应地延长预充电信号Precharge的脉冲宽度为T’。因此，预充电周期会被延长，使得解码器154仍在预充电周期内产生地址信号Addr。
因此，在时间点tb至时间点tc之间的重置周期。感测放大器162即可根据地址信号Addr在位线BL0～BLn-1之中决定选定位线组，并重置该选定位线组至一第二预定电压，而其他的位线则维持在第一预定电压。
而在时间点tc之后的发展与感测周期。连接于选定位线组的对应存储单元会产生存储单元电流(cell current)至感测放大器162。而感测电放大器162即可根据每条位线的电压变化大小来决定选定位线组上的逻辑电平，并作为读取数据。
另外，如果解码器154与第二脉冲产生器174由典型-典型角(TT corner)的元件所组成，则第二脉冲的脉冲宽度为T。再者，如果解码器154第二脉冲产生器174由快速-快速角(FF corner)的元件所组成，则第二脉冲的脉冲宽度为小于T。在以上的两种情况下，经由或门176后，前级脉冲产生电路162仍产生脉冲宽度为T的预充电信号Precharge。
根据以上说明可知，本发明的优点在于提出一种运用于非易失性存储器中的时序控制器。时序控制器160中包括由核心元件所构建而成的第一脉冲产生器172与I/O元件所构建而成的第二脉冲产生器174。
根据制程变化，当解码器154与第二脉冲产生器174由慢速-慢速角(SS corner)所构建而成时，第二脉冲产生器174可以改变输出脉冲的脉冲宽度，用以改变预充电信号Precharge的脉冲宽度以及预充电周期。如此，将可以确保解码器154在预充电周期内产生的地址信号Addr，并使得感测放大器162正确地产生读取数据。
请参照图5，其所绘示本发明第二脉冲产生器174的一个范例，且第二脉冲产生器174均由I/O元件所组成。第二脉冲产生器174包括一逻辑电路210与一延迟电路220。其中，延迟电路220接收时钟信号CLK，延迟时间T之后，产生延迟的时钟信号CLKd。再者，逻辑电路210接收时钟信号CLK与延迟的时钟信号CLKd，并产生第二信号P2。
基本上，逻辑电路210可以有各种实现的方式。例如，逻辑电路210可包括一非门与一或非门，依照图2C的连接方式，即可产生第二信号P2。
再者，延迟电路220包括串接的一第一反相电路(inverting circuit)222与一第二反相电路224。第一反相电路222具有一输入端接收该时钟信号。第二反相电路224具有一输入端连接至第一反相电路222的输出端，第二反相电路224并且具有一输出端产生延迟的时钟信号CLKd。
第一反相电路222中包括PMOS晶体管p1、NMOS晶体管n1、电容器c1与缓冲器(buffer)221；第二反相电路224中包括PMOS晶体管p2、NMOS晶体管n2、电容器c2与缓冲器(buffer)223。经由控制电容器c1、c2的电容值，即可控制延迟电路220的延迟时间，并进一步地改变第二信号P2的脉冲宽度。
该第一反相电路222包括：第一PMOS晶体管p1，具有一源极连接至一电压源Vdd，一栅极连接至该第一反相电路222的该输入端；第一NMOS晶体管n1，具有一源极连接至一接地端，一栅极连接至该第一反相电路222的该输入端，一漏极连接至该第一PMOS晶体管p1的一漏极；一第一电容器c1，具有一第一端连接至该第一PMOS晶体管p1的该漏极，一第二端连接至该接地端；以及一第一缓冲器221，具有一输入端连接至该第一PMOS晶体管p1的该漏极，一输出端作为该第一反相电路222的该输出端。
该第二反相电路224包括：一第二PMOS晶体管p2，具有一源极连接至该电压源Vdd，一栅极连接至该第一反相电路222的该输出端；一第二NMOS晶体管n2，具有一源极连接至该接地端，一栅极连接至该第一反相电路222的该输出端，一漏极连接至该第二PMOS晶体管p2的一漏极；一第二电容器c2，具有一第一端连接至该第二PMOS晶体管p2的该漏极，一第二端连接至该接地端；以及一第二缓冲器223，具有一输入端连接至该第二PMOS晶体管p2的该漏极，一输出端作为该第二反相电路224的该输出端。
再者，本发明还可以设计第一反相电路222中的PMOS晶体管p1为一弱PMOS晶体管(weak PMOS transistor)而第二反相电路224中NMOS晶体管n2为一弱NMOS晶体管(weakNMOS transistor)。如此，可以让第二脉冲产生器174的脉冲宽度更相关于慢速-慢速角(SScorner)的元件特性。当然，也可以设计第一反相电路222中的NMOS晶体管n1为一弱NMOS晶体管而第二反相电路224中PMOS晶体管p2为一弱PMOS晶体管。
综上所述，虽然本发明已以较佳实施例公开如上，然其并非用以限定本发明。本发明所属技术领域中技术人员，在不脱离本发明的精神和范围内，可以做出各种更动与润饰。因此，本发明的保护范围应当视所附权利要求书所界定者为准。

Claims (13)

1.一种非易失性存储器，包括：
一存储单元阵列，具有多条字线与多条位线；以及
一控制电路，连接至该多条字线与该多条位线；
其中，该控制电路包括：
一处理电路，在一时钟信号的一第一信号沿产生一读取指令；
一解码器，连接至该处理电路，用以接收该处理电路产生的该读取指令，并产生一地址信号；
一驱动器，连接至该多条字线，并根据该地址信号来驱动该多条字线其中之一；
一时序控制器，连接至该处理电路，在该处理电路产生该读取指令时，依序产生一预充电信号与一重置信号；以及
一感测放大器，连接至该多条字线，其中，在该预充电信号动作时，将该多条位线调整至第一预定电压；且在该重置信号动作时，根据该地址信号从该多条位线中决定一选定位线组，并将该选定位线组调整至一第二预定电压；
其中，该解码器由一第一类型元件所组成，该时序控制器由该第一类型元件与一第二类型元件所组成。
2.如权利要求1所述的非易失性存储器，其中第一类型元件为高耐压的元件，该第二类型元件为低耐压的元件。
3.如权利要求1所述的非易失性存储器，其中第一类型元件为一I/O元件，该第二类型元件为核心元件。
4.如权利要求1所述的非易失性存储器，其中该时序控制器包括：
一前级脉冲产生电路，根据该时钟信号的该第一信号沿产生该预充电信号，且该预充电信号具有一第一脉冲，该第一脉冲的一脉冲宽度为一预充电周期；以及
一次级脉冲产生电路，连接至该前级脉冲产生电路，该次级脉冲产生电路在该预充电周期后产生该重置信号，且该重置信号具有一第二脉冲，该第二脉冲的一脉冲宽度为一重置周期。
5.如权利要求4所述的非易失性存储器，其中该前级脉冲产生电路包括：
一第一脉冲产生器，接收该时钟信号并产生一第一信号；
一第二脉冲产生器，接收该时钟信号并产生一第二信号；以及
一决定电路，当该第一信号的一脉冲宽度大于该第二信号的一脉冲宽度时，将该第一信号作为该预充电信号；以及当该第一信号的该脉冲宽度小于该第二信号的该脉冲宽度时，将该第二信号作为该预充电信号。
6.如权利要求5所述的非易失性存储器，其中该第一脉冲产生器由该第一类型元件所组成；且该第二脉冲产生器由该第二类型元件所组成。
7.如权利要求5所述的非易失性存储器，其中该第二脉冲产生器包括：
一延迟电路，接收该时钟信号，并产生一延迟的时钟信号；以及
一逻辑电路，接收该时钟信号与该延迟的时钟信号并产生该第二信号。
8.如权利要求7所述的非易失性存储器，其中该延迟电路包括：
一第一反相电路，具有一输入端接收该时钟信号；以及
一第二反相电路，具有一输入端连接至该第一反相电路的一输出端，并具有一输出端产生该延迟的时钟信号。
9.如权利要求8所述的非易失性存储器，其中该第一反相电路包括：
一第一PMOS晶体管，具有一源极连接至一电压源，一栅极连接至该第一反相电路的该输入端；
一第一NMOS晶体管，具有一源极连接至一接地端，一栅极连接至该第一反相电路的该输入端，一漏极连接至该第一PMOS晶体管的一漏极；
一第一电容器，具有一第一端连接至该第一PMOS晶体管的该漏极，一第二端连接至该接地端；以及
一第一缓冲器，具有一输入端连接至该第一PMOS晶体管的该漏极，一输出端作为该第一反相电路的该输出端。
10.如权利要求9所述的非易失性存储器，其中该第二反相电路包括：
一第二PMOS晶体管，具有一源极连接至该电压源，一栅极连接至该第一反相电路的该输出端；
一第二NMOS晶体管，具有一源极连接至该接地端，一栅极连接至该第一反相电路的该输出端，一漏极连接至该第二PMOS晶体管的一漏极；
一第二电容器，具有一第一端连接至该第二PMOS晶体管的该漏极，一第二端连接至该接地端；以及
一第二缓冲器，具有一输入端连接至该第二PMOS晶体管的该漏极，一输出端作为该第二反相电路的该输出端。
11.如权利要求10所述的非易失性存储器，其中该第一PMOS晶体管为一弱PMOS晶体管，且该第二NMOS晶体管为一弱NMOS晶体管。
12.如权利要求10所述的非易失性存储器，其中该第一NMOS晶体管为一弱NMOS晶体管，且该第二PMOS晶体管为一弱PMOS晶体管。
13.如权利要求4所述的非易失性存储器，其中在该重置周期之后为一发展与感测周期，且在该发展与感测周期，该感测放大器根据该选定位线组上的电压变化来决定该选定位线组上的逻辑电平，并作为一读取数据。
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