CN107045886A - Nonvolatile memory - Google Patents

Nonvolatile memory Download PDF

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Publication number
CN107045886A
CN107045886A CN201710025661.3A CN201710025661A CN107045886A CN 107045886 A CN107045886 A CN 107045886A CN 201710025661 A CN201710025661 A CN 201710025661A CN 107045886 A CN107045886 A CN 107045886A
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China
Prior art keywords
signal
circuit
pulse
nonvolatile memory
pmos transistor
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CN201710025661.3A
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CN107045886B (en
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赖子能
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eMemory Technology Inc
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eMemory Technology Inc
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    • G—PHYSICS
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    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/102—External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
    • G11C16/105—Circuits or methods for updating contents of nonvolatile memory, especially with 'security' features to ensure reliable replacement, i.e. preventing that old data is lost before new data is reliably written
    • G—PHYSICS
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    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
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    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
    • G11C11/416—Read-write [R-W] circuits 
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    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors
    • H03K3/356113—Bistable circuits using complementary field-effect transistors using additional transistors in the input circuit
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Abstract

The present invention includes for a kind of nonvolatile memory：One memory cell array and a control circuit.Memory array has a plurality of wordline and multiple bit lines.Control circuit includes：One process circuit, a decoder, a driver, time schedule controller and a sensing amplifier.Decoder is connected to the process circuit.Driver is connected to the decoder and a plurality of wordline.Time schedule controller is connected to the process circuit.Sensing amplifier is connected to the decoder, the time schedule controller and a plurality of wordline.

Description

Nonvolatile memory
Technical field
The present invention on a kind of nonvolatile memory, and especially in regard to it is a kind of have time schedule controller non-volatile memories Device.
Background technology
It is well known that nonvolatile memory includes a memory cell array (memory array), memory cell battle array Row are formed by multiple memory cell (memory cell) arrangement, and include a floating gate transistors in each memory cell (floating gate transistor)。
In addition, also including a control circuit (controlling circuit) in nonvolatile memory, to control to deposit Storage unit array is programmed action, read action or erasing move.
Therefore, nonvolatile memory is when performing various actions, and control circuit can sequentially produce various signals to storage Cell array.If mistake occurs in the sequential of these signals, can occur the situation of running failure (fail).
The content of the invention
The main object of the present invention is a kind of nonvolatile memory of proposition, including：One memory cell array, with a plurality of Wordline and multiple bit lines；And one control circuit, be connected to a plurality of wordline and the multiple bit lines, wherein the control circuit bag Include：One process circuit, is instructed in one first signal of a clock signal along a reading is produced；One decoder, is connected to the processing Circuit, to receive the reading location order of process circuit generation, and produces an address signal；One driver, is connected to this many Bar wordline, and drive according to the address signal one of a plurality of wordline；Time schedule controller, is connected to processing electricity Road, when managing circuit in this place and producing the reading location and make, sequentially produces a precharging signal and a reset signal；And one sensing put Big device, is connected to a plurality of wordline, wherein, when the precharging signal is acted, the multiple bit lines are adjusted to the first predetermined electricity Pressure；And when the reset signal is acted, a selected set of bit lines is determined from the multiple bit lines according to the address signal, and this is selected Position line group is adjusted to one second predetermined voltage；Wherein, the decoder is made up of a first kind element, the time schedule controller It is made up of the first kind element with a Second Type element.
More preferably understand in order to which the above-mentioned and other aspect to the present invention has, preferred embodiment cited below particularly, and coordinate attached Figure, is described in detail as follows：
Brief description of the drawings
Fig. 1 is nonvolatile memory schematic diagram of the present invention.
The depicted coherent signal schematic diagrames in nonvolatile memory of Fig. 2A.
Fig. 2 B are time schedule controller schematic diagram.
Fig. 2 C are prime pulse-generating circuit schematic diagram.
Fig. 3 is the coherent signal schematic diagram in nonvolatile memory when processing procedure changes.
The depicted time schedule controllers for second embodiment of the invention of Fig. 4 A.
The depicted coherent signal schematic diagrames in nonvolatile memory of the present invention of Fig. 4 B.
One example of the second pulse generator of the invention depicted in Fig. 5.
Symbol description
100：Nonvolatile memory
110：Memory cell array
150：Control circuit
152：Process circuit
154：Decoder
156：Driver
160：Time schedule controller
161：Prime pulse-generating circuit
162：Sensing amplifier
163、221、223：NOT gate
164：Nor gate
165、220：Delay circuit
168：Secondary pulses generation circuit
172：First pulse generator
174：Second pulse generator
176：OR gate
210：Logic circuit
222：First negative circuit
224：Second negative circuit
Embodiment
Fig. 1 is refer to, it is nonvolatile memory schematic diagram of the present invention that it is depicted.Nonvolatile memory 100 includes： One memory cell array 110 and a control circuit 150.Furthermore, control circuit 150 includes：One process circuit (processing Circuit) 152, decoder (decoder) 154, driver (driver) 156, time schedule controller (timing Controller) 160, with sensing amplifier (sense amplifier) 162.
Control in circuit 150, process circuit 152 is connected to decoder 154, and decoder 154 be connected to driver 156 with Sensing amplifier 162.In addition, process circuit 152 is connected to time schedule controller 160, and time schedule controller 160 is connected to sensing and put Big device 162.
Furthermore, memory cell array 110 has m bars wordline WL0~WLm-1 and n bars bit line BL0~BLn-1.Wherein, Driver 156 is connected to bit line WL0~WLm-1 of memory cell array 110, and sensing amplifier 162 is connected to memory cell battle array Wordline BL0~BLn-1 of row 110.
The read action flow of nonvolatile memory 100 introduced below.Substantially, nonvolatile memory 100 can root Operated according to a clock signal clk.When being read out action, process circuit 152 can instruct (read command) by reading Decoder 154 is sent to, and decoder 154 decodes after (decode) reads instruction and produces an address signal Addr.Furthermore, driving Device 156 drives the particular word line in m bars wordline WL0~WLm-1 according to address signal Addr.In addition, sensing amplifier 162 According to address signal Addr, a selected set of bit lines (selected bit line are determined in n bars bit line BL0~BLn-1 Set sensor operation), and to selected set of bit lines is carried out, data (read data) are read to produce.
For example, after address signal Addr is produced, the driving wordline of driver 156 WL1.Therefore, memory cell array N memory cell being connected in 110 on wordline WL1 can be driven.And n memory cell on wordline WL1 is correspondingly connected To n bars bit line BL0~BLn-1.
Furthermore, sensing amplifier 162 is according to address signal Addr, and it is selected set of bit lines to determine bit line BL0~BL7.Therefore, Sensing amplifier 162 is the voltage change on sense bit line BL0~BL7, and and then determines that the logic on bit line BL0~BL7 is electric It is flat to be used as reading data.In other words, it is to represent the storing state for being connected to the first eight memory cell on wordline WL1 to read data.
In addition, producing address signal Addr process in decoder 154, sensing amplifier 162 is needed according to SECO The precharging signal Precharge and reset signal Reset of device 160 acts bit line, can just be correctly created reading data.
Fig. 2A is refer to, its depicted coherent signal schematic diagram in nonvolatile memory.Fig. 2 B are SECO Device schematic diagram.2C figures are prime pulse-generating circuit schematic diagram.
As shown in Figure 2 A, in time point t1, in the rising edge of clock signal clk, process circuit 152 will read instruction transmission To decoder 154.Meanwhile, the control sequential controller 160 of process circuit 152 generation precharging signal Precharge to sensing is put Big device 162.
Time point t1 between time point t2 be precharge cycle (precharge period).In time point t1, sequential Controller 160 produces the precharging signal Precharge of a pulse (pulse) to sensing amplifier 162, and precharging signal Precharge pulse width (pulse width) is to represent the precharge cycle.
In precharge cycle, the decoding of decoder 154, which is read, instructs and produces address signal Addr.And sensing amplifier 162 according to precharging signal Precharge, in precharge cycle that all bit line BL0~BLn-1 is precharged to first is pre- Determine voltage (first predetermined voltage).For example, precharge cycle is 10ns, and the first predetermined voltage is 3.0V。
Time point t2 between time point t3 be reset cycle (reset period).In time point t2, time schedule controller 160 according to precharging signal Precharge trailing edge, produces the replacement electric signal Reset of a pulse to sensing amplifier 162, and reset signal Reset pulse width is to represent the reset cycle.
In reset cycle, and sensing amplifier 162 is determined according to address signal Addr among bit line BL0~BLn-1 Selected set of bit lines, and the selected set of bit lines is reset to one second predetermined voltage, and other bit lines then maintain the first predetermined electricity Pressure.For example, reset cycle is 10ns.Furthermore, the first predetermined voltage is different from the second predetermined voltage, and the second predetermined voltage For for example, ground voltage (ground voltage).
It is development and sense period (developing and sensing period) after time point t3.In hair Exhibition and sense period, memory cell current (cell current) can be produced extremely by being connected to the corresponding memory cell of selected set of bit lines Sensing amplifier 162.And according to the different storing state of memory cell, different size of memory cell current is had as charging Electric current (charge current).
Therefore, in development and sense period, the voltage in selected set of bit lines can be held by second voltage (such as ground voltage) Begin to change, and sense electric amplifier 162 and determined to select the logic in set of bit lines according to the voltage change size of every bit line Level, and it is used as reading data.
As shown in Figure 2 B, in order to allow time schedule controller 160 to produce precharging signal Precharge and reset signal Reset.The time schedule controller 160 of first embodiment of the invention includes a prime pulse-generating circuit (primary pulse Generating circuit) 161 with secondary pulses generation circuit (secondary pulse generating circuit) 168。
Prime pulse-generating circuit 161 receives clock signal clk, and according to the rising edge (rising of clock signal clk Edge precharging signal Precharge) is produced.In addition, secondary pulses generation circuit 168 receives precharging signal Precharge, And reset signal Reset is produced according to precharging signal Precharge trailing edge (falling edge).Therefore, sequential control Device 160 processed can sequentially produce the precharging signal Precharge of pulse and reset signal Reset of a pulse.
Fig. 2 C are an example of prime pulse-generating circuit 161.Prime pulse-generating circuit 161 includes a logic circuit With a delay circuit (delaying circuit) 165, and logic circuit include a NOT gate 163 and a nor gate 164.Wherein, NOT gate 163 receives clock signal clk and produces anti-phase clock signal clk b；Delay circuit (delaying circuit) 165 connects Receive after clock signal clk, time delay T, produce the clock signal clk d of delay.Nor gate 164 receives anti-phase clock letter Number CLKb and clock signal clk d of delay, and produce the precharging signal Precharge that pulse width is T.Similarly, secondary arteries and veins Reset signal Reset can also be produced using similar logic circuit and delay circuit by rushing generation circuit 168, no longer be gone to live in the household of one's in-laws on getting married herein State.
Furthermore, because memory cell array 110 needs higher operating voltage (operation voltage), therefore solution Code device 154 need the element (device) using high withstand voltage to realize with driver 156, the PMOS transistor of such as high withstand voltage and Nmos pass transistor.It is and time schedule controller 160 is then realized with sensing amplifier 162 using low pressure-resistant element, such as low pressure-resistant PMOS transistor and nmos pass transistor.
In addition, in manufacture of semiconductor, the element of two kinds of pressure-resistant types of difference can be produced.The element of first type is The element of high withstand voltage, also known as I/O elements (I/O device), it needs the first higher operating voltage, such as 6V.In addition, The element of second of type is low pressure-resistant element, also known as core parts (core device), and it needs the second relatively low behaviour Make voltage, such as 1.2V.In other words, I/O elements (I/O device) need to be respectively connecting to core parts (core device) Different power domains (power domain).
It is well known that because the process parameter of integrated circuit changes (variation of fabrication Parameters), various process corners (process corner) element can be produced, and causes different running speeds.Citing For, the quick-element at quick angle (fast-fast corner, abbreviation FF corner), typical case-typical angular (typical- Typical corner, abbreviation TT corner) element or at a slow speed-angle (slow-slow corner, abbreviation SS at a slow speed Corner element).
The running speed of the element of typical case-typical angular (TT corner), its nmos pass transistor and PMOS transistor (operation speed) meets the requirement (requirement) of design.The element at quickly-quick angle (FF corner), its The running speed of nmos pass transistor and PMOS transistor is also quick compared with the requirement of design.At a slow speed-at a slow speed angle (SS corner) Requirement of the running speed of element, its nmos pass transistor and PMOS transistor compared with design will also be at a slow speed.
The control circuit 150 of nonvolatile memory 100 includes decoder 154 and driver that I/O elements are constituted 165, and time schedule controller 160, the sensing amplifier 162 that core parts are constituted.And at a slow speed-angle (SS corner) at a slow speed I/O elements be likely to result in nonvolatile memory 100 read failure generation.It is described as follows：
Fig. 3 is refer to, coherent signal schematic diagram during its depicted change for processing procedure in nonvolatile memory.
Assuming that when the I/O elements of decoder 154 are the element of typical case-typical angular (TT corner), decoder 154 can be (t1~t2) acts address signal Addr, such as curve in precharge cycle<I>.
Furthermore, when decoder 154 I/O elements for quick-quick angle (FF corner) element when, then address signal Addr actuation time can be moved along.Conversely, when the I/O elements of decoder 154 are at a slow speed-at a slow speed angle (SS corner) During element, then address signal Addr actuation time can move backward.
In normal operation, the meeting of decoder 154 generation address signal Addr in precharge cycle, and sensing amplifier 162 can further determine selected set of bit lines, and reset the selected set of bit lines extremely in reset cycle according to address signal Addr One second predetermined voltage.And when entering development with sense period, sensing amplifier 162 can produce reading data.
However, the process parameter due to integrated circuit can not be accurately controlled, if decoder 154 is by a slow speed-angle at a slow speed The I/O elements of (SS corner) are constituted, and decoder 154 just produces address signal Addr, such as curve after reset cycle <II>It is shown.The selected set of bit lines that then sensing amplifier 162 can determine to make mistake in reset cycle, and cause sensing amplifier 162 produce the reading data of mistake in development and sense period, cause the reading failure (read of nonvolatile memory 100 Fail) can not normal operation.
Explanation more than, causes to be that processing procedure changes the reason for reading failure, and cause decoder 154 by slow Speed-at a slow speed the element of angle (SS corner) constituted, cause decoder 154 can not be produced in predetermined period (precharge cycle) Address signal Addr.Furthermore, because time schedule controller 160 cannot respond to above-mentioned processing procedure change, and then cause to read failure.
Fig. 4 A are refer to, its depicted time schedule controller for second embodiment of the invention.Time schedule controller 160 includes one Prime pulse-generating circuit 161 and secondary pulses generation circuit 168.
Identical operation principles, prime pulse-generating circuit 161 receives clock signal clk, and according to clock signal clk Rising edge (rising edge) produces precharging signal Precharge.Secondary pulses generation circuit 168 receives precharging signal Precharge, and reset signal Reset is produced according to precharging signal Precharge trailing edge (falling edge).Cause This, the time schedule controller 160 i.e. precharging signal Precharge of sequentially one pulse of generation and the reset signal of a pulse Reset。
The second embodiment of the present embodiment is that prime pulse-generating circuit 161 includes one first pulse generator (pulse Generator) 172 and second pulse generator 174.Wherein, the first pulse generator 172 is by core parts (core Device) constituted, and the second pulse generator 174 is made up of I/O elements (I/Odevice).In addition, the first pulses generation Fig. 2 C similar with the circuit structure of the second pulse generator 174 of device 172, is respectively provided with a logic circuit and a delay circuit, each The pulse that pulse width is T can be produced.
Because the decoder 154 and time schedule controller 160 in control circuit 150 are made in identical integrated circuit (IC) On.Therefore, when making I/O elements, if occur processing procedure change, decoder 154 and time schedule controller can be had influence on simultaneously The second pulse generator 174 in 160.In other words, if processing procedure change causes decoder 154 by a slow speed-angle (SS at a slow speed Corner element) is constituted, then the second pulse generator 174 also can be by element institute group at a slow speed-at a slow speed angle (SS corner) Into.
Although the second pulse generator 174 is estimated to produce the pulse that pulse width is T, due to the second pulse generator 174 by a slow speed-at a slow speed the element of angle (SS corner) constituted, it will so that the pulse width of the second pulse generator 174 is big In T.And the pulse width of the second pulse generator 174 is relevant to element characteristic at a slow speed-at a slow speed angle (SS corner).That is, when When I/O element characteristics in second pulse generator 174 are poorer, its pulse width produced can be wider.
In the above cases, as shown in Figure 4 A, the first pulse generator produces the first signal P1 that pulse width is T, Second pulse generator produces the secondary signal P2 that pulse width is T '.Therefore, after OR gate 176, prime pulses generation electricity Road 161 is to produce the precharging signal that pulse width is T '.In other words, OR gate 176 can be considered a decision-making circuit, by the first signal The larger pulse of pulse width is used as precharging signal Precharge in P1 and secondary signal P2.
Fig. 4 B are refer to, its depicted coherent signal schematic diagram in nonvolatile memory of the present invention.Wherein, decode Device 154 and time schedule controller 160 by a slow speed-at a slow speed the element of angle (SS corner) constituted.
In time point ta, in the rising edge of clock signal clk, process circuit 152 is sent to decoder by instruction is read 154.Meanwhile, the control sequential controller 160 of process circuit 152 produces precharging signal Precharge to sensing amplifier 162.
Time point ta between time point tb be precharge cycle (precharge period).Because decoder 154 prolongs Address signal Addr is produced afterwards, and also accordingly extension precharging signal Precharge pulse width is time schedule controller 160 T’.Therefore, precharge cycle can be extended so that decoder 154 produces address signal Addr still in precharge cycle.
Therefore, in time point tb to the reset cycle between time point tc.Sensing amplifier 162 can be according to address signal Addr determines selected set of bit lines among bit line BL0~BLn-1, and resets the selected set of bit lines to one second predetermined voltage, and Other bit lines then maintain the first predetermined voltage.
And development and sense period after time point tc.Being connected to the corresponding memory cell of selected set of bit lines can produce Memory cell current (cell current) is to sensing amplifier 162.And sense electric amplifier 162 can be according to every bit line Voltage change size determines the logic level in selected set of bit lines, and as reading data.
In addition, if element institute of the pulse generator 174 of decoder 154 and second by typical case-typical angular (TT corner) Composition, then the pulse width of the second pulse is T.Furthermore, if the pulse generator 174 of decoder 154 second is by quick-quick angle The element of (FF corner) is constituted, then the pulse width of the second pulse is less than T.In the case of two kinds more than, via or After door 176, prime pulse-generating circuit 162 still produces the precharging signal Precharge that pulse width is T.
Understand from the description above, the advantage of the invention is that proposing a kind of sequential applied in nonvolatile memory Controller.Time schedule controller 160 is included as the first pulse generator 172 constructed by core parts and I/O elements institute The second built-up pulse generator 174.
Changed according to processing procedure, when the pulse generator 174 of decoder 154 and second is by a slow speed-angle (SS corner) institute at a slow speed When built-up, the second pulse generator 174 can change the pulse width of output pulse, to change precharging signal Precharge pulse width and precharge cycle.In this way, will may insure that decoder 154 is produced in precharge cycle Address signal Addr, and cause sensing amplifier 162 be correctly created reading data.
Fig. 5 is refer to, an example of its depicted second pulse generator 174 of the invention, and the second pulse generator 174 are constituted by I/O elements.Second pulse generator 174 includes a logic circuit 210 and a delay circuit 220.Wherein, Delay circuit 220 is received after clock signal clk, time delay T, produces the clock signal clk d of delay.Furthermore, logic circuit 210 receive clock signal clk and the clock signal clk d of delay, and produce secondary signal P2.
Substantially, logic circuit 210 can have the mode of various realizations.For example, logic circuit 210 may include a NOT gate with One nor gate, the connected mode according to Fig. 2 C, you can produce secondary signal P2.
Furthermore, delay circuit 220 includes one first negative circuit (inverting circuit) 222 and 1 the of concatenation Two negative circuits 224.There is first negative circuit 222 input to receive the clock signal.Second negative circuit 224 has one Input is connected to the output end of the first negative circuit 222, the second negative circuit 224 and produces delay with an output end Clock signal clk d.
First negative circuit 222 includes PMOS transistor p1, nmos pass transistor n1, capacitor c1 and buffer (buffer)221；Second negative circuit 224 includes PMOS transistor p2, nmos pass transistor n2, capacitor c2 and buffer (buffer)223.Via control capacitor c1, c2 capacitance, you can the time delay of control delay circuit 220, go forward side by side one Step ground changes secondary signal P2 pulse width.
First negative circuit 222 includes：First PMOS transistor p1, a voltage source Vdd, one are connected to a source electrode Grid is connected to the input of first negative circuit 222；First nmos pass transistor n1, a ground connection is connected to a source electrode End a, grid is connected to the input of first negative circuit 222, and a drain electrode is connected to the one of first PMOS transistor p1 Drain electrode；One first capacitor c1, first PMOS transistor p1 drain electrode, the connection of one second end are connected to a first end To the earth terminal；And one first buffer 221, first PMOS transistor p1 drain electrode is connected to an input, One output end as first negative circuit 222 the output end.
Second negative circuit 224 includes：One second PMOS transistor p2, voltage source Vdd is connected to a source electrode, One grid is connected to the output end of first negative circuit 222；One second nmos pass transistor n2, this is connected to a source electrode Earth terminal a, grid is connected to the output end of first negative circuit 222, and a drain electrode is connected to second PMOS transistor p2 A drain electrode；One second capacitor c2, second PMOS transistor p2 drain electrode, one second end are connected to a first end It is connected to the earth terminal；And one second buffer 223, second PMOS transistor p2 leakage is connected to an input Pole, an output end as second negative circuit 224 the output end.
Furthermore, the PMOS transistor p1 that the present invention can also design in the first negative circuit 222 is a weak PMOS transistor (weak PMOS transistor) and in the second negative circuit 224 nmos pass transistor n2 be a weak nmos pass transistor (weak NMOS transistor).In this way, the pulse width of the second pulse generator 174 can be allowed more relevant at a slow speed-angle (SS at a slow speed Corner element characteristic).It is of course also possible to which it is brilliant for a weak NMOS to design the nmos pass transistor n1 in the first negative circuit 222 Body pipe and in the second negative circuit 224 PMOS transistor p2 be a weak PMOS transistor.
In summary, although the present invention is disclosed as above with preferred embodiment, so it is not limited to the present invention.This hair Technical staff in bright art, without departing from the spirit and scope of the present invention, can make various changes and retouching. Therefore, protection scope of the present invention should be defined depending on the appended claims person of defining.

Claims (13)

1. a kind of nonvolatile memory, including：
One memory cell array, with a plurality of wordline and multiple bit lines；And
One control circuit, is connected to a plurality of wordline and the multiple bit lines；
Wherein, the control circuit includes：
One process circuit, is instructed in one first signal of a clock signal along a reading is produced；
One decoder, is connected to the process circuit, to receive the reading instruction of process circuit generation, and produces an address Signal；
One driver, is connected to a plurality of wordline, and drives according to the address signal one of a plurality of wordline；
Time schedule controller, is connected to the process circuit, when reason circuit produces reading instruction in this place, sequentially produces a preliminary filling Electric signal and a reset signal；And
One sensing amplifier, is connected to a plurality of wordline, wherein, when the precharging signal is acted, the multiple bit lines are adjusted To the first predetermined voltage；And when the reset signal is acted, a selected position is determined from the multiple bit lines according to the address signal Line group, and the selected set of bit lines is adjusted to one second predetermined voltage；
Wherein, the decoder is made up of a first kind element, and the time schedule controller is by the first kind element and one second Type element is constituted.
2. nonvolatile memory as claimed in claim 1, wherein first kind element are the element of high withstand voltage, the Equations of The Second Kind Type element is low pressure-resistant element.
3. nonvolatile memory as claimed in claim 1, wherein first kind element are an I/O elements, the Second Type Element is core parts.
4. nonvolatile memory as claimed in claim 1, the wherein time schedule controller include：
One prime pulse-generating circuit, the precharging signal, and the preliminary filling are produced according to first signal of clock signal edge Electric signal has one first pulse, and a pulse width of first pulse is a precharge cycle；And
Level pulse-generating circuit, is connected to the prime pulse-generating circuit, and the secondary pulses generation circuit is in the precharge The reset signal is produced after cycle, and the reset signal has one second pulse, a pulse width of second pulse is a weight Put the cycle.
5. nonvolatile memory as claimed in claim 4, wherein the prime pulse-generating circuit include：
One first pulse generator, receives the clock signal and produces one first signal；
One second pulse generator, receives the clock signal and produces a secondary signal；And
One decision-making circuit, when first signal a pulse width be more than the secondary signal a pulse width when, by this first Signal is used as the precharging signal；And when the pulse width of first signal is less than the pulse width of the secondary signal When, it regard the secondary signal as the precharging signal.
6. nonvolatile memory as claimed in claim 5, wherein first pulse generator are by the first kind element institute Composition；And second pulse generator is made up of the Second Type element.
7. nonvolatile memory as claimed in claim 5, wherein second pulse generator include：
One delay circuit, receives the clock signal, and produce the clock signal of a delay；And
One logic circuit, receives the clock signal of the clock signal and the delay and produces the secondary signal.
8. nonvolatile memory as claimed in claim 7, the wherein delay circuit include：
One first negative circuit, the clock signal is received with an input；And
One second negative circuit, an output end of first negative circuit is connected to an input, and with an output end Produce the clock signal of the delay.
9. nonvolatile memory as claimed in claim 8, wherein first negative circuit include：
One first PMOS transistor, a voltage source is connected to a source electrode, and a grid is connected to being somebody's turn to do for first negative circuit Input；
One first nmos pass transistor, an earth terminal is connected to a source electrode, and a grid is connected to being somebody's turn to do for first negative circuit Input a, drain electrode is connected to a drain electrode of first PMOS transistor；
One first capacitor, the drain electrode of first PMOS transistor is connected to a first end, and one second end is connected to this Earth terminal；And
One first buffer, is connected to the drain electrode of first PMOS transistor with an input, an output end as this The output end of one negative circuit.
10. nonvolatile memory as claimed in claim 9, wherein second negative circuit include：
One second PMOS transistor, the voltage source is connected to a source electrode, and a grid is connected to being somebody's turn to do for first negative circuit Output end；
One second nmos pass transistor, the earth terminal is connected to a source electrode, and a grid is connected to being somebody's turn to do for first negative circuit Output end a, drain electrode is connected to a drain electrode of second PMOS transistor；
One second capacitor, the drain electrode of second PMOS transistor is connected to a first end, and one second end is connected to this Earth terminal；And
One second buffer, is connected to the drain electrode of second PMOS transistor with an input, an output end as this The output end of two negative circuits.
11. nonvolatile memory as claimed in claim 10, wherein first PMOS transistor are a weak PMOS transistor, And second nmos pass transistor is a weak nmos pass transistor.
12. nonvolatile memory as claimed in claim 10, wherein first nmos pass transistor are a weak nmos pass transistor, And second PMOS transistor is a weak PMOS transistor.
13. nonvolatile memory as claimed in claim 4, wherein being a development and sensing week after the reset cycle Phase, and in the development and sense period, the sensing amplifier determines that this is selected according to the voltage change in the selected set of bit lines Logic level in set of bit lines, and read data as one.
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