TWI610312B - 具有錯誤修正碼的記憶體架構以及其操作方法 - Google Patents

具有錯誤修正碼的記憶體架構以及其操作方法 Download PDF

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TWI610312B
TWI610312B TW106101514A TW106101514A TWI610312B TW I610312 B TWI610312 B TW I610312B TW 106101514 A TW106101514 A TW 106101514A TW 106101514 A TW106101514 A TW 106101514A TW I610312 B TWI610312 B TW I610312B
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circuit
data
ecc
inverter
control circuit
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黃柏豪
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力旺電子股份有限公司
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Abstract

一種電路架構，用於在記憶體裝置中操作錯誤修正碼，包括控制電路及錯誤修正碼(ECC)電路。該錯誤修正碼電路與該控制電路耦接。該控制電路接收位元組的第一資料，以將該資料反相成為反相資料。該錯誤修正碼電路接收該反相資料，以進行加密或解密以及輸出第二資料。

Description

具有錯誤修正碼的記憶體架構以及其操作方法
本發明是有關於一種記憶體架構，且特別是有關於一種具有錯誤修正碼功能的記憶體架構。
對於記憶體裝置的基本架構，其包含記憶胞陣列以及多種週邊電路以存取記憶胞陣列的記憶胞。記憶胞陣列是儲存資料的核心部份。然而，儲存於記憶胞陣列中的資料可能有錯誤，其資料的一個位元可能會從原本要寫入的位元被翻轉。當資料對記憶胞陣列要被寫入或是讀出時，為了修正在記憶胞陣列中的錯誤位元，錯誤修正碼(error-correcting code, ECC)電路會被使用，根據奇偶(parity)檢查以偵測錯誤位元接著修正此錯誤位元。
多種演算方法可以被使用在ECC電路。對於其中的一種演算方法，其是以檢查例如32位元的資料組中的“1”的數量為偶數為根據。然而當記憶胞陣列的記憶胞原始資料都是“1”，例如是FFFF-FFFF時，其中一個字是由四個位元構成，一個“F”代表“1111”的四個位元，則ECC電路可能會改變初始資料。
ECC電路對資料“FFFF-FFFF”所造成的錯誤如下。舉一例，對於具有32位元I/O的ECC電路，其會有六個修正碼，或是位元。當資料“FFFF-FFFF”的32個位元輸入到ECC電路進行加密(encryption)時，經過ECC加密後的資料總共會具有38個位元，其中已包含 “01 1000”的六個位元而得到“3F-FFFF-FFD8”，其會被儲存到記憶胞陣列。然後，“3F-FFFF-FFD8”的資料從記憶胞陣列被讀出。在實際輸出前，“3F-FFFF-FFD8”的資料會進入ECC電路進行解密(decryption)，以移除ECC而得到32位元的“FFFF-FFFF”的輸出資料。然而，記憶體剛出廠時，從記憶胞陣列被讀出被讀出的資料是“3F-FFFF-FFFF”，而不是“3F-FFFF-FFD8”。這會造成第一次讀出的是失敗。這種情況特別可能存在於初始資料為 “FFFF-FFFF”時。
如何有效解決上述的議題，對於ECC電路的設計是需要被考慮的。
本發明提供具有ECC功能的記憶體架構，其中ECC功能可以維持其功能，但是對於輸入到ECC電路的資料會被反相，而從ECC電路輸出的資料也會被反相。
於一實施例，本發明提供一種具有錯誤修正碼功能的記憶體架構。該記憶體架構包括記憶胞陣列，用以儲存多個位元的資料。錯誤修正碼(ECC)電路，用以對具有錯誤修正碼的通過資料加密或解密。第一控制電路，連接於該ECC電路與該記憶胞陣列之間。第二控制電路，連接於該ECC電路與資料輸入/輸出(I/O)端之間。當該I/O端的輸入資料要被寫入到該記憶胞陣列時，該第二控制電路在該輸入資料進入該ECC電路進行加密之前對該輸入資料反相，以及該第一控制電路對該ECC電路的輸出反相，而寫入到該記憶胞陣列。當該記憶胞陣列的輸出資料要被讀出時，該輸出資料在進入該ECC電路進行解密之前由該第一控制電路反相，以及該第二控制電路對該ECC電路的輸出反相，而當作讀出資料。
於一實施例，對於所述的記憶體架構，該ECC電路是漢明碼(Hamming code) ECC電路。
於另一實施例，對於所述的記憶體架構，該輸入資料包含一位元組，以及該多個位元被分成多個群，該多個群是兩兩相交，且該ECC電路提供多個奇偶位元以對每一個該群修正使得具有“1”的位元的總數量為偶數。
於另一實施例，對於所述的記憶體架構，該ECC電路包含加密電路與解密電路，以分別構成加密路徑與解密路徑。
於另一實施例，對於所述的記憶體架構，該第一控制電路在分別的該加密電路與該解密電路中包含第一反相器與第二反相器，其中該第一反相器對該ECC電路的該輸出反相以寫入到該記憶胞陣列，以及該第二反相器對從該記憶胞陣列的該輸出資料反相以進入到該ECC電路進行解密。該第二控制電路在分別的該加密電路與該解密電路中包含第三反相器與第四反相器，其中該第三反相器對該輸入資料反相以進入到該ECC電路進行加密，以及該第四反相器對經該ECC電路解密後的該輸出反相以提供該讀出資料。
於另一實施例，對於所述的記憶體架構，該加密路徑與該解密路徑被多功處理，如此該第一到第四反相器的至少兩個是共用相同的一個反相器。
於另一實施例，本發明提供一種記憶體裝置的操作方法，其中該記憶體裝置包含記憶胞陣列、錯誤修正碼(ECC)電路、第一控制電路及第二控制電路。該ECC電路用以對具有錯誤修正碼的通過資料加密或解密。該操作方法包括:連接該第一控制電路於該ECC電路與該記憶胞陣列之間;連接該第二控制電路於該ECC電路與資料輸入/輸出(I/O)端之間;當從該I/O端來的一位元組的輸入資料要被寫入到該記憶胞陣列時進行程式模式，該第二控制電路在該輸入資料進入該ECC電路進行加密之前對該輸入資料反相，以及該第一控制電路對該ECC電路的輸出反相，而寫入到該記憶胞陣列; 以及當該記憶胞陣列的輸出資料要被讀出時進行讀出模式，對該輸出資料在進入該ECC電路進行解密之前由該第一控制電路反相，以及該第二控制電路對該ECC電路的輸出反相，而當作讀出資料。
於另一實施例，對於所述的操作方法，該ECC電路是漢明碼(Hamming code) ECC電路，以進行加密處理與解密處理。
於另一實施例，對於所述的操作方法，該輸入資料包含一位元組，以及該多個位元被分成多個群，該多個群是兩兩相交，且該ECC電路提供多個奇偶位元以對每一個該群修正使得具有“1”的位元的總數量為偶數。
於另一實施例，對於所述的操作方法，其更包括提供具有加密電路與解密電路的該ECC電路，以分別構成加密路徑與解密路徑。
於另一實施例，對於所述的操作方法，其更包括提供在該加密電路與該解密電路中分別具有第一反相器與第二反相器的該第一控制電路，其中該第一反相器對該ECC電路的該輸出反相以寫入到該記憶胞陣列，以及該第二反相器對從該記憶胞陣列的該輸出資料反相以進入到該ECC電路進行解密; 更提供在該加密電路與該解密電路中分別具有第三反相器與第四反相器的該第二控制電路，其中該第三反相器對該輸入資料反相以進入到該ECC電路進行加密，以及該第四反相器對經該ECC電路解密後的該輸出反相以提供該讀出資料。
於另一實施例，對於所述的操作方法，其更包括對該加密路徑與該解密路徑進行多功處理，如此該第一到第四反相器的至少兩個是共用相同的一個反相器。
於另一實施例，本發明提供一種操作記憶體裝置的方法。此方法包括:在程式模式下接收輸入資料;藉由控制電路對該輸入資料反相，成為第一反相資料;提供錯誤修正碼(ECC)電路，以接收該第一反相資料以進行加密與輸出加密資料;藉由該控制電路對該加密資料反相及寫入到記憶胞陣列;在讀出模式下使用該控制電路，以對從該記憶胞陣列讀出的輸出資料反相成第二反相資料;藉由該ECC電路對該第二反相資料解密; 以及藉由該控制電路，對該解密資料反相成為讀出資料。
於另一實施例，對於所述的方法，該控制電路對應加密與解密包含多個反相器，以對通過資料反相。
於另一實施例，對於所述的方法，其更包括對該加密路徑與該解密路徑進行多功處理，如此該第一到第四反相器的至少兩個是共用相同的一個反相器。
於另一實施例，對於所述的方法，其中該輸入資料包含一位元組，以及該多個位元被分成多個群，該多個群是兩兩相交，且該ECC電路提供多個奇偶位元以對每一個該群修正使得具有“1”的位元的總數量為偶數。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
以下舉一些實施例配合圖式來較詳細說明本發明。在圖式中相同的構件符號代表相同或相似的構件。
本發明提出一種ECC操作，其可以避免ECC的錯誤，其特別可能發生於存取儲存在記憶胞陣列的初始資料。此ECC可以維持其功能，但是對於輸入到ECC電路的資料會被反相，而從ECC電路輸出的資料也會被反相。
提供的多個實施例是用來描述本發明，但是不是用來限制本發明。
圖1依據本發明一實施例，繪示記憶體架構示意圖。參閱圖1，記憶體裝置50一般包括記憶胞陣列100及多種週邊元件來控制與存取記憶胞陣列100。這些週邊元件於一實施例可以包括驅動器102、Y電路/感應放大器 104、感應放大器控制電路(SACTL) 106、控制器(CTL) 108、ECC電路110、類比電路113、電源開關115以及高電壓系統117。多個終端點例如控制匯流排、地址匯流排及輸入/輸出(I/O) 匯流排等，也被提供來與外部的主機互通以存取記憶胞陣列100。記憶體裝置50的基本架構與操作是本技術領域一般可知的技術，於此不予詳細描述。
然而，本發明是關於ECC電路110的操作。以下的描述將針對本發明提出的ECC電路110的功能進行描述。
要被寫入記憶胞陣列100而儲存的輸入資料DIN，會先通過ECC電路110以ECC來加密，其中ECC電路110可以產生修正碼，其在之後的資料有發生錯誤位元時就可以修正此錯誤位元。ECC電路110於是輸出此資料DATA，其是實際被寫入記憶胞陣列100而儲存。另一方面，當輸出資料OUT從記憶胞陣列100要被外部主機讀出時，輸出資料OUT也會進入ECC電路110進行解密，接著輸出當作讀取資料PDOUT。
本發明所提出具有修改結構的ECC電路110，可以避免當資料的値是FFFF-FFFF時所可能發生的錯誤。圖2依據本發明一實施例，繪示操作ECC的電路架構示意圖。
參閱圖2，ECC電路110是在I/O端與記憶胞陣列100之間的中間元件。本發明不需要修改原始的ECC電路112。然而，本發明加入控制電路，其在一範例中為了方便配置可以包括第一控制電路114與第二控制電路116。ECC電路112可以被分為加密路徑(En)112a與解密路徑(De)112b。如此，如本發明所提出的ECC電路110具有第一控制電路114連接於ECC電路112與記憶胞陣列100之間，且第二控制電路116連接於ECC電路112與資料I/O端。
當從資料I/O端來的輸入資料DIN要被寫入到記憶胞陣列100，第二控制電路116在輸入資料DIN要通過加密路徑112a進入ECC電路112進行加密之前，將輸入資料DIN反相，而第一控制電路114對從ECC電路112的輸出反相成為資料，標示為DATA，而通過在Y電路/感應放大器104中的寫入電路而寫入到記憶胞陣列100。當如標示為OUT的輸出資料從記憶胞陣列100被在Y電路/感應放大器104中的感應放大器讀出。輸出資料OUT在通過解密路徑112b進入ECC電路112進行解密之前被第一控制電路114反相，並且第二控制電路116對從ECC電路112的輸出反相而視為讀出資料，如PDOUT的標示。
更詳細地，第一控制電路114包括第一反相器114a與第二反相器114b分別於加密路徑112a與解密路徑112b中，其中第一反相器114a對從ECC電路112的輸出反相以寫入到記憶胞陣列100，以及第二反相器114b對從記憶胞陣列100讀出的輸出資料反相以進入到ECC電路112進行解密。另一方面，第二控制電路116包含第三反相器116a與第四反相器116b，分別於加密路徑112a與解密路徑112b中，其中第三反相器116a對輸入資料DIN反相，以進入ECC電路112進行解密，且第四反相器116b對從ECC電路112經解密後的輸出反相，以提供讀出資料PDOUT。
在描述本發明所提出的ECC電路110的效果之前，先提供ECC的操作範例。圖3依據本發明一實施例，繪示ECC產生奇偶位元的機制示意圖。參閱圖3，以傳送由四個位元所構成的位元組為例，例如是1101，以及三個位元被加入當作奇偶位元。總共7個位元被傳送，其中這7個位元被編號成1到7的碼號。此7個位元例如被分成三群A、B、C。這些群是兩兩相交，其關係如左上所示。其結果，碼號1-7的碼值是1101010，其中前面四個位元代表資料。在ECC加密中，每一個群有四個位元且需要符合“1”的總數量為偶數。
圖4依據本發明一實施例，繪示ECC修正錯誤位元的機制示意圖。參閱圖4，要被傳送的資料需要是1101010，如左上所示。然而，儲存在記憶胞陣列100的資料可能是1101000。ECC電路112，例如是(7,4)漢明碼(Hamming code)電路，可以將1101000的資料解密為1101010。這是因為群B有奇數個位元是“1”，因此在碼號6的奇偶位元會被修正為 “1”。於此，依照在(7,4)漢明碼(Ha電路的操作，位元的總數量為7，但是僅有四個位元是原始要被傳送。
接著描述本發明提出的ECC電路110的操作機制。圖5依據本發明一實施例，繪示ECC操作加密的機制示意圖。參閱圖5，對於要加密的一個特殊情形，其輸入資料DIN的所有位元剛好全都是“1”，例如32位元的FFFF-FFFF。反相器116a將資料反相成反相資料DINB，其是0000-0000，於是進入到ECC電路112的加密路徑112a。因為資料是“0”，其仍符合位元為“1”的數量是偶數的條件。奇偶位元會維持“0”，而不必加入“1”的位元。於是，38個位元都是“0”的資料被再次被反相器114a反相成為3F-FFF-FFF的資料DATA，其要被寫入記憶胞陣列100。
圖6依據本發明一實施例，繪示ECC操作解密的機制示意圖。參閱圖6，資料從記憶胞陣列100被讀出以進行解密。於是，由記憶胞陣列100讀出的輸出資料OUT的所有38個位元都是“1”，如3F-FFFF-FFFF。再一次，反相器114b將資料OUT反相成資料OUTB，其接著進入到ECC電路112的解密路徑112b。於此，資料OUTB的所有位元都是“0”，如此ECC電路112不會改變資料而將為“0”的所有位元輸出。再一次，反相器116b將“0”的所有位元反相成“1”，當作讀出資料PDOUT，其在移除ECC後會維持原始的FFFF-FFFF的形式。
需要注意的是，多個反相器被用來描述其機制。然而，因為反相器都是相同的功能，如此這些反相器可以共用相同的一個反相器。換句話說，通過路徑的安排以及使用多功器，第一與第三反相器可以共用相同的一個反相器，而第二與第四反相器可以共用相同的一個反相器。甚至，第一到第四反相器也可以共用相同的一個反相器，其中路徑的選擇機制需要被加入。換句話說，加密路徑112a與解密路徑112b的每一個會涉及兩次的反相操作，其中的硬體的安排不必限制於前面所舉的實施例。
此ECC電路可以避免當初始資料的位元被設為“1”時，其資料被寫入於讀出時的不一致。ECC電路可以與其他類型的ECC電路相容，這是因為兩次的反相處理不會改變其他類型的ECC電路的結果。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
50‧‧‧憶體裝置
100‧‧‧記憶胞陣列
102‧‧‧驅動器
104‧‧‧Y電路/感應放大器
106‧‧‧感應放大器控制電路
108‧‧‧控制器
110‧‧‧ECC電路
112‧‧‧ECC電路
112a‧‧‧加密路徑
112b‧‧‧解密路徑
113‧‧‧類比電路
114‧‧‧控制電路
114a、114b‧‧‧反相器
115‧‧‧電源開關
116‧‧‧控制電路
116a、116b‧‧‧反相器
117‧‧‧高電壓系統(電荷泵)
圖1依據本發明一實施例，繪示記憶體架構示意圖。 圖2依據本發明一實施例，繪示操作ECC的電路架構示意圖。 圖3依據本發明一實施例，繪示ECC產生奇偶位元的機制示意圖。 圖4依據本發明一實施例，繪示ECC修正錯誤位元的機制示意圖。 圖5依據本發明一實施例，繪示ECC操作加密的機制示意圖。 圖6依據本發明一實施例，繪示ECC操作解密的機制示意圖。
110‧‧‧ECC電路
112‧‧‧ECC電路
112a‧‧‧加密路徑
112b‧‧‧解密路徑
114‧‧‧控制電路
114a、114b‧‧‧反相器
116‧‧‧控制電路
116a、116b‧‧‧反相器

Claims (16)

  1. 一種具有錯誤修正碼功能的記憶體架構，該記憶體架構包括： 記憶胞陣列，用以儲存多個位元的資料； 錯誤修正碼(ECC)電路，用以對具有錯誤修正碼的通過資料加密或解密; 第一控制電路，連接於該ECC電路與該記憶胞陣列之間; 以及 第二控制電路，連接於該ECC電路與資料輸入/輸出(I/O)端之間， 其中當該I/O端的輸入資料要被寫入到該記憶胞陣列時，該第二控制電路在該輸入資料進入該ECC電路進行加密之前對該輸入資料反相，以及該第一控制電路對該ECC電路的輸出反相，而寫入到該記憶胞陣列， 其中當該記憶胞陣列的輸出資料要被讀出時，該輸出資料在進入該ECC電路進行解密之前由該第一控制電路反相，以及該第二控制電路對該ECC電路的輸出反相，而當作讀出資料。
  2. 如申請專利範圍第1項所述的記憶體架構，其中該ECC電路是漢明碼(Hamming code) ECC電路。
  3. 如申請專利範圍第1項所述的記憶體架構，其中該輸入資料包含一位元組，以及該多個位元被分成多個群，該多個群是兩兩相交，且該ECC電路提供多個奇偶位元以對每一個該群修正使得具有“1”的位元的總數量為偶數。
  4. 如申請專利範圍第1項所述的記憶體架構，其中該ECC電路包含加密電路與解密電路，以分別構成加密路徑與解密路徑。
  5. 如申請專利範圍第4項所述的記憶體架構， 其中該第一控制電路在分別的該加密電路與該解密電路中包含第一反相器與第二反相器，其中該第一反相器對該ECC電路的該輸出反相以寫入到該記憶胞陣列，以及該第二反相器對從該記憶胞陣列的該輸出資料反相以進入到該ECC電路進行解密， 其中該第二控制電路在分別的該加密電路與該解密電路中包含第三反相器與第四反相器，其中該第三反相器對該輸入資料反相以進入到該ECC電路進行加密，以及該第四反相器對經該ECC電路解密後的該輸出反相以提供該讀出資料。
  6. 如申請專利範圍第5項所述的記憶體架構，其中該加密路徑與該解密路徑被多功處理，如此該第一到第四反相器的至少兩個是共用相同的一個反相器。
  7. 一種記憶體裝置的操作方法，其中該記憶體裝置包含記憶胞陣列、錯誤修正碼(ECC)電路、第一控制電路及第二控制電路，該ECC電路用以對具有錯誤修正碼的通過資料加密或解密，該操作方法包括: 連接該第一控制電路於該ECC電路與該記憶胞陣列之間; 連接該第二控制電路於該ECC電路與資料輸入/輸出(I/O)端之間; 當從該I/O端來的一位元組的輸入資料要被寫入到該記憶胞陣列時進行程式模式，該第二控制電路在該輸入資料進入該ECC電路進行加密之前對該輸入資料反相，以及該第一控制電路對該ECC電路的輸出反相，而寫入到該記憶胞陣列; 以及 當該記憶胞陣列的輸出資料要被讀出時進行讀出模式，對該輸出資料在進入該ECC電路進行解密之前由該第一控制電路反相，以及該第二控制電路對該ECC電路的輸出反相，而當作讀出資料。
  8. 如申請專利範圍第7項所述的記憶體裝置的操作方法，其中該ECC電路是漢明碼(Hamming code) ECC電路，以進行加密處理與解密處理。
  9. 如申請專利範圍第7項所述的記憶體裝置的操作方法，其中該輸入資料包含一位元組，以及該多個位元被分成多個群，該多個群是兩兩相交，且該ECC電路提供多個奇偶位元以對每一個該群修正使得具有“1”的位元的總數量為偶數。
  10. 如申請專利範圍第7項所述的記憶體裝置的操作方法，更包括提供具有加密電路與解密電路的該ECC電路，以分別構成加密路徑與解密路徑。
  11. 如申請專利範圍第10項所述的記憶體裝置的操作方法，更包括: 提供在該加密電路與該解密電路中分別具有第一反相器與第二反相器的該第一控制電路，其中該第一反相器對該ECC電路的該輸出反相以寫入到該記憶胞陣列，以及該第二反相器對從該記憶胞陣列的該輸出資料反相以進入到該ECC電路進行解密; 以及 提供在該加密電路與該解密電路中分別具有第三反相器與第四反相器的該第二控制電路，其中該第三反相器對該輸入資料反相以進入到該ECC電路進行加密，以及該第四反相器對經該ECC電路解密後的該輸出反相以提供該讀出資料。
  12. 如申請專利範圍第11項所述的記憶體裝置的操作方法，更包括對該加密路徑與該解密路徑進行多功處理，如此該第一到第四反相器的至少兩個是共用相同的一個反相器。
  13. 一種操作記憶體裝置的方法，包括: 在程式模式下，接收輸入資料; 藉由控制電路對該輸入資料反相，成為第一反相資料; 提供錯誤修正碼(ECC)電路，以接收該第一反相資料以進行加密與輸出加密資料; 藉由該控制電路對該加密資料反相及寫入到記憶胞陣列; 在讀出模式下使用該控制電路，以對從該記憶胞陣列讀出的輸出資料反相成第二反相資料; 藉由該ECC電路對該第二反相資料解密; 以及 藉由該控制電路，對該解密資料反相成為讀出資料。
  14. 如申請專利範圍第13項所述的操作記憶體裝置的方法，其中該控制電路對應加密與解密包含多個反相器，以對通過資料反相。
  15. 如申請專利範圍第14項所述的操作記憶體裝置的方法，更包括對該加密路徑與該解密路徑進行多功處理，如此該第一到第四反相器的至少兩個是共用相同的一個反相器。
  16. 如申請專利範圍第13項所述的操作記憶體裝置的方法，其中該輸入資料包含一位元組，以及該多個位元被分成多個群，該多個群是兩兩相交，且該ECC電路提供多個奇偶位元以對每一個該群修正使得具有“1”的位元的總數量為偶數。
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