TWI614766B - 非揮發性記憶體 - Google Patents

非揮發性記憶體 Download PDF

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TWI614766B
TWI614766B TW106100742A TW106100742A TWI614766B TW I614766 B TWI614766 B TW I614766B TW 106100742 A TW106100742 A TW 106100742A TW 106100742 A TW106100742 A TW 106100742A TW I614766 B TWI614766 B TW I614766B
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signal
circuit
pulse wave
volatile memory
precharge
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TW106100742A
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TW201727634A (zh
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賴子能
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力旺電子股份有限公司
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    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
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    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
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    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
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    • G06F21/72—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
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    • H—ELECTRICITY
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    • H03K—PULSE TECHNIQUE
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    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
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    • H—ELECTRICITY
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    • H10B—ELECTRONIC MEMORY DEVICES
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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  • Logic Circuits (AREA)
  • Detection And Correction Of Errors (AREA)
  • Storage Device Security (AREA)

Abstract

本發明為一種非揮發性記憶體包括：一記憶胞陣列與一控制電路。記憶體陣列具有複數條字元線與複數條位元線。控制電路包括：一處理電路、一解碼器、一驅動器、一時序控制器與一感測放大器。解碼器連接至該處理電路。驅動器連接至該解碼器與該些字元線。一時序控制器連接至該處理電路。感測放大器連接至該解碼器、該時序控制器與該些位元線。

Description

非揮發性記憶體
本發明是有關於一種非揮發性記憶體，且特別是有關於一種具時序控制器的非揮發性記憶體。
眾所周知，非揮發性記憶體中包括一記憶胞陣列(memory array)，記憶胞陣列係由多個記憶胞(memory cell)排列而成，而每個記憶胞中皆包含一浮動閘電晶體(floating gate transistor)。
另外，非揮發性記憶體中更包括一控制電路(controlling circuit)，用以控制記憶胞陣列進行編程動作、讀取動作、或者抹除動作。
因此，非揮發性記憶體在執行各種動作時，控制電路會依序產生各種信號至記憶胞陣列。如果這些信號的時序出現錯誤，則會發生運作失敗(fail)的狀況。
本發明之主要目的係提出一種非揮發性記憶體，包括：一記憶胞陣列，具有複數條字元線與複數條位元線；以及一控制電路，連接至該些字元線與該些位元線，其中該控制電路包 括：一處理電路，於一時脈信號的一第一信號緣產生一讀取指令；一解碼器，連接至該處理電路，用以接收該處理電路產生的該讀取址令，並產生一位址信號；一驅動器，連接至該些字元線，並根據該位址信號來驅動該些字元線其中之一；一時序控制器，連接至該處理電路，於該處理電路產生該讀取址令時，依序產生一預充電信號與一重置信號；以及一感測放大器，連接至該些位元線，其中，於該預充電信號動作時，將該些位元線調整至第一預定電壓；且於該重置信號動作時，根據該位址信號由該些位元線中決定一選定位元線組，並將該選定位元線組調整至一第二預定電壓；其中，該解碼器係由一第一類型元件所組成，該時序控制器由該第一類型元件與一第二類型元件所組成。
為了對本發明之上述及其他方面有更佳的瞭解，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下：
100‧‧‧非揮發性記憶體
110‧‧‧記憶胞陣列
150‧‧‧控制電路
152‧‧‧處理電路
154‧‧‧解碼器
156‧‧‧驅動器
160‧‧‧時序控制器
161‧‧‧前級脈波產生電路
162‧‧‧感測放大器
163、221、223‧‧‧反閘
164‧‧‧反或閘
165、220‧‧‧延遲電路
168‧‧‧次級脈波產生電路
172‧‧‧第一脈波產生器
174‧‧‧第二脈波產生器
176‧‧‧或閘
210‧‧‧邏輯電路
222‧‧‧第一反相電路
224‧‧‧第二反相電路
第1圖為本發明非揮發性記憶體示意圖。
第2A，其所繪示為非揮發性記憶體中的相關信號示意圖。
第2B圖為時序控制器示意圖。
第2C圖為前級脈波產生電路示意圖。
第3圖為製程變異時非揮發性記憶體中的相關信號示意圖。
第4A圖所繪示為本發明第二實施例的時序控制器。
第4B所繪示為本發明非揮發性記憶體中的相關信號示意圖。
第5圖所繪示本發明第二脈波產生器的一個範例。
請參照第1圖，其所繪示為本發明非揮發性記憶體示意圖。非揮發性記憶體100包括：一記憶胞陣列110與一控制電路150。再者，控制電路150中包括：一處理電路(processing circuit)152、解碼器(decoder)154、驅動器(driver)156、時序控制器(timing controller)160、與感測放大器(sense amplifier)162。
控制電路150中，處理電路152連接至解碼器154，而解碼器154連接至驅動器156與感測放大器162。另外，處理電路152連接至時序控制器160，而時序控制器160連接至感測放大器162。
再者，記憶胞陣列110具有m條字元線WL0~WLm-1以及n條位元線BL0~BLn-1。其中，驅動器156連接至記憶胞陣列110的位元線WL0~WLm-1，感測放大器162連接至記憶胞陣列110的字元線BL0~BLn-1。
以下介紹非揮發性記憶體100的讀取動作流程。基本上，非揮發性記憶體100會根據一時脈信號CLK來運作。於進行讀取動作時，處理電路152會將讀取指令(read command)傳送至解碼器154，而解碼器154解碼(decode)讀取指令後產生一位址信號Addr。再者，驅動器156根據位址信號Addr來驅動m條字元線WL0~WLm-1中的一特定字元線。另外，感測放大器162根 據位指信號Addr，於n條位元線BL0~BLn-1中決定一選定位元線組(selected bit line set)，並且對選定位元線組進行感測動作，以產生讀取資料(read data)。
舉例來說，當位址信號Addr產生後，驅動器156驅動字元線WL1。因此，記憶胞陣列110中連接至字元線WL1上的n個記憶胞會被驅動。而字元線WL1上的n個記憶胞對應地連接至n條位元線BL0~BLn-1。
再者，感測放大器162根據位址信號Addr，決定位元線BL0~BL7為選定位元線組。因此，感測放大器162即感測位元線BL0~BL7上的電壓變化，並進而決定位元線BL0~BL7上的邏輯準位作為讀取資料。換言之，讀取資料即代表連接至字元線WL1上前八個記憶胞的儲存狀態。
另外，在解碼器154產生位址信號Addr的過程，感測放大器162需要根據時序控制器160的預充電信號Precharge以及重置信號Reset來動作位元線，才可正確地產生讀取資料。
請參照第2A，其所繪示為非揮發性記憶體中的相關信號示意圖。第2B圖為時序控制器示意圖。第2C圖為前級脈波產生電路示意圖。
如第2A圖所示，於時間點t1，於時脈信號CLK的上升緣，處理電路152將讀取指令傳送至解碼器154。同時，處理電路152控制時序控制器160產生預充電信號Precharge至感測放大器162。
時間點t1至時間點t2之間為預充電周期(precharge period)。於時間點t1，時序控制器160產生一個脈波(pulse)的預充電信號Precharge至感測放大器162，且預充電信號Precharge 的脈波寬度(pulse width)即代表該預充電周期。
在預充電周期內，解碼器154解碼讀取指令並產生位址信號Addr。而感測放大器162根據預充電信號Precharge，在預充電周期內將所有的位元線BL0~BLn-1預充電至第一預定電壓(first predetermined voltage)。舉例來說，預充電周期為10ns，第一預定電壓為3.0V。
時間點t2至時間點t3之間為重置周期(reset period)。於時間點t2，時序控制器160根據預充電信號Precharge 的下降緣，產生一個脈波的重置電信號Reset至感測放大器162，且重置信號Reset的脈波寬度即代表該重置周期。
在重置周期內，而感測放大器162根據位址信號Addr於位元線BL0~BLn-1之中決定選定位元線組，並重置該選定位元線組至一第二預定電壓，而其他的位元線則維持在第一預定電壓。舉例來說，重置周期為10ns。再者，第一預定電壓相異於第二預定電壓，且第二預定電壓為，例如，接地電壓(ground voltage)。
於時間點t3之後即為發展與感測周期(developing and sensing period)。於發展與感測周期，連接於選定位元線組的對應記憶胞會產生記憶胞電流(cell current)至感測放大器162。而 根據記憶胞不同的儲存狀態，會有不同大小的記憶胞電流作為充電電流(charge current)。
因此，於發展與感測周期，選定位元線組上的電壓會由第二電壓(例如接地電壓)開始變化，而感測電放大器162即根據每條位元線的電壓變化大小來決定選定位元線組上的邏輯準位，並作為讀取資料。
如第2B圖所示，為了讓時序控制器160能夠產生預充電信號Precharge以及重置信號Reset。本發明第一實施例的時序控制器160包括一前級脈波產生電路(primary pulse generating circuit)161與次級脈波產生電路(secondary pulse generating circuit)168。
前級脈波產生電路161接收時脈信號CLK，並根據時脈信號CLK的上升緣(rising edge)產生預充電信號Precharge。另外，次級脈波產生電路168接收預充電信號Precharge，並根據預充電信號Precharge的下降緣(falling edge)產生重置信號Reset。因此，時序控制器160即可依序產生一個脈波的預充電信號Precharge以及一個脈波的重置信號Reset。
第2C圖為前級脈波產生電路161的一個範例。前級脈波產生電路161包括一邏輯電路與一延遲電路(delaying circuit)165，而邏輯電路包括一反閘163與一反或閘164。其中，反閘163接收時脈信號CLK產生反相的時脈信號CLKb；延遲電路(delaying circuit)165接收時脈信號CLK，延遲時間T之後，產 生延遲的時脈信號CLKd。反或閘164接收反相的時脈信號CLKb與延遲的時脈信號CLKd，並產生脈波寬度為T的預充電信號Precharge。同理，次級脈波產生電路168也可以利用類似的邏輯電路與延遲電路來產生重置信號Reset，此處不再贅述。
再者，由於記憶胞陣列110需要較高的操作電壓(operation voltage)，因此解碼器154與驅動器156需要利用高耐壓的元件(device)來實現，例如高耐壓的PMOS電晶體與NMOS電晶體。而時序控制器160與感測放大器162則利用低耐壓的元件來實現，例如低耐壓的PMOS電晶體與NMOS電晶體。
另外，在半導體製程中，可製造出二種不同耐壓類型的元件。第一種類型的元件為高耐壓的元件，又稱為I/O元件(I/O device)，其需要較高的第一操作電壓，例如6V。另外，第二種類型的元件為低耐壓的元件，又稱為核心元件(core device)，其需要較低的第二操作電壓，例如1.2V。換言之，I/O元件(I/O device)與核心元件(core device)需分別連接至不同的電源域(power domain)。
眾所周知，由於積體電路的製程參數變異(variation of fabrication parameters)，會產生各種製作角落(process corner)的元件，並導致不同的運作速度。舉例來說，快速-快速角落(fast-fast corner，簡稱FF corner)的元件，典型-典型角落(typical-typical corner，簡稱TT corner)的元件，或者慢速-慢速角落(slow-slow corner，簡稱SS corner)的元件。
典型-典型角落(TT corner)的元件，其NMOS電晶體與PMOS電晶體的運作速度(operation speed)符合設計著的要求(requirement)。快速-快速角落(FF corner)的元件，其NMOS電晶體與PMOS電晶體的運作速度較設計著的要求還要快速。慢速-慢速角落(SS corner)的元件，其NMOS電晶體與PMOS電晶體的運作速度較設計著的要求還要慢速。
非揮發性記憶體100的控制電路150中包括I/O元件所組成的解碼器154與驅動器165，以及核心元件所組成的時序控制器160、感測放大器162。而慢速-慢速角落(SS corner)的I/O元件可能造成非揮發性記憶體100讀取失敗的發生。說明如下：請參照第3圖，其所繪示為製程變異時非揮發性記憶體中的相關信號示意圖。
假設解碼器154的I/O元件為典型-典型角落(TT corner)的元件時，解碼器154可在預充電周期內(t1~t2)動作位址信號Addr，如曲線<I>。
再者，當解碼器154的I/O元件為快速-快速角落(FF corner)的元件時，則位址信號Addr的動作時間會往前移動。反之，當解碼器154的I/O元件為慢速-慢速角落(SS corner)的元件時，則位址信號Addr的動作時間會往後移動。
於正常運作時，解碼器154會在預充電周期內產生位址信號Addr，而感測放大器162會在重置周期內，根據位址信 號Addr進一步地決定選定位元線組，並重置該選定位元線組至一第二預定電壓。而進入發展與感測周期時，感測放大器162即可產生讀取資料。
然而，由於無法精準的控制積體電路的製程參數，如果解碼器154係由慢速-慢速角落(SS corner)的I/O元件所組成，且解碼器154在重置周期之後才產生位址信號Addr，如曲線<II>所示。則感測放大器162在重置周期會決定出錯誤的選定位元線組，並導致感測放大器162在發展與感測周期中產生錯誤的讀取資料，造成非揮發性記憶體100的讀取失敗(read fail)而無法正常運作。
由以上的說明可知，造成讀取失敗的原因在於製程變異，並使得解碼器154由慢速-慢速角落(SS corner)的元件所組成，導致解碼器154無法於預定周期(預充電周期)產生位址信號Addr。再者，由於時序控制器160無法因應上述製程變異，進而導致讀取失敗。
請參照第4A圖，其所繪示為本發明第二實施例的時序控制器。時序控制器160包括一前級脈波產生電路161與次級脈波產生電路168。
相同的運作原理，前級脈波產生電路161接收時脈信號CLK，並根據時脈信號CLK的上升緣(rising edge)產生預充電信號Precharge。次級脈波產生電路168接收預充電信號Precharge，並根據預充電信號Precharge的下降緣(falling edge) 產生重置信號Reset。因此，時序控制器160即依序產生一個脈波的預充電信號Precharge以及一個脈波的重置信號Reset。
本實施例的第二實施例在於前級脈波產生電路161包括一第一脈波產生器(pulse generator)172與第二脈波產生器174。其中，第一脈波產生器172係由核心元件(core device)所組成，而第二脈波產生器174係由I/O元件(I/O device)所組成。另外，第一脈波產生器172與第二脈波產生器174的電路結構類似第2C圖，皆具有一邏輯電路與一延遲電路，各自可產生脈波寬度為T的脈波。
由於控制電路150中的解碼器154與時序控制器160係製作於相同的積體電路(IC)上。因此，於製作I/O元件時，若發生製程變異時，則會同時影響到解碼器154與時序控制器160中的第二脈波產生器174。換言之，如果製程變異造成解碼器154由慢速-慢速角落(SS corner)的元件所組成，則第二脈波產生器174也會由慢速-慢速角落(SS corner)的元件所組成。
雖然第二脈波產生器174預計產生脈波寬度為T的脈波，但由於第二脈波產生器174係由慢速-慢速角落(SS corner)的元件所組成，將會使得第二脈波產生器174的脈波寬度大於T。而第二脈波產生器174的脈波寬度係相關於慢速-慢速角落(SS corner)的元件特性。意即，當第二脈波產生器174中的I/O元件特性越差時，其產生的脈波寬度會越寬。
在上述的情況下，如第4A圖所示，第一脈波產生 器產生脈波寬度為T的第一信號P1，第二脈波產生器產生脈波寬度為T’的第二信號P2。因此，經過或閘176後，前級脈波產生電路161即產生脈波寬度為T’的預充電信號。換言之，或閘176可視為一決定電路，將第一信號P1與第二信號P2中脈波寬度較大的脈波作為預充電信號Precharge。
請參照第4B，其所繪示為本發明非揮發性記憶體中的相關信號示意圖。其中，解碼器154與時序控制器160皆由慢速-慢速角落(SS corner)的元件所組成。
於時間點ta，於時脈信號CLK的上升緣，處理電路152將讀取指令傳送至解碼器154。同時，處理電路152控制時序控制器160產生預充電信號Precharge至感測放大器162。
時間點ta至時間點tb之間為預充電周期(precharge period)。由於解碼器154延後產生位址信號Addr，而時序控制器160也對應地延長預充電信號Precharge的脈波寬度為T’。因此，所以預充電周期會被延長，使得解碼器154仍在預充電周期內產生位址信號Addr。
因此，於時間點tb至時間點tc之間的重置周期。感測放大器162即可根據位址信號Addr於位元線BL0~BLn-1之中決定選定位元線組，並重置該選定位元線組至一第二預定電壓，而其他的位元線則維持在第一預定電壓。
而於時間點tc之後的發展與感測周期。連接於選定位元線組的對應記憶胞會產生記憶胞電流(cell current)至感測放 大器162。而感測電放大器162即可根據每條位元線的電壓變化大小來決定選定位元線組上的邏輯準位，並作為讀取資料。
另外，如果解碼器154與第二脈波產生器174係由典型-典型角落(TT corner)的元件所組成，則第二脈波的脈波寬度為T。再者，如果解碼器154第二脈波產生器174係由快速-快速角落(FF corner)的元件所組成，則第二脈波的脈波寬度為小於T。在以上的二種情況下，經由或閘176後，前級脈波產生電路162仍產生脈波寬度為T的預充電信號Precharge。
根據以上說明可知，本發明的優點在於提出一種運用於非揮發性記憶體中的時序控制器。時序控制器160中包括由核心元件所建構而成的第一脈波產生器172與I/O元件所建構而成的第二脈波產生器174。
根據製程變異，當解碼器154與第二脈波產生器174係由慢速-慢速角落(SS corner)所建構而成時，第二脈波產生器174可以改變輸出脈波的脈波寬度，用以改變預充電信號Precharge的脈波寬度以及預充電周期。如此，將可確保解碼器154於預充電周期內產生的位址信號Addr，並使得感測放大器162正確地產生讀取資料。
請參照第5圖，其所繪示本發明第二脈波產生器174的一個範例，且第二脈波產生器174皆由I/O元件所組成。第二脈波產生器174包括一邏輯電路210與一延遲電路220。其中，延遲電路220接收時脈信號CLK，延遲時間T之後，產生延遲的 時脈信號CLKd。再者，邏輯電路210接收時脈信號CLK與延遲的時脈信號CLKd，並產生第二信號P2。
基本上，邏輯電路210可以有各種實現的方式。例如，邏輯電路210可包括一反閘與一反或閘，依照第2C圖的連接方式，即可產生第二信號P2。
再者，延遲電路220包括串接的一第一反相電路(inverting circuit)222與一第二反相電路224。第一反相電路222具有一輸入端接收該時脈信號。第二反相電路224具有一輸入端連接至第一反相電路222的輸出端，第二反相電路224並具有一輸出端產生延遲的時脈信號CLKd。
第一反相電路222中包括PMOS電晶體p1、NMOS電晶體n1、電容器c1與緩衝器(buffer)221；第二反相電路224中包括PMOS電晶體p2、NMOS電晶體n2、電容器c2與緩衝器(buffer)223。經由控制電容器c1、c2的電容值，即可控制延遲電路220的延遲時間，並進一步地改變第二信號P2的脈波寬度。
該第一反相電路222包括：第一PMOS電晶體p1，具有一源極連接至一電壓源Vdd，一閘極連接至該第一反相電路222的該輸入端；第一NMOS電晶體n1，具有一源極連接至一接地端，一閘極連接至該第一反相電路222的該輸入端，一汲極連接至該第一PMOS電晶體p1的一汲極；一第一電容器c1，具有一第一端連接至該第一PMOS電晶體p1的該汲極，一第二端連接至該接地端；以及一第一緩衝器221，具有一輸入端連接至該 第一PMOS電晶體p1的該汲極，一輸出端作為該第一反相電路222的該輸出端。
該第二反相電路224包括：一第二PMOS電晶體p2，具有一源極連接至該電壓源Vdd，一閘極連接至該第一反相電路222的該輸出端；一第二NMOS電晶體n2，具有一源極連接至該接地端，一閘極連接至該第一反相電路222的該輸出端，一汲極連接至該第二PMOS電晶體p2的一汲極；一第二電容器c2，具有一第一端連接至該第二PMOS電晶體p2的該汲極，一第二端連接至該接地端；以及一第二緩衝器223，具有一輸入端連接至該第二PMOS電晶體p2的該汲極，一輸出端作為該第二反相電路224的該輸出端。
再者，本發明更可以設計第一反相電路222中的PMOS電晶體p1為一弱PMOS電晶體(weak PMOS transistor)而第二反相電路224中NMOS電晶體n2為一弱NMOS電晶體(weak NMOS transistor)。如此，可以讓第二脈波產生器174的脈波寬度更相關於慢速-慢速角落(SS corner)的元件特性。當然，也可以設計第一反相電路222中的NMOS電晶體n1為一弱NMOS電晶體而第二反相電路224中PMOS電晶體p2為一弱PMOS電晶體。
綜上所述，雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者 為準。
100‧‧‧非揮發性記憶體
110‧‧‧記憶胞陣列
150‧‧‧控制電路
152‧‧‧處理電路
154‧‧‧解碼器
156‧‧‧驅動器
160‧‧‧時序控制器
162‧‧‧感測放大器

Claims (12)

  1. 一種非揮發性記憶體，包括：一記憶胞陣列，具有複數條字元線與複數條位元線；以及一控制電路，連接至該些字元線與該些位元線；其中，該控制電路包括：一處理電路，於一時脈信號的一第一信號緣產生一讀取指令；一解碼器，連接至該處理電路，用以接收該處理電路產生的該讀取指令，並產生一位址信號；一驅動器，連接至該些字元線，並根據該位址信號來驅動該些字元線其中之一；一時序控制器，連接至該處理電路，於該處理電路產生該讀取指令時，依序產生一預充電信號與一重置信號；以及一感測放大器，連接至該些位元線，其中，於該預充電信號動作時，將該些位元線調整至第一預定電壓；且於該重置信號動作時，根據該位址信號由該些位元線中決定一選定位元線組，並將該選定位元線組調整至一第二預定電壓；其中，該解碼器係由一第一類型元件所組成，該時序控制器由該第一類型元件與一第二類型元件所組成，該第一類型元件係為高耐壓的元件，且該第二類型元件係為低耐壓的元件。
  2. 一種非揮發性記憶體，包括： 一記憶胞陣列，具有複數條字元線與複數條位元線；以及一控制電路，連接至該些字元線與該些位元線；其中，該控制電路包括：一處理電路，於一時脈信號的一第一信號緣產生一讀取指令；一解碼器，連接至該處理電路，用以接收該處理電路產生的該讀取指令，並產生一位址信號；一驅動器，連接至該些字元線，並根據該位址信號來驅動該些字元線其中之一；一時序控制器，連接至該處理電路，於該處理電路產生該讀取指令時，依序產生一預充電信號與一重置信號；以及一感測放大器，連接至該些位元線，其中，於該預充電信號動作時，將該些位元線調整至第一預定電壓；且於該重置信號動作時，根據該位址信號由該些位元線中決定一選定位元線組，並將該選定位元線組調整至一第二預定電壓；其中，該解碼器係由一第一類型元件所組成，該時序控制器由該第一類型元件與一第二類型元件所組成，該第一類型元件係為一I/O元件，該第二類型元件係為核心元件。
  3. 一種非揮發性記憶體，包括：一記憶胞陣列，具有複數條字元線與複數條位元線；以及一控制電路，連接至該些字元線與該些位元線； 其中，該控制電路包括：一處理電路，於一時脈信號的一第一信號緣產生一讀取指令；一解碼器，連接至該處理電路，用以接收該處理電路產生的該讀取指令，並產生一位址信號；一驅動器，連接至該些字元線，並根據該位址信號來驅動該些字元線其中之一；一時序控制器，連接至該處理電路，於該處理電路產生該讀取指令時，依序產生一預充電信號與一重置信號；以及一感測放大器，連接至該些位元線，其中，於該預充電信號動作時，將該些位元線調整至第一預定電壓；且於該重置信號動作時，根據該位址信號由該些位元線中決定一選定位元線組，並將該選定位元線組調整至一第二預定電壓；其中，該解碼器係由一第一類型元件所組成，該時序控制器由該第一類型元件與一第二類型元件所組成；其中，該時序控制器包括：一前級脈波產生電路，根據該時脈信號的該第一信號緣產生該預充電信號，且該預充電信號具有一第一脈波，該第一脈波的一脈波寬度為一預充電周期；以及一次級脈波產生電路，連接至該前級脈波產生電路，該次級脈波產生電路於該預充電周期後產生該重置信號，且該重置號具有一第二脈波，該第二脈波的一脈波寬度為一重置周期。
  4. 如申請專利範圍第3項所述之非揮發性記憶體，其中該前級脈波產生電路包括：一第一脈波產生器，接收該時脈信號並產生一第一信號；一第二脈波產生器，接收該時脈信號並產生一第二信號；以及一決定電路，當該第一信號的一脈波寬度大於該第二信號的一脈波寬度時，將該第一信號作為該預充電信號；以及當該第一信號的該脈波寬度小於該第二信號的該脈波寬度時，將該第二信號作為該預充電信號。
  5. 如申請專利範圍第4項所述之非揮發性記憶體，其中該第一脈波產生器係由該第一類型元件所組成；且該第二脈波產生器係由該第二類型元件所組成。
  6. 如申請專利範圍第4項所述之非揮發性記憶體，其中該第二脈波產生器包括：一延遲電路，接收該時脈信號，並產生一延遲的時脈信號；以及一邏輯電路，接收該時脈信號與該延遲的該時脈信號並產生該第二信號。
  7. 如申請專利範圍第6項所述之非揮發性記憶體，其中該延遲電路包括：一第一反相電路，具有一輸入端接收該時脈信號；以及一第二反相電路，具有一輸入端連接至該第一反相電路的一輸出端，並具有一輸出端產生該延遲的時脈信號。
  8. 如申請專利範圍第7項所述之非揮發性記憶體，其中該第一反相電路包括：一第一PMOS電晶體，具有一源極連接至一電壓源，一閘極連接至該第一反相電路的該輸入端；一第一NMOS電晶體，具有一源極連接至一接地端，一閘極連接至該第一反相電路的該輸入端，一汲極連接至該第一PMOS電晶體的一汲極；一第一電容器，具有一第一端連接至該第一PMOS電晶體的該汲極，一第二端連接至該接地端；以及一第一緩衝器，具有一輸入端連接至該第一PMOS電晶體的該汲極，一輸出端作為該第一反相電路的該輸出端。
  9. 如申請專利範圍第8項所述之非揮發性記憶體，其中該第二反相電路包括：一第二PMOS電晶體，具有一源極連接至該電壓源，一閘極連接至該第一反相電路的該輸出端； 一第二NMOS電晶體，具有一源極連接至該接地端，一閘極連接至該第一反相電路的該輸出端，一汲極連接至該第二PMOS電晶體的一汲極；一第二電容器，具有一第一端連接至該第二PMOS電晶體的該汲極，一第二端連接至該接地端；以及一第二緩衝器，具有一輸入端連接至該第二PMOS電晶體的該汲極，一輸出端作為該第二反相電路的該輸出端。
  10. 如申請專利範圍第9項所述之非揮發性記憶體，其中該第一PMOS電晶體為一弱PMOS電晶體，且該第二NMOS電晶體為一弱NMOS電晶體。
  11. 如申請專利範圍第9項所述之非揮發性記憶體，其中該第一NMOS電晶體為一弱NMOS電晶體，且該第二PMOS電晶體為一弱PMOS電晶體。
  12. 如申請專利範圍第3項所述之非揮發性記憶體，其中於該重置周期之後為一發展與感測周期，且於該發展與感測周期，該感測放大器根據該選定位元線組上的電壓變化來決定該選定位元線組上的邏輯準位，並作為一讀取資料。
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