TWI487072B - 垂直集成系統 - Google Patents
垂直集成系統 Download PDFInfo
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- TWI487072B TWI487072B TW100146568A TW100146568A TWI487072B TW I487072 B TWI487072 B TW I487072B TW 100146568 A TW100146568 A TW 100146568A TW 100146568 A TW100146568 A TW 100146568A TW I487072 B TWI487072 B TW I487072B
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- layer
- semiconductor die
- component
- integrated system
- integrated circuit
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Description
本發明係關於積體電路系統。詳言之,本發明係關於多層垂直集成系統,該等多層垂直集成系統具有遠離半導體晶粒之作用組件安置於該晶粒之背側上的組件。
近來,諸如蜂巢式電話、PDA及遊戲裝置之行動電子裝置已得到廣泛的常用性。如今,此等裝置已變為必需品而非奢侈品。結果,電子裝置已在大小上不斷減小以滿足消費者對於更小、更易於攜帶的裝置之需求。又,該等裝置已變得更複雜且將眾多功能性提供給消費者。然而,不同的功能性需要在電子裝置中之更多零件且增加裝置大小(在Z軸上,以及在X及Y軸上)。因此,工程師通常必須權衡更具功能性對較小之裝置大小的選擇。因此,工程師不斷地尋求方式來使包含電子裝置之電組件的大小最小化。
電子裝置通常包括在電路板上耦接在一起的各種積體電路。每一積體電路結合在電子裝置中之其他積體電路來執行功能。在材料科學中之進展已引起積體電路中之電晶體大小的減小,從而產生進入市場的更小且更複雜之電子裝置。電子裝置在積體電路晶片內提供所有電路系統以最小化空間將為理想的。遺憾地,現代製造技術不提供此等性能。因此,電子裝置常常包括複數個晶片及額外「離散」裝置。離散裝置為獨立於半導體晶粒而製造之組件,諸如電阻器、電容器、電感器等。離散組件常常提供於晶片外部但電連接至晶片內之某電路。離散組件常常安裝於鄰近於晶片之印刷電路板(PCB)上,此增加電子裝置大小。
因此,在此項技術中需要在離散被動組件不佔用昂貴空間之情況下將離散被動組件併入於電子零件中。
本發明之實施例提供一種積體電路系統,其包括:一第一作用層,其製造於一半導體晶粒之一前側上;及一第二預先製造層,其在該半導體晶粒之一背側上且具有體現於其中之電組件,其中該等電組件包括至少一離散被動組件。該積體電路系統亦包括將該第一作用層與該第二預先製造層耦接之至少一電路徑。
本發明之實施例提供一種包含一電路板及一垂直積體電路之電子裝置。該垂直積體電路安置於該電路板上且包含:一第一作用層,其製造於一半導體晶粒之一前側上;一第二預先製造層,其在該半導體晶粒之一背側上且具有體現於其中之電組件,其中該等電組件包括至少一離散被動組件;及至少一電路徑,其將該第一作用層與該第二預先製造層耦接。
本發明之實施例提供一種垂直積體電路,其包含:一作用層,其具有一主動式電路;及一組件層,其安置於該作用層之一背側上且具有複數個離散被動組件及鏈路,其中該等離散被動組件電連接至該主動式電路。
圖1為根據本發明之實施例的集成系統100之簡化方塊圖。集成系統100可包括具有兩個相反側(作用側120及背側130)之半導體晶粒110。該集成系統亦可包括安置於背側130上之被動組件140.1、140.2,被動組件140.1、140.2藉由諸如矽穿孔(TSV)150之電連接器耦接至作用側120。TSV 150可耦接至具有端子160之作用側120。
半導體晶粒110可為矽晶圓或其他已知的半導體晶粒材料。作用側120可位於該半導體晶粒之前側上且可包括在製造處理程序期間在其上所製造之主動式電路。可使用此項技術中之已知的技術來將主動式電路蝕刻至矽載體上。該主動式電路可包括半導體裝置,諸如可定義集成系統100之功能性的電晶體。
背側130可位於半導體之與半導體晶粒110上之作用側120相反的側上。可將被動組件140.1、140.2直接安裝於背側130上。被動組件140.1、140.2可為可獨立於半導體晶粒110製造處理程序而預先製造之離散組件。被動組件140.1、140.2可為對於藉由積體電路技術來製造為過大之組件。被動組件140.1、140.2可為不需要操作電源由此為被動之組件,諸如電阻器、電容器及電感器。被動組件140.1、140.2可包含陶瓷、矽或其他合適的材料。圖1僅出於說明目的而展示兩個被動組件140.1、140.2,且本發明之實施例可包括小於或大於2之不同數目個被動組件。舉例而言,根據本發明之積體電路可包括一個被動組件或可包括四個被動組件。
可取決於所涉及之特定材料使用導電黏著劑或導電膏、各向異性導電膜或任何其他合適的方法來將被動組件140.1、140.2附接或電耦接至半導體晶粒110之背側130。亦可使用不同於針對半導體晶粒110之製造處理程序的製造處理程序來製造被動組件140.1、140.2。被動組件製造處理程序可為與半導體晶粒製造處理程序相比成本較低之製造型處理程序,其可實現製造具有大於關於可用於更複雜結構之較精細幾何結構製造處理程序之效能特性的效能特性之被動離散組件。可使用諸如金接合、玻璃接合、陽極接合或任何其他合適之接合方法的多個不同處理程序來將所製造之基板(晶粒基板及被動組件基板)連結(join)。
TSV 150可為經蝕刻或雷射鑽孔穿過半導體晶粒110之通孔。在蝕刻出或雷射鑽孔出通孔之後,可接著電鍍該等通孔或用導電材料填充該等通孔以在作用側120與背側130之間提供電連接。可提供諸如凸塊化(bumping)或圖案化之後續處理步驟來製造在TSV 150與被動組件140.1、140.2之間的電連接。亦可在矽之背側內或頂部製造該等被動組件(作為TSV製造處理程序之部分)。舉例而言,可製造電感線圈或電阻器且將其鏈接至TSV。又,可修改TSV幾何結構及開口以促進經耦接之被動組件的最佳電性質,此係因為不同之被動組件可要求不同的TSV形狀、開口、深度、圖案等。舉例而言,可在TSV內製造電感螺線或線圈。又,可能要求特定縱橫比以將電荷保留或儲存於電容器中。因此,舉例而言,可修改與TSV同時製造之在矽之背側內的凹座以增強所需要之電性質。此外,端子160可完成在TSV 150與作用側120上之主動式電路之間的電連接。端子160(例如)可為焊料凸塊且亦提供至下一封裝層級之電連接。
在操作中,作用側120上之主動式電路可控制背側上之被動組件。主動式電路可在必要時存取背側130上之被動組件。因此,主動式電路可作為集成系統100之「腦」來操作。
集成系統100可以垂直方式併有在背側130上之被動組件140.1、140.2;因此,先前安裝於電路板上之被動組件現可置放於半導體晶粒之背側上,由此節約在電路板上之寶貴空間。將被動組件安裝於半導體晶粒內亦可減小藉由垂直集成系統所佔據之垂直高度(Z高度)。又,預先製造組件之使用實現混合不同的技術。舉例而言,可將啟用被動組件(諸如,電容器)之薄膜陶瓷基板併入至矽基晶粒中,由此產生單集成解決方案。
圖2為根據本發明之另一實施例的集成系統200之簡化方塊圖。集成系統200可包括具有兩個相反側(作用側220及背側230)之半導體晶粒210。該集成系統亦可包括安置於背側230上之被動組件240.1、240.2,被動組件240.1、240.2藉由諸如導電跡線250之電連接器耦接至作用側220。導電跡線250可耦接至具有端子260之作用側220。又,導電跡線250可沿著半導體晶粒210之側邊緣延行。集成系統200可能不需要經鑽孔穿過矽半導體晶粒210之通孔,同時仍以垂直方式併有在背側230上之被動組件240.1、240.2,此係因為導電跡線250可沿著半導體晶粒之邊緣將該兩個相反側耦接。
集成系統200之其他部分與在圖1之集成系統100中所展示的實施例中之彼等部分類似。因此,此處將不重複彼等部分之詳細描述。此外,出於清晰及簡要之目的,在以下實施例中將不對以上實施例所共有的一些部分進行進一步展示及描述。舉例而言,將不會進一步展示或描述至作用側之端子,此係因為一般熟習此項技術者將極好地理解,彼等部分在以下實施例中存在。
圖3為根據本發明之另一實施例的集成系統300之簡化方塊圖。集成系統300可包括將被動組件340.1、340.2與TSV 350耦接之線接合360。在以下情況下可能需要線接合:被動組件340.1、340.2與半導體晶粒係由具有不同的膨脹係數之不同材料製成,其適合於如用於多晶片模組之標準組裝製程(其中可使用標準線接合技術來將晶片電容器電連接)。若如此,則半導體晶粒及被動組件可在不同的溫度下以不同之速率膨脹及收縮,從而導致該兩個部分之間的連接中之裂縫。可經由用環氧樹脂(或另一合適之材料)囊封所安裝的組件及線接合來緩和此情形,該環氧樹脂(或另一合適之材料)將保護相關連結件/界面且使得藉由熱膨脹係數/材料不匹配所引起之應力能夠最小化且防止經由機械損壞的電斷開。
具有安裝於晶片之背側上的被動組件亦可允許在晶片設計中之更多的客製化(customization)。垂直集成設計可提供可容易地調諧及校準以配合多種不同應用的晶片。根據本發明之實施例,可提供在所有垂直集成層之組裝之後可調諧之集成系統。圖4(a)展示可在半導體裝置之背側上安裝的組件層400,組件層400具有被動組件,諸如電阻器410、電容器420、及電感器430、鏈路440,及TSV 450。組件層400可為諸如薄矽晶圓、陶瓷或玻璃基板之預先製造基板。舉例而言,該組件層可為材料為6、8或12吋之薄矽晶圓。組件層400可為矽基板、陶瓷基板或印刷電路板(PCB)型基板,且可在不同於作用矽載體之位點處被預先製造。此外,可藉由在基質矽上濺鍍、電鍍或沈積結構來製造預先製造基板。若組件層400為單獨的預先製造層,則可使用(例如)陽極接合、金接合、各向異性導電膜或另一合適之方法來將組件層400連結至作用層(載體矽)。
舉例而言,可使用比用於載體矽之製程較不複雜的製程來在矽上製造組件層400。不同的矽基板可使一些被動組件效能特性之製造容易。舉例而言,組件層400可具有與載體矽晶粒相比為較薄之幾何結構。可取決於所需要之效能特性來將被動組件至組件層400上或內之併入進一步最佳化。舉例而言,若製造電容器,則兩個平行板之深度及表面積提供(deliver)用以儲存電荷之更好容量。此情形可反映於用以將平行板之面積最大化之不同形狀/組合中,如下文在圖8(b)及圖8(c)的描述中所描述。
不同的製造處理程序可混合在一起以將特定被動組件之所要效能特性最大化。組件層400可電連接至載體矽,且組件層400可包括至併入於其中之被動組件的鏈路。該等鏈路可能能夠斷開或經修改,以使得併入於其中之被動組件的效能特性得以修改。因此,該集成系統在單體化之後可為可調諧的。
如在圖4(a)之局部放大部分中進一步展示,組件層400可包括被動組件之基本建置區塊陣列。組件層400可包括諸如電阻器410、電容器420及電感器430之被動組件。出於說明目的,圖4(a)將該等被動組件展示為其各別電路示意符號。可修置換件層400中之被動組件的陣列,以使得電連接至下方之載體矽(例如,經由電熔毀式(electrically blowing)熔斷型鏈路或雷射修整(laser trimming))的特定數目及類型之被動組件在整個系統被電連接(在單體化之前)時得以設定。因此,可調諧或校準整個垂直集成系統。
對於特定應用,被動組件可為可修改的或可調諧的。圖4(b)至圖4(e)說明可用以調諧被動組件之不同技術。圖4(b)以示意符號形式展示可具有總電阻值R3的電阻器組件。在此實例中,電阻可直接取決於電阻器之長度。因此,可將電阻器雷射修整以產生較小的電阻值。舉例而言,可將電阻器修整以產生如所示之較小的電阻R2及R1。或者,可隨著長度保持恆定而修改被動組件之寬度,以使得電阻可直接取決於被動組件的寬度。可藉由雷射修整、相關鏈路或結構之實體修改,或其他合適之技術來執行該修改。
圖4(c)展示調諧電阻值之另一方法。在此實例中,三個電阻器R1、R2及R3可串聯耦接。不同之鏈路L1、L2、L3及L4亦可提供於電阻器的連接中間。取決於哪一電阻值為較佳的,該等鏈路可選擇性地熔斷或斷開。舉例而言,若R2之電阻值為較佳的,則可斷開鏈路L1及L4,由此僅留下耦接至電阻器R2之每一末端的鏈路L2及L3。在另一實例中,若R1+R2之電阻值為較佳的,則可斷開鏈路L2及L4,由此僅留下以串聯方式提供R1及R2之鏈路L1及L3。此外,可相應地以與所配置之鏈路並聯的型式來配置電阻器。或者,可在共同軌道上將不同的鏈路L1、L2、L3及L4連接在一起,該共同軌道可隨後經修改以按設計來斷開或修改連接。
圖4(d)展示調諧電阻值之另一方法。在此實例中,可提供三個電阻器,以使得該等電阻器中之每一者可耦接至TSV。取決於哪一電阻值為較佳的,該等電阻器可經由線接合選擇性地耦接至TSV。在另一實施例中,所有電阻器可耦接至TSV,且隨後,至除一電阻器以外的所有電阻器之接合可斷開。又,可經由熔斷型鏈路來將垂直集成系統之層內的電結構連接,該等熔斷型鏈路可經電熔毀以便調諧系統。
圖4(e)說明調諧電容值之方法。圖4(e)展示被動離散電容器之橫截面圖及俯視圖。電容器可具有儲存電荷之兩個平行側A及B,且該兩個平行側可藉由介電質來分離。電容器之一側可包括可為可修改的電鏈路。舉例而言,可斷開該等鏈路,從而減小電容器板之大小,且由此減小電容。
在電感器之狀況中,性質可受在電感器線圈中之匝數影響。可藉由熔毀連接每一層上之匝的熔絲來修改在層之間的鏈路,該等層含有不同的匝數。可在每一層上連接多個匝及鏈路,且可熔斷(且接著電熔毀)或實體修改此等鏈路。
此外,組件層400亦可包括在被動組件與TSV 450之間的鏈路440,TSV 450電連接至在下方的作用層。因此,亦可斷開或變更鏈路400以調諧或修改集成系統。結果,可電測試作為完整堆疊之集成系統,且可隨後調諧、修改或校準在背側上的組件層中之組件。因為在所有層之組裝之後,垂直集成系統允許呈晶圓夾層形式之調諧、修改或校準,所以垂直集成系統可針對不同應用容易地客製化。又,可在完整堆疊經組裝、電測試及調諧之後將不同的個別系統單體化,從而引起至電路板上(或內)之下一封裝層級中的容易併入。
圖5為根據本發明之另一實施例的集成系統500之簡化方塊圖。集成系統500可包括具有作用側520及併有被動組件540.1、540.2之背側530的半導體晶粒。TSV 550可將被動組件540.1、540.2耦接至作用側520上之主動式電路。該集成系統可包括在背側530上之空腔560,其中安裝有被動組件540.1、540.2。又,集成系統500可包括保護層570。
空腔560可為蝕刻至半導體晶粒之背側中或形成於該背側內的凹座。藉由使得被動組件540.1、540.2安裝於空腔內,垂直集成系統之總系統高度大大減小,從而引起組件大小的進一步減小。
保護層570可藉由通孔耦接至諸如作用側520之在下方的層,且可將保護性覆蓋提供至被動組件540.1、540.2。保護層570可為電磁場(EMF)屏蔽。又,保護層570可包括用於集成系統500之接地平面或電源平面。因為保護層570係在其他層之頂部,所以保護層570可耗散藉由在下方之層所產生的熱量。保護層570亦可含有被動組件。因此,保護層570可提供EMF屏蔽且同時提供額外組件層。又,保護層570可為可修改的以調諧或校準集成系統500,例如在於單體化之前所有層組裝在一起時。可經由雷射修整、熔毀熔絲或其他已知的技術來電修改保護層570。
圖6為與圖5之集成系統500類似的根據本發明之另一實施例的集成系統600之簡化方塊圖。集成系統600可包括填充空腔之囊封劑610。囊封劑610在硬化時可圍繞被動組件而成模,從而將被動組件鎖定於適當位置。
根據本發明之另一實施例,集成系統可包括多個空腔。圖7(a)中之集成系統700可包括兩個空腔760.1、760.2,其中可分別在每一空腔中安裝被動組件740.1、740.2。又,每一空腔可具有安裝於其中之一個以上被動組件。圖7(b)展示可包括具有囊封劑790.1、790.2之多個空腔的集成系統780,囊封劑790.1、790.2分別填充該等空腔。囊封劑790.1、790.2在硬化時可圍繞被動組件而成模,從而將被動組件鎖定於適當位置。
可取決於被動組件之大小及被動組件的電性質以不同方式將被動組件安裝或嵌入於半導體晶粒內。圖8(a)說明根據本發明之實施例的以不同方式安裝於半導體晶粒之背側上的三個被動組件裝置。可將被動組件810.1直接安裝至無空腔且具有垂直高度Z1
之背側上。另一方面,可將被動組件810.2完整地安裝於空腔內,其中填充空腔之深度及寬度可改良被動組件810.2的電性質。舉例而言,增加空腔之深度可允許將更多的電阻性材料併入至空腔中,且由此增加總體電阻性質。
將被動組件810.2完整地嵌入於空腔內減小集成系統之垂直高度,此係因為被動組件810.2並未添加其自己的z高度。可將被動組件810.3安裝於背側上,以使得其填充空腔且亦重疊該空腔。藉由填充空腔之深度及寬度所達成的總體積及額外重疊可改良被動組件810.3之電性質。舉例而言,使材料圍繞空腔重疊可增加電阻性材料之總體積,且由此可增加總體電阻性質。此外,被動組件810.3之z高度Z2
小於直接安裝於背側上的被動組件810.1之垂直高度Z1
。因此,可藉由使用本文中所描述之不同安裝技術來減小系統的垂直高度。
安裝有被動組件之空腔或凹座可經成形及修改以將所需要之效能最佳化。舉例而言,圖8(b)展示根據本發明之實施例的集成系統820.1,集成系統820.1具有完整地處於空腔內之作為安裝於背側上之被動組件的電容器830.1。空腔及TSV經成形以使得電容器830.1之頂板840.1及底板850.1配合該空腔。此外,該空腔可經進一步修改以允許使用較高值之電容器。圖8(c)展示根據本發明之實施例的集成系統820.2,集成系統820.2具有在空腔中之作為安裝於背側上之被動組件的電容器830.2。可將此實施例中之空腔台階化以將電容器830.2之平行板(頂板840.2及底板840.3)的表面積最大化。因為電容與平行板之表面積直接相關,所以電容增加,且由此,所儲存之電荷的量增加。
圖9為根據本發明之另一實施例的集成系統900之簡化方塊圖。集成系統900可包括在彼此之頂部堆疊之多個被動組件,其中每一被動組件安裝於各別凹座中。第一凹座910.1可具有安裝於其中之被動組件940.1;第二凹座910.2可具有安裝於其中之被動組件940.2;且第三凹座910.3可具有安裝於其中之被動組件940.3。每一被動組件可如圖9中所展示藉由TSV電連接至作用側上之主動式電路。被動組件940.1可藉由成對之TSV 950.1連接至主動式電路,被動組件940.2可藉由成對之TSV 950.2連接至主動式電路,且被動組件940.3可藉由成對之TSV 950.3連接至主動式電路。每一凹座可蝕刻至具有台階化構形之半導體晶粒的背側中或形成於該背側內。半導體晶粒之背側內的凹座或空腔之「台階化」可使得許多不同的被動組件能夠併入至集成系統900中,同時最小化集成系統900之水平長度及垂直高度兩者。
可在尚仍與半導體晶粒分離之基板上將被動組件940.1、940.2、940.3預先製造在一起。可接著將預先製造基板插入至半導體晶粒之台階化凹座中以用於組裝。
圖10為與圖900之集成系統900類似的根據本發明之另一實施例的集成系統1000之簡化方塊圖。集成系統1000可包括填充空腔之囊封劑1010。囊封劑1010在硬化時可在每一凹座中圍繞被動組件而成模,從而將被動組件鎖定於適當位置。
此外,可將如圖11中所展示之保護層1110置放於被動組件之頂部。保護層1110可藉由通孔耦接至諸如作用側之在下方的層,且可將保護性覆蓋提供至被動組件。保護層1110可為電磁場(EMF)屏蔽。又,保護層1110可包括用於集成系統1100之接地平面或電源平面。因為保護層1110係在其他層之頂部,所以保護層1110可耗散藉由在下方的層所產生之熱量。保護層1110亦可含有被動組件。因此,保護層1110可提供EMF屏蔽且同時提供額外組件層。又,保護層1110可為可修改的以調諧或校準集成系統1100,例如在於單體化之前所有層組裝在一起時。可經由雷射修整、熔毀熔絲或其他已知的技術來電修改保護層1110。
圖12(a)為根據本發明之另一實施例的集成系統1200之簡化方塊圖。集成系統1200可使用置放於背側上之電感器線圈來將來自不同電壓域之晶粒的電信號隔離及耦接。集成系統1200可包括藉由隔離障壁1230所分離之低電壓晶粒1210及高電壓晶粒1220。該集成系統亦可包括被動組件1240.1、1240.2,及一對電感器線圈1250.1、1250.2。
低電壓晶粒1210及高電壓晶粒1220在經電分離之不同電壓域上操作。隔離障壁1230可將該兩個晶粒電分離且可由非導電材料製成。被動組件1240.1、1240.2可併入至背側中(或沈積於背側之頂部),且可直接耦接至低電壓晶粒1210之主動式電路。被動組件1240.1、1240.2亦可耦接至電感器線圈1250.1、1250.2中之一者,而另一線圈可耦接至高電壓晶粒1220之主動式電路。因此,集成系統1200可使用電感器線圈1250.1、1250.2來經由包括被動組件1240.1、1240.2之預先製造基板將在該兩個晶粒(低電壓晶粒1210及高電壓晶粒1220)之間的電信號隔離及磁性耦接。預先製造基板層亦可含有如上文所描述之保護層。
亦可在線圈內包括鐵磁性材料。圖12(b)為根據本發明之實施例的併入至集成系統中之電感器之簡化方塊圖。該電感器可具有鐵磁性磁芯1260.1及圍繞鐵磁性磁芯1260.1纏繞之線圈1270.1。可將該電感器預先製造且安裝至半導體晶粒之背側上。又,該電感器可連接至具有諸如TSV之導電路徑的作用側。
圖12(c)為根據本發明之實施例的至集成系統中之電感器之簡化方塊圖。該電感器可具有鐵磁性磁芯1260.2及圍繞鐵磁性磁芯1260.2纏繞之線圈1270.2。在此實施例中,可將該電感器預先製造且插入於在半導體晶粒之背側上的空腔內。又,該電感器可連接至具有諸如TSV之導電路徑的作用側。
圖12(d)為根據本發明之實施例的至集成系統中之電感器之簡化方塊圖。該電感器可具有鐵磁性磁芯1260.3及圍繞鐵磁性磁芯1260.3纏繞之線圈1270.3。在此實施例中,可在半導體晶粒之背側內製造該電感器。又,該電感器可連接至具有諸如TSV之導電路徑的作用側。
可使用鐵磁性材料來形成在集成系統之層內的變壓器。該變壓器可為升壓或降壓變壓器。舉例而言,可將形成於層內之變壓器用作RF變壓器。圖12(e)說明根據本發明之實施例的變壓器形成方法。預先製造層A 1280.1可含有圍繞鐵磁性磁芯1281纏繞之線圈1282。層A 1280.1可為所製造之PCB、陶瓷或其他合適基板。層A 1280.1亦可含有其他被動組件、屏蔽、電源平面及接地平面。層A 1280.1亦可含有至其他層之連接。另一層B 1290.1可為半導體晶粒之背側。層B 1290.1可含有圍繞安裝於半導體晶粒背側中之空腔內的鐵磁性磁芯1291纏繞之線圈1292。可連結該兩個層(層A 1280.1及層B 1290.1),且可連接每一各別層之鐵磁性磁芯1281、1291以形成具有線圈1281及線圈1282的變壓器,線圈1281為變壓器之頂部線圈且線圈1282為底部線圈。此外,囊封劑可填充空腔。或者,可將變壓器直接安裝至半導體晶粒的背側上。
圖12(f)說明根據本發明之實施例的變壓器形成方法。圖12(f)中之變壓器可含有如所示圍繞鐵磁性磁芯纏繞之一對線圈。該變壓器可形成於基板上,該基板經安裝而具有至晶粒之背側上的厚的介電質。該介電質可在熱量及壓力下變形,從而留下可安裝於晶粒之背側上的暴露之磁芯末端。
圖13為根據本發明之另一實施例的集成系統1300之簡化方塊圖。與圖12(a)之集成系統1200類似,集成系統1300亦可使用置放於背側上之電感器線圈來將至及來自不可直接耦接的不同電壓晶粒之電信號隔離及耦接;然而,在集成系統1300中,亦將包括被動組件之基板用作在不同電壓晶粒之間的隔離電路。集成系統1300可包括低電壓晶粒1310、高電壓晶粒1320、隔離障壁1330、被動組件1340.1及一對電感器線圈1350.1、1350.2。在此實施例中,高電壓晶粒1320可堆疊於低電壓晶粒1310之頂部,其中隔離障壁1330係在該兩個晶粒中間以將該兩個晶粒電隔離。隔離電路可為如在本發明中所描述之包括被動組件的預先製造基板。
在集成系統1300之另一態樣中,低電壓晶粒1310中之主動式電路可控制包括被動組件1340.1及高電壓晶粒1320電路之其他層的操作。低電壓晶粒1310可存取其他層。
圖14為與圖1300之集成系統1300類似的根據本發明之另一實施例的集成系統1400之簡化方塊圖。集成系統1400可進一步包括在高電壓晶粒1420上之微機電系統(MEMS)1460.1、1460.2。舉例而言,低電壓晶粒1410可含有儲存針對MEMS 1460.1、1460.2之機械位置(諸如,針對迴轉儀之初始位置)的記憶體部分。當集成系統1400在操作中時,可將MEMS之敏感度及輸出正規化至初始機械位置。其他應用實例可包括用於在不同頻帶中之天線調諧的以串聯或並聯配置之RF MEMS開關。
隔離障壁1430亦可含有定位於線圈之間的鐵磁性材料。該等鐵磁性材料可在集成系統內按需要提供升壓或降壓變壓器。
根據本發明之另一實施例,光學系統可將來自在不同的隔離域中操作之不同晶粒的電信號隔離及耦接。圖15(a)為包括光學系統之集成系統1500的簡化方塊圖。集成系統1500可包括低電壓晶粒1510、高電壓晶粒1520、隔離障壁1530及被動組件1540.1。集成系統1500亦可包括具有光電晶體1550、LED 1560.1及波導1570之光學系統。在此實施例中,高電壓晶粒1520可堆疊於低電壓晶粒1510之頂部,其中隔離障壁1530係在該兩個晶粒中間以將該兩個晶粒電隔離。隔離電路可為如上文所描述之包括被動組件的預先製造基板。
在此實施例中,光學系統可將在兩個不同操作電壓晶粒1510與1520之間的電信號隔離及光學耦接。光電晶體1550.1可置放於該等晶粒中之一者(例如,高電壓晶粒)上,且對應的LED 1560.1可置放於另一晶粒上。波導1570.1亦可置放於光電晶體1550.1與LED 1560.1中間以便使光波能夠行進。波導1570可形成於隔離障壁1530內。在操作中,低電壓晶粒1510上之主動式電路可接通在波導1570.1之一末端上的LED 1560.1作為通信信號。在波導1570.1之另一末端處的光電晶體1550.1將感測何時LED 1560.1被接通且將資訊傳輸至高電壓晶粒1520電路上的電路。因此,低電壓晶粒1510中之主動式電路可控制包括被動組件1540.1及高電壓晶粒1520電路之其他層的操作。低電壓晶粒1510在必要時可存取其他層。
或者,光學系統可為根據本發明之實施例的如圖15(b)中所展示之在層之間的雙向通信系統。在雙向通信系統中,每一晶粒可包括光電晶體1550.1、1550.2及LED 1560.1、1560.2,從而允許在兩個方向上的通信。
此外,當在一層上並排置放兩個晶粒時,可使用光學系統。圖15(c)為根據本發明之實施例的集成系統1503之簡化方塊圖。低電壓晶粒1510.3及高電壓晶粒1520.3可在同一層上且可藉由隔離障壁1530.3分離。光學系統可安裝於該兩個晶粒上。光學系統可包括光電晶體1550.3、LED 1560.3及波導1570.3。
圖16之集成系統1600展示作用側上之主動式電路可存取不同的被動組件之方式的根據本發明之實施例。集成系統1600可包括被動組件1610.1、1610.2,及置放於耦接至被動組件及主動式電路之頂部基板中的電感器線圈1630至1650。電感器線圈1630至1650可開啟/關斷以啟動/撤銷啟動被動組件1610.1、1610.2。舉例而言,主動式電路可在其需要存取被動組件1610.1時將電壓發送至電感器線圈1630.1、1630.2。一對電感器線圈亦可控制對被動組件之區塊的存取而非對僅一被動組件之存取。
在半導體晶粒之背側上的不同層/材料之集成可導致結構不穩定性。在不同層之間的黏著對於保持結構完整性可為關鍵的(在垂直集成系統之操作/壽命期間且亦在個別垂直集成系統之單體化期間)。在多層系統中於不類似之材料層之間的熱膨脹係數(CTE)產生在邊緣上集中的應力。換言之,可導致層之間的接合之剪切及剝落的應力在邊緣上為最強的,當多層系統含有不同材料之許多薄層時此情形可加劇。因此,根據本發明,提供將在所嵌入之組件之邊緣處的黏著最大化且因此改良垂直集成系統之機械穩固性的下文所描述之不同實施例。
圖17(a)展示根據本發明之實施例的集成系統1700。集成系統1700可包括在半導體晶粒周邊中之軌道。圖17(a)之頂部區段展示具有兩個軌道之晶粒之平面圖,且底部區段展示具有該兩個軌道的橫截面圖。可藉由雷射切口或藉由蝕刻或能夠提供所需要之變形的某其他製程來在半導體晶粒之背側上形成軌道。該等軌道形成用於將囊封劑嵌入於內之隆脊,由此將該多個層更牢固地彼此附接。
圖17(b)展示根據本發明之實施例的集成系統1710。集成系統1710可包括在半導體晶粒周邊中之正方形物。圖17(b)之頂部區段展示具有正方形物之晶粒之平面圖,且底部區段展示具有該等正方形物的橫截面圖。可藉由雷射切口或藉由蝕刻或能夠提供所需要之變形的某其他製程來在半導體晶粒之背側上形成該等正方形物。該等正方形物形成用於將囊封劑嵌入於內之隆脊,由此將該多個層更牢固地彼此附接。
圖17(c)展示根據本發明之實施例的集成系統1720。集成系統1720可包括在半導體晶粒周邊中之同心圓。圖17(c)之頂部區段展示具有兩個同心圓之晶粒之平面圖,且底部區段展示具有該兩個同心圓的橫截面圖。可藉由雷射切口或藉由蝕刻或能夠提供所需要之變形的某其他製程來在半導體晶粒之背側上形成該等同心圓。該等同心圓形成用於將囊封劑嵌入於內之隆脊,由此將該多個層更牢固地彼此附接。
圖17(d)展示根據本發明之實施例的集成系統1730。集成系統1730可包括在半導體晶粒周邊中之交錯台階。圖17(d)之頂部區段展示具有交錯台階之晶粒之平面圖,且底部區段展示具有該等交錯台階的橫截面圖。可藉由雷射切口或藉由蝕刻或能夠提供所需要之變形的某其他製程來在半導體晶粒之背側上形成該等台階。該等台階形成用於將囊封劑嵌入於內之隆脊,由此將該多個層更牢固地彼此附接。
可在必要時將所使用之圖案及形狀最佳化以改良在層之間的黏著及鎖定。可藉由增加表面積且亦藉由提供凹座/渠溝/區域(取決於所使用之圖案或形狀)來達成此情形,待連結之材料的一部分在該凹座/渠溝/區域中填充/固化/硬化以使得其經機械鎖定。可將所使用之圖案及形狀最佳化以將完整垂直集成結構的穩固性最大化(經由單體化製程以及經由系統之操作壽命)。
可將根據本發明之集成系統嵌入於PCB型結構內。因此,該集成系統可併有其他鎖定特徵以確保該集成系統可牢固地嵌入於PCB型結構或其他結構內。圖18說明根據本發明之實施例的集成系統之邊緣。半導體晶粒1810及組件層1820兩者可具有如所示之鋸齒形邊緣或另一形狀構形以改良黏著且由此允許更牢固地嵌入於最終基板內。如下文中進一步詳細地描述,可在單體化製程期間形成邊緣加工(edge finish)。
圖19進一步說明根據本發明之實施例的在平面圖及橫截面圖中之集成系統1900中的邊緣加工。集成系統1900可包括半導體晶粒1910、在作用區中之金屬墊1920,及切割道1930。金屬墊1920可用於連接至另一層。切割道1930可包括諸如鋸齒形邊緣之邊緣加工,從而產生可隨後藉由囊封劑填充之間隙。
圖20說明可形成邊緣加工之方式。切割道2010可經製造而具有開口2020。可藉由雷射切割或其他已知的技術來形成開口2020,且開口2020可為如所示之圓形或另一形狀。可在開口2020中製造用於集成系統之單體化的最終切口2030以產生圖19中所展示之鋸齒形邊緣加工。可藉由雷射、劃片機(dicing saw)或其他已知的裝置來製造最終切口2030。
圖21為根據本發明之另一實施例的集成系統2100之簡化方塊圖。集成系統2100展示根據本發明之使用改良在兩個層之間的黏著之鎖定特徵的該兩個層之互連。集成系統2100可包括鎖定溝槽2110.1、2110.2、鎖定台階2120及囊封劑2130。
與圖17中所展示之實施例類似,鎖定溝槽2110.1、2110.2可位於晶粒之邊緣上。鎖定台階2120可為自安裝有被動組件之表面升起的台階。鎖定溝槽2110.1、2110.2可改良集成系統之構造的穩固性,此係因為鎖定溝槽2110.1、2110.2更堅固地緊固所保護之背側塗層。結果,邊緣層之分層或分離的可能性大大減小。因為背側層更牢固地黏附至晶粒,所以此情形亦轉譯為併入於背側上之被動裝置更牢固地黏附。
可藉由在晶粒之背側上蝕刻來形成鎖定溝槽2110.1、2110.2。此外,可將囊封劑填充至溝槽中且囊封劑可填充開口且接著硬化以機械地鎖定於晶粒內。與平坦表面相比,鎖定溝槽2110添加更多之接觸表面積,由此改良黏著。相同概念對於鎖定台階2120為成立的。
圖22展示鎖定溝槽2220之放大圖以便說明鎖定溝槽改良黏著之方式。根據本發明之實施例,可藉由蝕刻如圖22中所展示之凹座來進一步改良黏著,其中溝槽之最寬部分「b」大於表面上之開口「a」。因為b>a,所以接觸表面積增加,甚至進一步產生改良之黏著。
圖23為根據本發明之另一實施例的改良黏著之集成系統2300之簡化圖。集成系統2300可包括鎖定溝槽2320、囊封劑2330及鎖定層2340。在組裝中,可將鎖定層2340添加至第一溝槽集合。接著,可將囊封劑2330添加至第二溝槽集合且亦添加於鎖定層2340內。由於在層之間的界面處之材料經由熱量、壓力等而變形且填充溝槽,因此該材料將硬化,此情形可機械地鎖定及緊固整個集成系統以及增加表面積,增加表面積亦將最大化黏著。可修改開口特徵及表面圖案(諸如,變更凹座/開口之形狀及使在不同層內的位置交錯)以實現最佳化,以使得整個集成系統更穩固。
根據本發明之實施例,亦可對半導體晶粒之作用側進行修改以改良黏著。圖24之集成系統2400說明此等修改。集成系統2400可包括半導體晶粒2410、介電層2430、金屬墊2440.1、2440.2,及鎖定切口2450。金屬墊2440.1、2440.2可為用以連接至下一封裝層級(諸如,PCB)的暴露之金屬接點。在金屬墊2440.1、2440.2中間,介電層2430可包括增加接觸表面積之鎖定切口2450,由此改良黏著。作為凸塊化/晶圓處理之部分,可製造鎖定切口2450。
圖25展示根據本發明之實施例的包括能夠截留(trapping)或鎖定囊封劑之鎖定切口或溝槽的作用側之平面圖。集成系統2500可包括鎖定切口2550.1、2550.2及金屬墊2540。如所示,鎖定切口2550.1、2550.2可為蝕刻於頂層介電質中之同心圓。金屬墊2540可為用以連接至下一封裝層級(諸如,PCB)之暴露的金屬接點。
在本發明之另一實施例中,可修改TSV之形狀以便改良含於內之導電材料的黏著。舉例而言,可修改在半導體晶粒之背側上的TSV開口,以使得被動組件之端子可更牢固地嵌入於晶粒中,從而使得整個集成系統更穩固。圖26(a)展示具有圓形開口之TSV 2610之平面圖,且圖26(b)展示具有不規則形狀之開口的TSV 2620之平面圖。TSV 2610及TSV 2620兩者可具有相同半徑r。在電鍍製程步驟中,與具有圓形開口之TSV 2610相比,具有不規則形狀之開口的TSV 2620具有待用導電材料填充之在通孔內的較小體積。TSV 2620開口具有小於TSV 2610之表面積(對於圓形開口為π*r2
)的表面積。因此,可修改TSV開口形狀以產生針對在通孔內之導電材料的最佳化黏著效應,從而使得集成系統更穩固。
此外,在通孔內之導電層的分離及分層可引起針對集成系統的嚴重問題。然而,如本文中所描述之根據本發明之實施例的通孔構造可更牢固地固持導電材料,且因此,使得集成系統更穩固。
如下文更詳細地論述,根據本發明之實施例的集成系統亦可用於流體、氣體等之分析中,且通孔可用作用於在層之間的移動之管道。取決於特定應用,該等通孔可經建構以將通過開口之材料流動最佳化至最佳速率。圖26(c)展示根據本發明之實施例的TSV 2630之橫截面圖。TSV 2630可包括不同的台階化同心開口,以使得可將通過該層之實體流動控制至特定速率。舉例而言,自該層之頂部至該層之底部的材料流動可減小,此係由於TSV 2630之逐漸變窄的構形。圖26(d)展示根據本發明之實施例的TSV 2640之橫截面圖。TSV 2640可包括不同的傾斜同心開口,以使得可將通過該層之實體流動控制至特定所要速率。或者,通孔可經修改以產生其他最佳化形狀之螺旋,以便促進在液位之間的流體移動之所要速率。舉例而言,通孔可經修改以充當過濾或流動速率減小製程之部分,以使得可監測pH位準,諸如在如下情況下:穿過垂直集成系統內之特定層或
區域的流體展示可辨別的經量測電性值,且該等層經實體建構以提供所要流動速率以使得可持續地監測流體的pH值。
根據本發明之實施例,可將TSV置放於半導體晶粒之非作用區域中,此係因為某些電路可能具有直接在主動式電路上方之TSV的問題。舉例而言,在某些類型之電路上方之通孔的併入可引起可影響系統之效能的機械應力且引起參數偏移問題。圖27展示作用側之平面圖及具有主動式電路2710及TSV陣列2720之集成系統2700的橫截面圖。TSV陣列2720可位於主動式電路2710之周邊上,由此位於半導體晶粒之非作用區域上。區域「d」為在主動式電路2710與最接近之TSV 2720.1之間的最小距離,以便將在該兩個部分之間的干擾最小化。
此外,在另一實施例中,取決於TSV之應用,TSV可能並不填充有導電材料。舉例而言,光學系統或冷卻系統可使用不要求導電材料填充於其中之TSV。因此,非導電TSV仍可連接垂直集成系統之不同層。
垂直集成系統可出現發熱問題。主動式電路以及被動組件可在操作時產生熱量。過量之熱量可損壞電零件且使集成系統之總體效能惡化。圖28為根據本發明之另一實施例的集成系統2800之簡化圖。集成系統2800可包括散熱片2810及熱型TSV 2820。散熱片2810可為熱結塊或高導熱材料區塊。將圖28中之散熱片2810展示為附接至鎖定台階;然而,可將散熱片2810附接至冷卻板或其他界面。熱型TSV 2820可將熱量自晶粒之作用側傳導至背側。因此,散熱片2810及熱型TSV 2820結合起來耗散自作用側所產生之熱量,從而防止過熱,由此改良集成系統的總體效能。或者,如下文所描述,可使用藉由系統所產生之熱量來改良集成系統之總體效率(亦即,經由使用熱電產生層)。此外,可修改(例如,放大)用以傳送熱量之熱型TSV 2820以將熱效率最佳化。
圖29為根據本發明之另一實施例的集成系統2900之簡化圖。集成系統2900可包括散熱片2910及熱型TSV 2920。散熱片2910可為熱結塊或高導熱材料區塊。將圖29中之散熱片2910展示為附接至鎖定台階;然而,可將散熱片2910附接至冷卻板或其他界面。熱型TSV 2920可將熱量自晶粒之作用側傳導至背側。散熱片2910可整體地覆蓋作用側上之主動式電路,且可在所耗散熱量上比部分地覆蓋主動式電路之散熱片更有熱效率。隨著散熱片之大小增加,散熱片之熱效率亦增加,此係因為熱效率直接與散熱片的大小成比例。
根據本發明之另一實施例,冷卻層亦可在耗散在垂直集成系統中所產生之熱量時使用。圖30(a)為根據本發明之另一實施例的集成系統3000之簡化圖。集成系統3000可包括半導體晶粒3010、TSV 3020、冷卻層3030,及具有被動組件3050.1、3050.2之組件層3040。組件層3040可藉由TSV 3020電耦接至在半導體晶粒3010之作用側上的主動式電路。冷卻層3030亦可包括通孔以支撐在組件層3040與主動式電路之間的電連接。取決於冷卻層材料,冷卻層3030中之通孔可為或可能不為穿矽的。冷卻層3030可為冷卻板或微流體系統以將熱量耗散最佳化。
圖30(b)為冷卻層3030之一實施例之簡化圖。冷卻層3030可包括冷卻劑材料可穿過之微通道。冷卻層3030亦可容納微流體泵系統以使冷卻劑環流,由此移除熱量。可將冷卻劑插入於一末端中且泵汲至另一末端。結果,冷卻劑環流可降低集成系統中之溫度。
圖31(a)為冷卻層3100之另一實施例之簡化圖。冷卻層3100可包括帕耳帖(peltier)或熱電型冷卻系統。冷卻層3100可包括熱側3020、冷側3030及通道3040.1至3040.n。冷卻層3100亦可藉由通孔3010耦接至下方的層。通孔3010可為熱型通孔,且通孔3010可將冷卻層3010(例如)耦接至散熱片或PCB。可選擇性地使用通道3040.1至3040.n以將熱量耗散至熱側3020中之特定區域及在特定區域中耦接至熱側的通孔3010。可接著使熱量耗散通過通孔3020,從而防止過熱。在此實施例中,至特定區域中之目標熱量耗散可經最佳化。可藉由指引熱量通過此等通孔朝向熱電層來進一步最佳化系統。此層亦可經組態以將冷卻應用於垂直集成系統內之特定區域。
除耗散熱量之外,冷卻層亦可用作熱電產生層,其中熱量(例如,自垂直集成系統內之其他組件或層所產生)轉換為電荷。圖31(b)為熱電產生層3100.1之實施例的簡化圖。熱電產生層3100.1可包括熱側3020、冷側3030及通道3040.1至3040.n。熱電產生層3100.1亦可耦接至下方的熱量產生層3050,熱量產生層3050可含有被動組件或其他高功率組件。熱電產生層3100.1可使用自系統內所產生之熱量來產生電流,可接著將該電流儲存或重新散佈於該系統內。熱電層可被併入以將所產生之電荷的量最大化。舉例而言,熱側3020可熱連接至來自該系統內之熱點,且冷側3030亦可連接至冷卻層或連接至其他結構以使得在熱側3020與冷側3030之間的溫度差分別可最大化,且由此,可產生最大電流。因此,該集成系統可收穫作為熱量所耗散之能量且使該能量再循環以向該集成系統供電且由此節省電力。
此外,可使用橫向通道以用於熱量耗散需要。橫向通道亦可將在熱電層之熱面與冷面之間的溫度差最大化,且因此將所產生之電荷最大化。圖32為根據本發明之另一實施例的集成系統3200之簡化圖。圖32展示作用側之平面圖及集成系統3200之橫截面圖。集成系統3200可包括主動式電路2710、TSV陣列3220及橫向通道3230。橫向通道3230可安置於在主動式電路3210上方之半導體晶粒中且與前側及背側平行地延行。橫向通道3230亦可用以併有微流體冷卻、光學傳輸系統等。藉由在橫向通道下方之主動式電路所產生的熱量可藉由橫向通道耗散。
橫向通道亦可位於垂直集成系統之不同層(諸如,冷卻層)中。圖33(a)為根據本發明之另一實施例的集成系統3300之簡化圖。集成系統3300可包括半導體晶粒3310、TSV 3320、具有橫向通道3335之冷卻層3330,及具有被動組件3350.1、3350.2之組件層3340。組件層3040可藉由TSV 3320電耦接至半導體晶粒3010之作用側上的主動式電路。冷卻層3330亦可包括用導電材料填充之通孔3337以支撐在組件層3340與主動式電路之間的電連接。取決於冷卻層材料,通孔3337可為或可能不為穿矽的。
圖33(b)為併有微流體冷卻系統之冷卻層3330之一實施例的簡化圖。冷卻層3330可包括冷卻劑材料可穿過之橫向通道3335。冷卻層3330亦可容納微流體泵系統以使冷卻劑環流,由此移除熱量。
此外,橫向通道可用於不同於冷卻系統之其他目的。舉例而言,光學傳輸線路可位於橫向通道中以便提供通信鏈路。圖34(a)為與圖33(a)之集成系統3300類似的根據本發明之另一實施例的集成系統3400之簡化圖。集成系統3400可包括冷卻層3340,冷卻層3340具有作為如圖34(b)中所展示之光學通道3415操作的橫向通道。光學通道3415可包括光管、光纖等。亦可在能量收穫應用中利用光學隔離。舉例而言,當可使能量再循環回至電池供應器時,可經由光學隔離鏈路將升高的電壓位準(超過對裝置所施加之供應電壓)置換(shuffle)為該供應電壓,以避免由於任何電流或電壓突增而使電池超載之任何可能的不利效應。光學通道亦可用以實際上升高電壓且使用光源及光電二極體陣列升高至所要電壓位準來產生次級供應電壓。
對於一些應用(例如,觸覺或觸控式螢幕技術),可藉由觸碰螢幕以存取螢幕上之功能來產生大的電壓。隨著選擇不同的選項,產生電荷且必須將其「傾出(dump)」。根據本發明之實施例的集成系統可提供含有如下結構(例如,電容器)之層:可儲存此「所傾出的」電荷且接著經由系統使其再環流。因此,根據本發明之集成系統可收穫藉由系統之不同刻面所產生的能量以改良總體電力效率且亦在避免「鋰事件」時提供重要的安全性特徵。
一些積體電路應用可能要求諸如流體、氣體等之材料的分析。按照慣例,通常需要處於積體電路外部之單獨零件以用於固持及量測需要被分析的材料。根據本發明之實施例,可將量測層併入於半導體晶粒之背側上,由此減少針對給定應用所需要之單獨零件的數目。
圖35(a)為根據本發明之實施例的集成系統3500之簡化圖。集成系統3500可包括半導體晶粒3510、TSV 3520、量測層3530,及具有被動組件3550.1、3550.2之組件層3540。量測層3530可包括如圖34(b)中所展示之可操控或分析所穿過之流體或其他材料的通道。舉例而言,該量測層可監測流體之pH位準、監測針對液體之流動速率、監測氣體濃度等。
量測層3530可包括用於耦接至上方之層及下方之層的電連接。該等電連接可為用導電材料填充之通孔。量測層3530亦可包括其他電子電路以提供表示監測量之電信號及將該信號提供至集成系統3500中的其他層。舉例而言,量測層3530可包括電子電路以產生表示所分析之液體之pH位準的類比信號。此外,該量測層可進一步包括電子電路以提供過濾、分離及分析性能。舉例而言,可將MEMS裝置併入至該量測層中。該量測層亦可併有將流體、氣體等之操控最佳化的機械特徵及結構。
圖36為根據本發明之實施例的集成系統3600之簡化圖。集成系統3600可包括冷卻層3610及量測層3620。冷卻層3610可與上文所描述之冷卻層類似,且量測層3620可與上文所描述之量測層類似。冷卻層3610及量測層3620可結合地工作以量測材料同時冷卻集成系統3600,此情形係由於在層之間的相互作用。舉例而言,冷卻層3610可包括自主動式電路吸收熱量之發熱元件。
該等發熱元件亦可加速穿過量測層3620之材料的處理。因此,集成系統3600使用藉由一層所產生之通常對系統有害的熱量來更好地操作諸如量測層的另一層。舉例而言,量測層3620可包括用於待分析之液體的通道。自冷卻層3620所輸送之熱量可加速通過量測層中之通道之液體的移動,從而引起更快的操作。諸如分離、過濾等之其他分析操作亦可藉由熱量來加速。此外,冷卻層3610及量測層3620可包括可與集成系統3600中之其他層通信的其他電子電路。
根據本發明之另一實施例,可使用通過垂直集成系統之不同層的通孔作為用於分析之通道。圖37為根據本發明之實施例的集成系統3700之簡化圖。通孔3710.1、3710.2可穿過集成系統3700之一些層或所有層。通孔3710.1、3710.2可操控或分析流體或其他材料,諸如穿過通孔之氣體。集成系統3700中之一層可包括提供分析操作(諸如,分離、過濾等)之電子電路(例如,MEMS)。
通孔設計之一益處為其節省電力。重力可在集成系統內之通孔中輸送材料。因此,集成系統將需要較少電力。圖38說明材料可穿過通孔3810.1、3810.2之方式。箭頭展示重力可將材料自頂層通過集成系統3800移動至底層的方式。可按需要來修改此等通孔之特定設計以適合於特定應用。
可在根據本發明之垂直集成系統中使用其他電力節約技術。圖39為根據本發明之實施例的集成系統3900之簡化圖。集成系統3900可包括具有作用側3920及背側3930之半導體晶粒3910、光伏打層3940及TSV 3950。光伏打層3940可形成或安裝於背側3930上且可為可藉由雷射修整來修改的。光伏打層3940可包括將太陽光線轉變為電能之有機光伏打電池。該等電池可包括允許光耦接至活性材料由此產生電能之透明導電電極。電能可接著向集成系統3900供電,由此提供自供電系統。
圖40(a)為根據本發明之實施例的集成系統4000之簡化圖。集成系統可包括光伏打層4010.1、具有開口4030.1之耐光層4020.1,及電儲存組件4040.1。耐光層4020.1可安置於該光伏打層之頂部且可包括按策略置放之開口4030.1。耐光層4020.1可為若干目的服務。該耐光層可保護在集成系統4000中之可藉由曝光損壞之其他電零件。通過開口4030.1之耐光層4020.1亦可經圖案化以控制光及電流之流動。可將開口4030.1最佳化以將自光伏打層4010.1至在下方之其他層的電流最大化。此外,電儲存組件4040.1可位於在開口4030.1下方之區中,以便儲存及操控藉由光伏打層4010.1所產生的電荷。主動式電路可控制電儲存組件4040.1之操作。舉例而言,主動式電路可在應用要求使用某些組件時存取某些電儲存組件。因此,電力使用可藉由主動式電路有效地控制。或者,耐光層可併有按策略置放之光伏打電池以在特定區域中產生電荷。此外,可使用光管及其他光傳輸裝置來將來自外部源之光轉向、導通及集中至該集成系統內的特定光伏打電池,且由此將所產生之電荷最大化。
可將光伏打層及耐光層換位,其中光伏打層處於耐光層之頂部。圖40(b)為根據本發明之實施例的集成系統4001之簡化圖。集成系統4001可包括光伏打層4010.2、具有開口4030.2之耐光層4020.2,及電儲存組件4040.2。在此實施例中,光伏打層4010.2可處於耐光層4020.2之頂部且可為最頂層。藉由光伏打層4010.2所產生之電荷與曝露至光之區域成比例。因此,將光伏打層4010.2定位於頂部可將所產生之電荷的量最大化。又,耐光層4020.2之選擇性圖案化可保護積體電路之一些區域免於曝光。
垂直集成系統可取決於其應用而以不同方式來配置。圖41為根據本發明之實施例的集成系統4100之簡化圖。集成系統4100可包括光伏打層4110、具有開口4125之耐光層4120、組件層4130及電儲存組件4140。組件層4130可包括被動組件。耐光層4120可處於組件層4130下方,且光伏打層4110可處於耐光層4120下方。因為光伏打層4110處於少許層下方,所以開口4125可按策略圖案化以將自光伏打層4010至在下方之其他層的電流最大化。又,在此實施例中,亦可按策略定位組件層4130,以使其不覆蓋開口。此外,電儲存組件4140可位於在開口4125下方之區中,以便儲存及操控藉由光伏打層4110所產生的電荷。主動式電路可控制電儲存組件4140之操作。
在其他實施例中,可將光伏打層作為最頂層置放於垂直集成系統中。圖42為根據本發明之實施例的集成系統4200之簡化圖。在集成系統4200中,具有被動組件之組件層4230可處於光伏打層4210下方。因為光伏打層4230為最頂層,所以其增加用於曝光之表面積。藉此,增加所產生之電能的量。
在其他實施例中,光伏打層可結合熱電層來工作。圖43為根據本發明之實施例的集成系統4300之簡化圖。在集成系統4300中,可將光伏打層4310提供於熱電層4320及具有被動組件之組件層4330的頂部。熱電產生層4320可包括熱側、冷側及通道。熱電產生層4320可使用自該系統內所產生之熱量來產生電流(收穫電荷),可接著將該電流儲存或重新散佈於該系統內。另外,熱電產生層4320亦可自光伏打層4310收穫電荷。集成系統4300可包括諸如電容器之組件以儲存所收穫的電荷。此外,可修改在該等層之間的攜載電荷之鏈路以改良電流的移動之速率。可經由收穫在該系統內所產生之熱量且亦收穫自其他來源(諸如,光伏打層)所產生之電荷來大大地改良該集成系統的能量效率。所收穫之電荷可經儲存及遍及該系統重新散佈,(例如)以對電池充電。
在根據本發明之集成系統的一應用中,可在諸如警示系統之監測系統中使用該集成系統。圖44為根據本發明之實施例的集成系統4400之簡化圖。集成系統4400可包括信號傳輸層4410及組件層4440。集成系統4400亦可包括本文中在其他實施例中所描述之其他組件。信號傳輸層4410可包括諸如電感器線圈之線圈4420,及可連接至該集成系統內之其他層的通孔4430。在量測某一條件後,線圈4420即可產生所得信號。可接著將該所得信號自該集成系統傳輸至另一遠端位置(例如,警示命令中心)。舉例而言,該集成系統可監測流體之pH位準,且若所監測之pH位準超過預定位準,則該集成系統可傳輸該所得信號。
在另一實施例中,根據本發明之集成系統可包括在一層中之能夠接收遠端信號的電感器。該遠端信號之接收可啟動該集成系統或該集成系統之一部分。電感線圈可按策略遍及該集成系統而定位以啟動/撤銷啟動該集成系統的不同部分及功能性。
另外,根據本發明之集成系統可併有諸如熱電偶或光纖鏈路之遠端感測管道。該遠端感測管道可允許遠端輸入饋給至該集成系統內的層。舉例而言,可將具有感測元件之熱電偶置放於惡劣環境(諸如,高溫環境)中。該熱電偶可接著與該集成系統內之層通信且提供可能原本不可得到之重要資訊。
可在多種電子裝置及應用中使用根據本發明之集成系統。圖45為根據本發明之實施例的電子裝置4500之簡化方塊圖。電子裝置4500可包括電路板4510,電路板4510可具有安裝於電路板4510上或內之集成系統4520。集成系統4520可包括本文中在其他實施例中所描述之組件。電路板4510可耦接至電子裝置4500之其他組件,諸如處理器4530、使用者介面4540及其他合適的電組件。
處理器4530可控制電子裝置4500及其組件之操作。處理器4500可為包括微處理器、數位信號處理器及場可程式化邏輯陣列之習知處理系統中的任一者或組合。
使用者介面4540可包括諸如LCD螢幕、CRT、電漿螢幕、LED螢幕或其類似者之顯示器。使用者介面4540可為鍵盤、滑鼠、觸控式螢幕感測器,或將允許使用者與電子裝置4500互動之任何其他使用者輸入裝置。使用者介面4540可包括硬鍵及/或螢幕按鍵。舉例而言,使用者介面4540可以觸控式螢幕顯示器之形式與顯示器集成。電子裝置4500可取決於電子裝置應用而包括其他組件。電子裝置4500可為可自根據本發明之集成系統之併入獲益的攜帶型電子裝置,諸如數位相機、蜂巢式電話、警示系統、遊戲裝置或其類似者。根據本發明之集成系統之併入可減小電子裝置的大小同時將效能最大化。
本文特定地說明且描述本發明之若干實施例。然而,應瞭解,在不脫離本發明之精神及預期範疇的情況下,本發明之修改及變化係藉由上文之教示涵蓋且涵蓋於所附申請專利範圍之範圍內。此外,應瞭解,在不脫離本發明之精神及預期範疇的情況下,可結合使用來自不同實施例之不同組件。在其他例子中,未詳細描述熟知之操作、組件及電路以便不會混淆實施例。可瞭解,本文中所揭示之特定結構及功能細節可為代表性的且未必限制實施例之範疇。
可使用硬體元件、軟體元件或兩者之組合來實施各種實施例。硬體元件之實例可包括處理器、微處理器、電路、電路元件(例如,電晶體、電阻器、電容器、電感器等等),積體電路、特殊應用積體電路(ASIC)、可程式化邏輯裝置(PLD)、數位信號處理器(DSP)、場可程式化閘陣列(FPGA)、邏輯閘、暫存器、半導體裝置、晶片、微晶片、晶片組等等。軟體之實例可包括軟體組件、程式、應用程式、電腦程式、應用程式、系統程式、機器程式、作業系統軟體、中間軟體、韌體、軟體模組、常式、子常式、函式、方法、程序、軟體介面、應用程式介面(API)、指令集、計算程式碼、電腦程式碼、程式碼片段、電腦程式碼片段、字、值、符號或其任何組合。判定使用硬體元件及/或軟體元件來實施實施例可根據任何數目個因素而變化,諸如所要計算速率、功率位準、熱容限、處理循環預算、輸入資料速率、輸出資料速率、記憶體資源、資料匯流排速度,及其他設計或效能約束條件。
可(例如)使用可儲存指令或指令集之電腦可讀媒體或物品來實施一些實施例,該指令或指令集在藉由機器執行時可使得該機器執行根據實施例之方法及/或操作。此機器可包括(例如)任何合適之處理平台、計算平台、計算裝置、處理裝置、計算系統、處理系統、電腦、處理器或其類似者,且可使用硬體及/或軟體之任何合適組合來實施。該電腦可讀媒體或物品可包括(例如)任何合適類型之記憶體單元、記憶體裝置、記憶體物品、記憶體媒體、儲存裝置、儲存物品、儲存媒體及/或儲存單元,例如記憶體,抽取式或非抽取式媒體、可抹除或非可抹除媒體、可寫或可重寫媒體、數位或類比媒體、硬碟、軟性磁碟、緊密光碟唯讀記憶體(CD-ROM)、可記錄式緊密光碟(CD-R)、可重寫式緊密光碟(CD-RW)、光碟、磁性媒體、磁光媒體、抽取式記憶卡或磁碟、各種類型之數位影音光碟(DVD)、磁帶、卡帶或其類似者。該等指令可包括使用任何合適之高階、低階、物件導向式、視覺、編譯及/或解譯程式設計語言所實施之任何合適類型的程式碼,諸如原始程式碼、經編譯程式碼、經解譯程式碼、可執行程式碼、靜態程式碼、動態程式碼、經加密程式碼及其類似者。
100...集成系統
110...半導體晶粒
120...作用側
130...背側
140.1...被動組件
140.2...被動組件
150...矽穿孔(TSV)
160...端子
200...集成系統
210...半導體晶粒
220...作用側
230...背側
240.1...被動組件
240.2...被動組件
250...導電跡線
260...端子
300...集成系統
340.1...被動組件
340.2...被動組件
350...矽穿孔(TSV)
360...線接合
400...組件層
410...電阻器
420...電容器
430...電感器
440...鏈路
450...矽穿孔(TSV)
500...集成系統
520...作用側
530...背側
540.1...被動組件
540.2...被動組件
550...矽穿孔(TSV)
560...空腔
570...保護層
600...集成系統
610...囊封劑
700...集成系統
720...作用側
730...背側
740.1...被動組件
740.2...被動組件
750...矽穿孔(TSV)
760.1...空腔
760.2...空腔
770...保護層
780...集成系統
790.1...囊封劑
790.2...囊封劑
810.1...被動組件
810.2...被動組件
810.3...被動組件
820.1...集成系統
820.2...集成系統
830.1...電容器
830.2...電容器
840.1...頂板
840.2...頂板
850.1...底板
850.2...底板
900...集成系統
910.1...第一凹座
910.2...第二凹座
910.3...第三凹座
940.1...被動組件
940.2...被動組件
940.3...被動組件
950.1...矽穿孔(TSV)
950.2...矽穿孔(TSV)
950.3...矽穿孔(TSV)
1000...集成系統
1010...囊封劑
1100...集成系統
1110...保護層
1200...集成系統
1210...低電壓晶粒
1220...高電壓晶粒
1230...隔離障壁
1240.1...被動組件
1240.2...被動組件
1250.1...電感器線圈
1250.2...電感器線圈
1260.1...鐵磁性磁芯
1260.2...鐵磁性磁芯
1260.3...鐵磁性磁芯
1270.1...線圈
1270.2...線圈
1270.3...線圈
1280.1...預先製造層A
1280.2...層A
1281...鐵磁性磁芯
1282...線圈
1290.1...層B
1290.2...層B
1291...鐵磁性磁芯
1292...線圈
1300...集成系統
1310...低電壓晶粒
1320...高電壓晶粒
1330...隔離障壁
1340.1...被動組件
1350.1...電感器線圈
1350.2...電感器線圈
1400...集成系統
1410...低電壓晶粒
1420...高電壓晶粒
1430...隔離障壁
1440.1...被動組件
1450.1...電感器線圈
1450.2...電感器線圈
1460.1...微機電系統(MEMS)
1460.2...微機電系統(MEMS)
1500...集成系統
1503...集成系統
1510...低電壓晶粒
1510.3...低電壓晶粒
1520...高電壓晶粒
1520.3...高電壓晶粒
1530...隔離障壁
1530.3...隔離障壁
1540.1...被動組件
1550...光電晶體
1550.1...光電晶體
1550.2...光電晶體
1550.3...光電晶體
1560.1...發光二極體
1560.2...發光二極體
1560.3...發光二極體
1570...波導
1570.1...波導
1570.2...波導
1570.3...波導
1600...集成系統
1610.1...被動組件
1610.2...被動組件
1630...電感器線圈
1630.1...電感器線圈
1630.2...電感器線圈
1640...電感器線圈
1640.1...電感器線圈
1640.2...電感器線圈
1650...電感器線圈
1650.1...電感器線圈
1650.2...電感器線圈
1700...集成系統
1710...集成系統
1720...集成系統
1730...集成系統
1810...半導體晶粒
1820...組件層
1900...集成系統
1910...半導體晶粒
1920...金屬墊
1930...切割道
2010...切割道
2020...開口
2030...最終切口
2100...集成系統
2110...鎖定溝槽
2110.1...鎖定溝槽
2110.2...鎖定溝槽
2120...鎖定台階
2130...囊封劑
2210...半導體晶粒
2220...鎖定溝槽
2300...集成系統
2310...半導體晶粒
2320...鎖定溝槽
2330...囊封劑
2340...鎖定層
2400...集成系統
2410...半導體晶粒
2420...鎖定溝槽
2430...介電層
2440.1...金屬墊
2440.2...金屬墊
2450...鎖定切口
2500...集成系統
2540...金屬墊
2550.1...鎖定切口
2550.2...鎖定切口
2610...矽穿孔(TSV)
2620...矽穿孔(TSV)
2630...矽穿孔(TSV)
2640...矽穿孔(TSV)
2700...集成系統
2710...主動式電路
2720...TSV陣列
2720.1...矽穿孔(TSV)
2800...集成系統
2810...散熱片
2820...熱型TSV
2900...集成系統
2910...散熱片
2920...熱型TSV
3000...集成系統
3010...半導體晶粒/通孔
3020...矽穿孔(TSV)/熱側/通孔
3030...冷卻層/冷側
3040...組件層
3040.1至3040.n...通道
3050...熱量產生層
3050.1...被動組件
3050.2...被動組件
3100...冷卻層
3100.1...熱電產生層
3200...集成系統
3210...主動式電路
3220...TSV陣列
3230...橫向通道
3300...集成系統
3310...半導體晶粒
3320...矽穿孔(TSV)
3330...冷卻層
3335...橫向通道
3337...通孔
3340...組件層/冷卻層
3350.1...被動組件
3350.2...被動組件
3400...集成系統
3415...光學通道
3500...集成系統
3510...半導體晶粒
3515...通孔
3520...矽穿孔(TSV)
3530...量測層
3540...組件層
3550.1...被動組件
3550.2...被動組件
3600...集成系統
3610...冷卻層
3620...量測層
3700...集成系統
3710.1...通孔
3710.2...通孔
3800...集成系統
3810.1...通孔
3810.2...通孔
3900...集成系統
3910...半導體晶粒
3920...作用側
3930...背側
3940...光伏打層
3950...矽穿孔(TSV)
4000...集成系統
4001...集成系統
4010.1...光伏打層
4010.2...光伏打層
4020.1...耐光層
4020.2...耐光層
4030.1...開口
4030.2...開口
4040.1...電儲存組件
4040.2...電儲存組件
4100...集成系統
4110...光伏打層
4120...耐光層
4125...開口
4130...組件層
4140...電儲存組件
4200...集成系統
4210...光伏打層
4230...組件層
4300...集成系統
4310...光伏打層
4320...熱電層/熱電產生層
4330...組件層
4400...集成系統
4410...信號傳輸層
4420...線圈
4430...通孔
4440...組件層
4500...電子裝置
4510...電路板
4520...集成系統
4530...處理器
4540...使用者介面
A...平行側
B...平行側
L1...鏈路
L2...鏈路
L3...鏈路
L4...鏈路
R1...電阻器
R2...電阻器
R3...電阻器
圖1為根據本發明之實施例的集成系統之方塊圖。
圖2為根據本發明之實施例的集成系統之方塊圖。
圖3為根據本發明之實施例的集成系統之方塊圖。
圖4(a)說明根據本發明之實施例的組件層。
圖4(b)說明根據本發明之實施例的電阻器調諧。
圖4(c)說明根據本發明之實施例的電阻器調諧。
圖4(d)說明根據本發明之實施例的電阻器調諧。
圖4(e)說明根據本發明之實施例的電容器調諧。
圖5為根據本發明之實施例的集成系統之方塊圖。
圖6為根據本發明之實施例的集成系統之方塊圖。
圖7(a)為根據本發明之實施例的集成系統之方塊圖。
圖7(b)為根據本發明之實施例的集成系統之方塊圖。
圖8(a)為根據本發明之實施例的集成系統之方塊圖。
圖8(b)為根據本發明之實施例的集成系統之方塊圖。
圖8(c)為根據本發明之實施例的集成系統之方塊圖。
圖9為根據本發明之實施例的集成系統之方塊圖。
圖10為根據本發明之實施例的集成系統之方塊圖。
圖11為根據本發明之實施例的集成系統之方塊圖。
圖12(a)為根據本發明之實施例的集成系統之方塊圖。
圖12(b)至圖12(d)為根據本發明之實施例的包括電感器之集成系統之方塊圖。
圖12(e)至圖12(f)為根據本發明之實施例的包括變壓器之集成系統的方塊圖。
圖13為根據本發明之實施例的集成系統之方塊圖。
圖14為根據本發明之實施例的集成系統之方塊圖。
圖15(a)為根據本發明之實施例的集成系統之方塊圖。
圖15(b)為根據本發明之實施例的集成系統之方塊圖。
圖15(c)為根據本發明之實施例的集成系統之方塊圖。
圖16為根據本發明之實施例的集成系統之方塊圖。
圖17(a)說明根據本發明之實施例的集成系統之平面圖及橫截面圖。
圖17(b)說明根據本發明之實施例的集成系統之平面圖及橫截面圖。
圖17(c)說明根據本發明之實施例的集成系統之平面圖及橫截面圖。
圖17(d)說明根據本發明之實施例的集成系統之平面圖及橫截面圖。
圖18說明根據本發明之實施例的集成系統之邊緣的橫截面圖。
圖19說明根據本發明之實施例的集成系統之平面圖及橫截面圖。
圖20說明根據本發明之實施例的集成系統之切割道。
圖21為根據本發明之實施例的集成系統之方塊圖。
圖22說明根據本發明之實施例的鎖定機構。
圖23說明根據本發明之實施例的鎖定機構。
圖24為根據本發明之實施例的集成系統之方塊圖。
圖25說明根據本發明之實施例的作用側之平面圖。
圖26(a)至圖26(d)說明根據本發明之實施例的矽穿孔。
圖27說明根據本發明之實施例的集成系統之平面圖及橫截面圖。
圖28為根據本發明之實施例的集成系統之方塊圖。
圖29為根據本發明之實施例的集成系統之方塊圖。
圖30(a)為根據本發明之實施例的集成系統之方塊圖。
圖30(b)說明根據本發明之實施例的冷卻層。
圖31(a)說明根據本發明之實施例的冷卻層。
圖31(b)說明根據本發明之實施例的熱電產生層。
圖32說明根據本發明之實施例的集成系統之平面圖及橫截面圖。
圖33(a)為根據本發明之實施例的集成系統之方塊圖。
圖33(b)說明根據本發明之實施例的冷卻層。
圖34(a)為根據本發明之實施例的集成系統之方塊圖。
圖34(b)說明根據本發明之實施例的冷卻層。
圖35(a)為根據本發明之實施例的集成系統之方塊圖。
圖35(b)說明根據本發明之實施例的量測層。
圖36為根據本發明之實施例的集成系統、冷卻層及量測層之方塊圖。
圖37為根據本發明之實施例的集成系統之方塊圖。
圖38為根據本發明之實施例的集成系統之方塊圖。
圖39為根據本發明之實施例的集成系統之方塊圖。
圖40(a)為根據本發明之實施例的集成系統之方塊圖。
圖40(b)為根據本發明之實施例的集成系統之方塊圖。
圖41為根據本發明之實施例的集成系統之方塊圖。
圖42為根據本發明之實施例的集成系統之方塊圖。
圖43為根據本發明之實施例的集成系統之方塊圖。
圖44為根據本發明之實施例的集成系統之方塊圖。
圖45為根據本發明之實施例的電子裝置之方塊圖。
100...集成系統
110...半導體晶粒
120...作用側
130...背側
140.1...被動組件
140.2...被動組件
150...矽穿孔(TSV)
160...端子
Claims (34)
- 一種積體電路系統,其包含:一第一作用層,其製造於一半導體晶粒之一前側上;一第二預先製造層,其在該半導體晶粒之一背側上且具有體現於其中之電組件及連接該等電組件之一或多個鏈路,其中該等電組件包括至少一離散被動組件;及至少一電路徑,其耦接該第一作用層與該第二預先製造層;及其中該一或多個鏈路係可修改以在該第一作用層與該第二預先製造層之組裝後調諧該積體電路系統之效能。
- 如請求項1之積體電路系統,其中該至少一電路徑為一矽穿孔(TSV)或在該半導體晶粒之一側邊緣上的一導電跡線。
- 如請求項1之積體電路系統,其中該第二預先製造層安置於該半導體晶粒之一空腔中,且其中該第二預先製造層係基於該至少一離散被動組件之電性質而組態。
- 如請求項3之積體電路系統,其進一步包含一保護層,該保護層安置於該半導體晶粒之該背側上且覆蓋該至少一離散被動組件。
- 如請求項1之積體電路系統,其進一步包含耦接至該被動離散元件之一電感線圈,該電感線圈啟動及撤銷啟動該被動離散元件。
- 如請求項1之積體電路系統,該背側包括一黏附特徵,該黏附特徵位於該半導體晶粒之該邊緣上或該晶粒之周 邊上。
- 如請求項1之積體電路系統,該背側包括一鎖定台階,該鎖定台階具有大於該至少一離散組件之一垂直高度。
- 如請求項1之積體電路系統,其進一步包含具有一半徑r之一TSV開口,該TSV開口具有一小於π*r2 之面積。
- 如請求項1之積體電路系統,其進一步包含電耦接至該第一作用層之一散熱片。
- 如請求項1之積體電路系統,其進一步包含安置於該背側上之冷卻層及併入於至少一系統層中之一橫向通道。
- 如請求項1之積體電路系統,其進一步包含將該前側與該背側耦接之一TSV陣列,該TSV陣列位於距該前側上之一作用部分一預定距離處。
- 如請求項1之積體電路系統,其進一步包含安置於該背側上之一熱電產生層,該熱電產生層將在該積體電路系統內所產生之熱量轉換為電荷。
- 如請求項1之積體電路系統,其進一步包含安置於該背側上之一量測層,該量測層可操作以分析穿過該垂直集成系統之至少一部分的流體且電耦接至該第一作用層。
- 如請求項1之積體電路系統,其進一步包含安置於該背側上之一光伏打層。
- 如請求項1之積體電路系統,其進一步包含在一與該半導體晶粒垂直集成之微機電系統(MEMS)晶粒上之一MEMS組件。
- 一種積體電路系統,其包含: 一第一半導體晶粒,其在一基板上,該第一半導體晶粒包括在一前側上之一作用層;一組件層,其與該第一半導體晶粒垂直集成,該組件層包括至少一離散被動組件;至少一電路徑,其耦接該作用層與該組件層;一第二半導體晶粒,其在不同於該第一半導體晶粒之一電壓下操作,且安置於與該第一半導體晶粒相同之基板上;及一隔離障壁,其經組態以將該第一半導體晶粒及該第二半導體晶粒彼此電隔離。
- 如請求項16之積體電路系統,其中該積體電路系統可在該第一作用層與該第二預先製造層之組裝後以晶圓夾層形式調諧,且可操作以作為一完整系統被存取及供電,且可操作以待隨後修改。
- 如請求項16之積體電路系統,其進一步包含:一光學系統,其用於以光學方式耦接在該第一半導體晶粒與該第二半導體晶粒之間的電路。
- 如請求項16之積體電路系統,其進一步包含一對電感線圈,其用以磁性耦接在該第一半導體晶粒與該第二半導體晶粒之間的電路。
- 如請求項16之積體電路系統,其進一步包含一變壓器,其經組態以傳送在該第一半導體晶粒與該第二半導體晶粒之間的資料。
- 如請求項16之積體電路系統,其中該第一半導體晶粒與 該第二半導體晶粒係與在其間之該隔離障壁並列地定位。
- 如請求項16之積體電路系統,其中該第一半導體晶粒與該第二半導體晶粒係與在其間之該隔離障壁彼此定位於頂部。
- 如請求項16之積體電路系統,其中該第二半導體晶粒包含一MEMS元件。
- 如請求項18之積體電路系統,其中該光學系統包含一光電晶體及一發光二極體(LED)。
- 如請求項18之積體電路系統,其中該光學系統支持在該第一半導體晶粒與該第二半導體晶粒之間的雙向通訊。
- 一種積體電路系統,其包含:一第一作用層,其製造於一半導體晶粒之一前側上;一第二預先製造層,其與該半導體晶粒垂直集成且具有體現於其中之電組件,其中該等電組件包括至少一離散被動組件;至少一電路徑,其耦接該第一作用層與該第二預先製造層;及一接收器,其用以自一外部源接收一信號,其中該信號啟動該積體電路系統的至少一部分。
- 一種積體電路系統,其包含:一第一作用層,其製造於一半導體晶粒之一前側上;一第二預先製造層,其與該半導體晶粒垂直集成且具有體現於其中之電組件,其中該等電組件包括至少一離 散被動組件;至少一電路徑,其耦接該第一作用層與該第二預先製造層;及一傳輸器,其用以將一信號傳輸至一外部源,其中該信號係基於對該積體電路系統所執行之一量測讀取而傳輸。
- 一種電子裝置,其包含:一電路板;及一垂直積體電路,其安置於該電路板上,其包含:一第一作用層,其製造於一半導體晶粒之一前側上;一第二預先製造層,其在該半導體晶粒之一背側上且具有體現於其中之電組件及連接該等電組件之一或多個鏈路,其中該等電組件包括至少一離散被動組件;及至少一電路徑,其耦接該第一作用層與該第二預先製造層;其中該一或多個鏈路係可修改以在該第一作用層與該第二預先製造層之組裝後調諧該垂直積體電路之效能。
- 如請求項28之電子裝置,其進一步包含一處理器及耦接至該電路板之一介面。
- 一種積體電路系統,其包含:一作用層,其包含製造於一半導體晶粒上之一作用電 路;一組件層,其與該半導體晶粒垂直集成,該組件層包括被動組件及在該作用層與該組件層之組裝後可修改之可修改元件;及一電路徑,其耦接該作用層之該作用電路與該組件層之該等被動組件之至少一者。
- 如請求項30之系統,其中該等可修改元件包含鏈路,其經組態以電連接該組件層之該等被動組件。
- 如請求項30之系統,其中該作用層與該組件層係配置於一堆疊中,且其中該等可修改元件經組態以在該作用層與該組件層經組裝於該堆疊中後調諧該積體電路系統之效能。
- 如請求項30之系統,其中該等可修改元件包含一熔絲。
- 如請求項30之系統,其中該組件層係一預先製造層,且其中該組件層包含一矽基板、一陶瓷基板及一玻璃基板之一者。
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US12/975,847 US8569861B2 (en) | 2010-12-22 | 2010-12-22 | Vertically integrated systems |
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TW104113577A TWI506750B (zh) | 2010-12-22 | 2011-12-15 | 垂直集成系統 |
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EP (4) | EP2469595B1 (zh) |
JP (5) | JP2012164970A (zh) |
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