TW202042329A - 具有增強性能之射頻元件及其形成方法 - Google Patents

具有增強性能之射頻元件及其形成方法 Download PDF

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TW202042329A
TW202042329A TW109102895A TW109102895A TW202042329A TW 202042329 A TW202042329 A TW 202042329A TW 109102895 A TW109102895 A TW 109102895A TW 109102895 A TW109102895 A TW 109102895A TW 202042329 A TW202042329 A TW 202042329A
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layer
top surface
transfer
end process
active layer
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TW109102895A
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朱力奧 Ｃ 科斯塔
麥可 卡羅爾
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美商科沃美國公司
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Publication of TW202042329A publication Critical patent/TW202042329A/zh

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Abstract

本發明係關於一種射頻元件，其包括一轉移元件晶粒及一位於該轉移元件晶粒下方之多層式重佈結構。該轉移元件晶粒包括一元件區域，該元件區域具有一後段製程(BEOL)部及一位於該BEOL部上方之前段製程(FEOL)部；以及一轉移基板。該FEOL部包括絕緣段及受該等絕緣段包圍之一主動層。將該元件區域之一頂表面平面化。該轉移基板位於該元件區域之該頂表面上方。在此，矽晶並不存於該轉移基板內或該轉移基板與該主動層之間。該多層式重佈結構包括若干凸塊結構，該等凸塊結構位於該多層式重佈結構之一底部並電性耦接至該轉移元件晶粒之該FEOL部。

Description

具有增強性能之射頻元件及其形成方法
本發明係關於一種射頻(RF)元件及其製作程序，更詳而言之，本發明係關於一種具有增強熱性能及電性能之RF元件，及一種用以提供具有增強性能之RF元件之晶圓級製作及封裝程序。相關申請案
本申請案主張2019年6月26日所提出之臨時專利申請第62/866,926號及2019年1月23日所提出之臨時專利申請第62/795,804號之優先權，該等申請案之整體經參照合併於此。
本申請係關於2019年11月8日同時提出申請且名為「具有增強性能之射頻元件及其形成方法」之美國專利申請第16/678,551號案、名為「具有增強性能之射頻元件及其形成方法」之美國專利申請第16/678,573號案、名為「具有增強性能之射頻元件及其形成方法」之美國專利申請第16/678,586號案及名為「具有增強性能之射頻元件及其形成方法」之美國專利申請第16/678,619號案，該等申請案之整體經參照合併於此。
蜂巢式元件及無線元件之廣泛使用帶動射頻(RF)技術之快速發展。RF元件所用之基板是RF技術能否達成高階性能之重要因素。於習用矽基板上製作RF元件具有多種優點，包括矽材料成本低、適合於大規模晶圓製造、現有完善半導體設計工具及現有完善半導體製造技法等多重優點。儘管利用習用矽基板製造RF元件具有上述優點，業界鹹知習用矽基板對於RF元件而言具有兩項不利特性，即諧波失真及低電阻率。諧波失真使建立於矽基板上之RF元件難以達成高階直線性。
並且，高速高性能電晶體係以更高密度整合於RF元件中。因此，由於RF元件中所整合之電晶體數量大，通過電晶體之功率量大且/或電晶體之操作速度快等因素，RF元件所產生之熱大幅增加。據此，宜將RF元件封裝為利於散熱之配置。
晶圓級扇出型(WLFO)技術及嵌入晶圓級球格陣列(eWLB)技術目前於可攜式RF應用領域中備受矚目。WLFO及eWLB技術可提供高密度輸入/輸出(I/O)埠而不增加封裝體之體積。因此可於單一晶圓中密集封裝入大量RF元件。
為增強RF元件之操作速度及性能，解決RF元件增加之熱產生並減少RF元件之諧波失真，同時發揮WLFO/eWLB技術之優點，因此本發明之目的在於提供一種用於具有增強性能之RF元件的改良之晶圓級製作及封裝程序。再者，提升RF元件之性能但不增加元件尺寸亦為所冀。
本發明係關於一種具有增強性能之射頻(RF)元件及其製作程序。本發明之RF元件包括一轉移元件晶粒及一多層式重佈結構。轉移元件晶粒包括一元件區域，元件區域具有一前段製程(FEOL)部及一後段製程(BEOL)部；以及一轉移基板。在此，FEOL部位於BEOL部上方且具有絕緣段及一主動層，絕緣段包圍主動層，且主動層並不垂直延伸超過絕緣段。元件區域具有一平面化頂表面。轉移基板位於元件區域之頂表面上方。轉移基板內或轉移基板與元件區域內之主動層之間並不存有未含鍺、氮或氧之矽晶。多層式重佈結構形成於轉移元件晶粒之BEOL部下方，且包括若干凸塊結構。凸塊結構位於多層式重佈結構之一底表面上並電性耦接至轉移元件晶粒之FEOL部。
於RF元件之一種實施例中，轉移基板具有一大於10 W/m·K之熱導率及一大於1E5 Ohm-cm之電阻率。
於RF元件之一種實施例中，轉移基板之材質係藍寶石、熱導式石英、氮化鋁、氮化硼及氧化鈹中之一者。
於RF元件之一種實施例中，轉移基板之厚度係介於10微米與1000微米之間。
於RF元件之一種實施例中，主動層係以一應變矽磊晶層形成，其中一矽晶格常數在一300 K溫度下大於5.461。
於RF元件之一種實施例中，BEOL部包括連接層，FEOL部進一步包括一接觸層，且多層式重佈結構進一步包括重佈互連。在此，主動層及絕緣段位於接觸層上方，且BEOL部位於接觸層下方。經由多層式重佈結構內之重佈互連及BEOL部內之連接層，將凸塊結構電性耦接至轉移元件晶粒之FEOL部。
於RF元件之一種實施例中，元件區域進一步包括一位於主動層上方且受絕緣段包圍之鈍化層。在此，鈍化層係以二氧化矽形成。各絕緣段之頂表面與鈍化層之頂表面為共平面，且形成元件區域之頂表面。
於RF元件之一種實施例中，各絕緣段之頂表面與主動層之頂表面為共平面，且形成元件區域之頂表面。
於RF元件之一種實施例中，轉移元件晶粒進一步包括一阻障層，其材質係氮化矽，耦接於元件區域之頂表面與轉移基板之間。
於RF元件之一種實施例中，FEOL部係配置為提供一開關場效電晶體(FET)、一二極體、一電容器、一電阻器或一電感器中之至少一者。
依據另一實施例，一種替代RF元件包括一轉移元件晶粒及一多層式重佈結構。轉移元件晶粒包括一元件區域，元件區域具有一FEOL部及一BEOL部；以及一轉移基板。在此，FEOL部位於BEOL部上方且包括絕緣段及一主動層，絕緣段包圍主動層，且主動層並不垂直延伸超過絕緣段。元件區域具有一平面化頂表面。轉移基板位於元件區域之頂表面上方。轉移基板內或轉移基板與元件區域內之主動層之間並不存有未含鍺、氮或氧之矽晶。多層式重佈結構形成於轉移元件晶粒之BEOL部下方，並水平延伸超過轉移元件晶粒。多層式重佈結構包括若干凸塊結構，凸塊結構位於多層式重佈結構之一底表面上並電性耦接至轉移元件晶粒之FEOL部。替代RF元件進一步包括一位於多層式重佈結構上方之模塑化合物以封裝轉移元件晶粒。
於替代RF元件之一種實施例中，轉移基板具有一大於10 W/m·K之熱導率及一大於1E5 Ohm-cm之電阻率。
於替代RF元件之一種實施例中，轉移基板之材質係藍寶石、熱導式石英、氮化鋁、氮化硼及氧化鈹中之一者。
於替代RF元件之一種實施例中，轉移基板之厚度係介於10微米與1000微米之間。
於替代RF元件之一種實施例中，主動層係以一應變矽磊晶層形成，其中一矽晶格常數在一300 K溫度下大於5.461。
於替代RF元件之一種實施例中，BEOL部包括連接層，FEOL部進一步包括一接觸層，且多層式重佈結構進一步包括重佈互連。在此，主動層及絕緣段位於接觸層上方，且BEOL部位於接觸層下方。經由多層式重佈結構內之重佈互連及BEOL部內之連接層，將凸塊結構電性耦接至轉移元件晶粒之FEOL部。
於替代RF元件之一種實施例中，元件區域進一步包括一位於主動層上方且受絕緣段包圍之鈍化層。在此，鈍化層係以二氧化矽形成。各絕緣段之頂表面與鈍化層之頂表面為共平面，且形成元件區域之頂表面。
於替代RF元件之一種實施例中，各絕緣段之頂表面與主動層之頂表面為共平面，且形成元件區域之頂表面。
於替代RF元件之一種實施例中，轉移元件晶粒進一步包括一阻障層，其材質係氮化矽，耦接於元件區域之頂表面與轉移基板之間。
於替代RF元件之一種實施例中，FEOL部係配置為提供一開關FET、一二極體、一電容器、一電阻器或一電感器中之至少一者。
依據一例示程序，首先提供一前導晶圓，其包括若干完整元件區域、若干單個介面層及一矽處理基板。各完整元件區域包括一BEOL部及一位於BEOL部上方之完整FEOL部。完整FEOL部具有一主動層及完整絕緣段，完整絕緣段垂直延伸超過主動層並包圍主動層。在此，各單個介面層位於一個主動層上方且受一對應完整元件區域之完整絕緣段包圍。各單個介面層係以SiGe形成。矽處理基板位於各完整絕緣段及各單個介面層上方。接著，完全移除矽處理基板。而後將完整絕緣段減薄以提供具有平面化頂表面之經減薄後之晶圓。經減薄後之晶圓包括若干元件區域，及各元件區域之頂表面之結合形成經減薄後之晶圓之平面化頂表面。各元件區域包括BEOL部及一位於BEOL部上方之FEOL部。FEOL部具有主動層及包圍主動層之經減薄後之絕緣段。將轉移基板附接至經減薄後之晶圓之頂表面，以提供一包括若干轉移元件晶粒之轉移元件晶圓。在此，轉移基板內或各元件區域內之主動層與轉移基板之間並不存有未含鍺、氮或氧之矽晶。各轉移元件晶粒包括一對應元件區域及位於對應元件區域上方之部分轉移基板。
於例示程序之一種實施例中，轉移基板具有一大於10 W/m·K之熱導率及一大於1E5 Ohm-cm之電阻率。
於例示程序之一種實施例中，轉移基板之材質係藍寶石、熱導式石英、氮化鋁、氮化硼及氧化鈹中之一者。
於例示程序之一種實施例中，轉移基板之厚度係介於10微米與1000微米之間。
依據另一實施例，例示程序進一步包括在移除矽處理基板之前經由一接合層將前導晶圓接合至一暫時載體，以及在附接轉移基板之後剝離暫時載體並清潔轉移元件晶圓上之接合層。
依據另一實施例，例示程序進一步包括在轉移元件晶圓下方形成一多層式重佈結構。在此，多層式重佈結構包括若干位於多層式重佈結構之一底表面上之凸塊結構及位於多層式重佈結構中之重佈互連。經由多層式重佈結構內之重佈互連及對應轉移元件晶粒之BEOL部內之連接層，將各凸塊結構電性耦接至一對應轉移元件晶粒之一個主動層。
依據另一實施例，例示程序進一步包括將轉移元件晶圓切割成若干單個轉移元件晶粒。繼而將模塑化合物施用於各單個轉移元件晶粒周圍及上方，以提供一模塑元件晶圓。在此，模塑化合物封裝各單個轉移元件晶粒之一頂表面及側表面，而各單個轉移元件晶粒之一底表面則暴露在外。模塑元件晶圓之一底表面為各單個轉移元件晶粒之一底表面與模塑化合物之一底表面之結合。繼而於模塑元件晶圓下方形成一多層式重佈結構。多層式重佈結構包括若干位於多層式重佈結構之一底表面上之凸塊結構及位於多層式重佈結構中之重佈互連。經由多層式重佈結構內之重佈互連及對應單個轉移元件晶粒之BEOL部內之連接層，將各凸塊結構電性耦接至一對應單個轉移元件晶粒之一個主動層。
依據另一實施例，例示程序進一步包括在移除矽處理基板之後且減薄完整絕緣段之前移除各單個介面層。以此方式，在減薄步驟之後，各元件區域之平面化頂表面藉由一對應主動層之一頂表面與對應經減薄後之絕緣段之頂表面而形成。
依據另一實施例，例示程序進一步包括在移除矽處理基板之後且減薄完整絕緣段之前移除各單個介面層及將鈍化層施用於一對應主動層上方。以此方式，在減薄步驟之後，各元件區域之平面化頂表面藉由一對應鈍化層之頂表面與對應經減薄後之絕緣段之頂表面而形成。
於例示程序之一種實施例中，鈍化層藉由一電漿增強沉積程序、一陽極氧化程序及一臭氧基氧化程序中之一者來施用。
依據另一實施例，例示程序進一步包括在將轉移基板附接至經減薄後之晶圓之前將阻障層施用於經減薄後之晶圓之頂表面。在此，阻障層係以氮化矽形成。
於例示程序之一種實施例中，提供前導晶圓始自提供一起始晶圓，起始晶圓包括一共同矽磊晶層、一位於共同矽磊晶層上方之共同介面層以及一位於共同介面層上方之矽處理基板。隨後執行互補式金屬氧化物半導體(CMOS)程序以提供前導晶圓。在此，完整絕緣段延伸通過共同矽磊晶層及共同介面層，並延伸進入矽處理基板，使得共同介面層分隔成單個介面層，且共同矽磊晶層分隔成若干單個矽磊晶層。各主動層係以一對應單個矽磊晶層形成。
於例示程序之一種實施例中，藉由一機械研磨程序及之後的蝕刻程序來移除矽處理基板。
於例示程序之一種實施例中，矽處理基板藉由一具有一蝕刻劑化學物之蝕刻程序移除，蝕刻劑化學物係氫氧化四甲銨(TMAH)、氫氧化鉀(KOH)、氫氧化鈉(NaOH)、乙醯膽鹼(ACH)及二氟化氙(XeF2)中之至少一者。
於例示程序之一種實施例中，矽處理基板藉由一具有一氯基氣體化學物之活性離子蝕刻系統而移除。
於例示程序之一種實施例中，轉移基板藉由陽極接合、電漿接合及聚合物黏合中之一者而附接至經減薄後之晶圓之頂表面。
精於此技藝人士經參照附圖閱讀以下較佳實施例之詳細說明後，應可理解本發明之範疇並領會其各種態樣。
以下提供之實施例陳述供熟悉此技藝人士實施本發明所需之資訊，並說明實踐實施例之最佳方式。經參照附圖閱讀以下說明後，熟悉此技藝人士將可瞭解本發明之概念，且將領會此等概念未盡於本文之各種應用。應知此等概念及應用俱屬本發明及所附申請專利範圍之範疇。
儘管在此可能以第一、第二等術語描述各種元件，應知此等元件並不受限於此等術語。此等術語僅用於區分不同元件。例如，第一元件可改稱為第二元件，且同理，第二元件可改稱為第一元件，而不脫離本發明之範疇。如在此所用，「及/或」包括一或多種所列相關項目之任何及全部組合。
應知當於此稱一元件，例如一層體、區域或基板，為位於另一元件上或延伸至另一元件上，其可為直接在另一元件上或直接延伸至另一元件上，或其間亦可能存有其他中間元件。反之，當稱一元件為「直接」位於另一元件上或延伸至另一元件上，表示兩者之間並無其他中間元件存在。同理，應知當稱一元件，例如一層體、區域或基板，為在另一元件上或延伸於另一元件上，其可為直接在另一元件上或直接延伸於另一元件上方或其間亦可能存有其他中間元件。反之，當稱一元件為「直接」位於另一元件上或延伸於另一元件上方，表示兩者之間並無其他中間元件存在。亦應知，當稱一元件「連接」或「耦接」於另一元件，其可直接連接或耦接於另一元件，或其間亦可能存有其他中間元件。反之，當稱一元件「直接連接」或「直接耦接」至另一元件，表示兩者之間並無其他中間元件存在。
在此所用相對性術語，例如「在下」或「在上」或「上方」或「下方」或「水平」或「垂直」或「在...上方」或「在...下方」係為描述圖中一元件、層體或區域與另一元件、層體或區域之關係。應知此等術語及上文論述者意欲包含與圖中所示不同之元件方向。
在此所用術語僅為描述具體實施，且並非意圖限制本發明。除非上下文另有明確指定，否則在此所用單數形之「一」及「該」亦應包括複數形。亦應知，在此當以「包含」及/或「包括」指定所稱特徵、數值、步驟、操作、元件及/或組件之存在時，並不排除其他一或多種特徵、數值、步驟、操作、元件、組件及/或群組之存在或添加。
除非另有定義，否則在此使用之所有術語(包括技術及科學術語)均具有如同為熟悉本發明所屬技藝人士週知之意義。且應知在此所用術語應採與本說明書上下文及相關技藝中意義相符之解釋，且除非文中如此要求，否則不應採理想化或過度制式之解讀。
有鑑於習用射頻絕緣層上覆矽(RFSOI)晶圓在未來數年可預見之短缺，業界正以利用矽晶圓、富陷阱層形成及智切法SOI晶圓程序等方式研發替代技術，試圖免除高電阻之需求。一種替代技術是在矽基板與矽磊晶層之間使用矽鍺(SiGe)介面層取代埋入氧化層(BOX)。然而，此項技術與RFSOI技術同樣難以倖免於來自矽基板之有害失真效應。本發明係關於一種具有增強性能之射頻(RF)元件及一種製作其之晶圓級製作及封裝程序，且使用SiGe介面層而無來自矽基板之有害失真效應。
圖1示出依據本發明之一種實施例之具有增強性能之例示RF元件10。為了說明目的，例示RF元件10包括一轉移元件晶粒12，轉移元件晶粒12具有一元件區域14及一轉移基板16；以及一形成於轉移元件晶粒12之元件區域14下方之多層式重佈結構18。
詳言之，元件區域14包括一前段製程(FEOL)部20及一位於FEOL部20下方之後段製程(BEOL)部22。於一種實施例中，FEOL部20係配置為提供一開關場效電晶體(FET)，且包括一主動層24及一接觸層26。主動層24係以一鬆弛矽磊晶層或一應變矽磊晶層形成，且包括一源極28、一汲極30及一位於源極28與汲極30之間之通道32。在此，鬆弛矽磊晶層係指矽磊晶層，其中矽晶格常數在一300 K溫度下為5.431。應變矽磊晶層係指一矽磊晶層，其中矽晶格常數大於鬆弛矽磊晶層中之晶格常數，例如在一300 K溫度下大於5.461，或大於5.482，或大於5.493，或大於5.515。以此方式，應變矽磊晶層中電子相比於鬆弛矽磊晶層中電子可能具有增強之遷移率。因此，相比於以一鬆弛矽磊晶層形成之FET，以應變矽磊晶層形成之FET可能具有更快之開關速度。
接觸層26形成於主動層24下方，且包括一閘極結構34、一源極接點36、一汲極接點38及一閘極接點40。閘極結構34可係以氧化矽形成，並水平延伸於通道32下方(即自源極28下方至汲極30下方)。源極接點36連接至並位於源極28下方，汲極接點38連接至並位於汲極30下方，且閘極接點40連接至並位於閘極結構34下方。源極接點36、汲極接點38、閘極結構34及閘極接點40周圍可形成有絕緣材料42以將源極28、汲極30與閘極結構34電性分隔。於不同應用中，FEOL部20可具有不同FET配置或提供不同元件組件，例如二極體、電容器、電阻器及/或電感器。
此外，FEOL部20亦包括絕緣段44，其位於接觸層26之絕緣材料42上方並包圍主動層24。絕緣段44係配置為將RF元件10，特別是主動層24，與共同晶圓中形成之其他元件電性分隔(圖未示)。絕緣段44可係以二氧化矽形成，其可耐受例如氫氧化四甲銨(TMAH)、二氟化氙(XeF2 )、氫氧化鉀(KOH)、氫氧化鈉(NaOH)或乙醯膽鹼(ACH)等蝕刻劑化學物，且可耐受一乾式蝕刻系統，例如具有氯基氣體化學物之活性離子蝕刻(RIE)系統。
於一些應用中，元件區域14進一步包括一鈍化層48，其材質係二氧化矽，用以鈍化主動層24。鈍化層48沉積於主動層24之頂表面上方並受絕緣段44所包圍。於一種實施例中，鈍化層48之頂表面與絕緣段44之頂表面為共平面。鈍化層48係配置為終止主動層24之表面接合，其可造成不期望之洩漏。
於一些應用中，元件區域14進一步包括一介面層及/或一緩衝結構(圖未示)，其材質為SiGe，形成於主動層24之頂表面上方並受絕緣段44所包圍(於下文說明且在此未示)。若設有鈍化層48、緩衝結構及介面層，則介面層及緩衝結構垂直位於主動層24與鈍化層48之間。在此，鈍化層48之頂表面與絕緣段44之頂表面為共平面。若省略鈍化層48，但設有介面層及/或緩衝結構，則介面層之頂表面(或緩衝結構之頂表面)與絕緣段44之頂表面為共平面(圖未示)。若省略鈍化層48、緩衝結構及介面層，則主動層24之頂表面與絕緣段44之頂表面為共平面(圖未示)。應知，不論鈍化層48、緩衝結構及/或介面層存在與否，始終將元件區域14之頂表面(絕緣段44之頂表面與鈍化層48之頂表面之結合，絕緣段44之頂表面與介面層之頂表面之結合，絕緣段44之頂表面與緩衝結構之頂表面之結合，或絕緣段44之頂表面與主動層24之頂表面之結合)平面化。
轉移基板16位於元件區域14之頂表面上方。元件區域14產生之熱可向上到達位於主動層24上方之轉移基板16之底部，繼而將向下通過元件區域14並由多層式重佈結構18將熱散出。因此，非常需要轉移基板16具有高導熱率，尤其對於緊挨著主動層24之部分。在此，轉移基板16之高熱導率係介於2 W/m·K與500 W/m·K之間(期望高於10 W/m·K)，且高電阻率係介於1E5 Ohm-cm與1E14 Ohm-cm之間。用以形成轉移基板16之適當基板材料可包括藍寶石、熱導式石英及陶瓷材料，例如氮化鋁、氮化硼等。轉移基板16亦係以氧化鈹形成。轉移基板16之厚度取決於RF元件10所需熱性能、元件佈局、與多層式重佈結構18相隔距離以及封裝體及組體之詳情。轉移基板16之厚度可介於10微米與1000微米之間。
於一些應用中，轉移元件晶粒12可進一步包括一耦接於元件區域14之頂表面與轉移基板16之間之阻障層(圖未示)。此阻障層可以氮化矽形成，其厚度係介於100 Å與5000 Å之間。阻障層係配置為提供一阻擋濕氣及雜質之卓越屏障作用，濕氣及雜質可擴散進入主動層24之通道32並破壞元件之可靠性。此外，阻障層係配置為增強元件區域14與轉移基板16之間之黏附性。應知，不論阻障層、鈍化層48或介面層存在與否，轉移基板16內或轉移基板16與主動層24之頂表面之間並不存有未含鍺、氮或氧之矽晶。阻障層、鈍化層48及介面層之材質皆為矽复合物。
BEOL部22位於FEOL部20下方且包括多個形成於介電質層52中之連接層50。一些連接層50(用於內部連接)受介電質層52封裝(圖未示)，而一些連接層50之底部則未受介電質層52覆蓋。特定連接層50電性連接至FEOL部20。為說明目的，其中一連接層50連接至源極接點36，且另一連接層50連接至汲極接點38。
形成於轉移元件晶粒12之BEOL部22下方之多層式重佈結構18包括若干重佈互連54、一介電質圖案56及若干凸塊結構58。在此，各重佈互連54連接至BEOL部22中之對應連接層50並延伸在BEOL部22之底表面上方。重佈互連54與連接層50間之連結係不經焊接而達成。介電質圖案56形成於各重佈互連54之周圍及下方。一些重佈互連54(將轉移元件晶粒12連接至相同晶圓形成之其他元件組件)可由介電質圖案56封裝(圖未示)，而一些重佈互連54具有經由介電質圖案56暴露之底部。各凸塊結構58形成於多層式重佈結構18之底表面並經由介電質圖案56而電性耦接至對應重佈互連54。以此方式，重佈互連54係配置為將凸塊結構58連接至BEOL部22中與FEOL部20電性連接之特定連接層50。因此，凸塊結構58經由對應重佈互連54及對應連接層50而電性連接至FEOL部20。此外，凸塊結構58彼此分隔並從介電質圖案56突出。
於一些應用中，可設有通過介電質圖案56電性耦接至重佈互連54之外加重佈互連(圖未示)，以及形成於介電質圖案56下方之外加介電質圖案(圖未示)，使得一些外加重佈互連之底部可暴露在外。因此，各凸塊結構58通過外加介電質圖案而耦接至一對應外加重佈互連(圖未示)。不論重佈互連及/或介電質圖案之層數，多層式重佈結構18可不含玻璃纖維或不含玻璃。在此，玻璃纖維意指經撚搓成較大線股之玻璃線縷。而後可將此等玻璃線縷編成織品。重佈互連54可係以銅或其他適合之金屬形成。介電質圖案56可係以苯並環丁烯(BCB)、聚醯亞胺或其他介電質材料形成。凸塊結構58可為焊球或銅柱。多層式重佈結構18之厚度係介於2微米與300微米之間。
圖2示出一替代RF元件10A，其進一步包括一對照圖1所示RF元件10之模塑化合物60。在此，多層式重佈結構18可水平延伸超過轉移元件晶粒12，且模塑化合物60位於多層式重佈結構18上方以封裝轉移元件晶粒12。於此實施例中，多層式重佈結構18之重佈互連54可水平延伸超過轉移元件晶粒12，且多層式重佈結構18之凸塊結構58可不受限於轉移元件晶粒12之外周內。模塑化合物60可為有機環氧樹脂系統或類似物。
圖3A-圖15提供一種例示晶圓級製作及封裝程序，其說明用於製造圖1所示例示RF元件10之步驟。儘管在此依序說明例示步驟，但各步驟並非必須按照固定順序。一些步驟可透過與所示者不同之順序進行。再者，本說明範疇內之程序可較圖3A-圖15所示者包括更少或更多步驟。
首先提供如圖3A及圖3B所示之起始晶圓62。起始晶圓62包括一共同矽磊晶層64、一位於共同矽磊晶層64上方之共同介面層66及一位於共同介面層66上方之矽處理基板68。在此，共同矽磊晶層64係以元件級矽材料形成，且具有形成電子元件所需之矽磊晶特性。矽處理基板68可由傳統低成本、低電阻及高介電常數之矽構成，且在一300 K溫度下可具有約5.431之晶格常數。共同介面層66係以SiGe形成，且將共同矽磊晶層64與矽處理基板68分隔開來。
於例如300 K之一固定溫度下，鬆弛矽之晶格常數為5.431 Å，而鬆弛Si1-x Gex 之晶格常數取決於鍺濃度，例如(5.431+0.2x+0.027x2 ) Å。鬆弛SiGe之晶格常數大於鬆弛矽之晶格常數。若共同介面層66直接生長於矽處理基板68下方，則共同介面層66中之晶格常數將受矽處理基板68應變(減小)。若共同矽磊晶層64直接生長於共同介面層66下方，則共同矽磊晶層64中之晶格常數可保持為原始鬆弛形式(與矽基板中之晶格常數大致相同)。因此，共同矽磊晶層64不可增強電子遷移率。
於一種實施例中，共同緩衝結構70可形成於矽處理基板68與共同介面層66之間，如圖3A所示。共同緩衝結構70允許從矽處理基板68至共同介面層66之晶格常數轉換。共同緩衝結構70可包括多個層且可係以具有一垂直分級鍺濃度之SiGe形成。共同緩衝結構70中之鍺濃度可從頂側之0%(緊挨著矽處理基板68)增長至底側之X%(緊挨著共同介面層66)。X%可取決於共同介面層66中之鍺濃度，例如15%，或25%，或30%，或40%。共同介面層66在此生長於共同緩衝結構70下方，且可將其晶格常數保持為鬆弛形式，且可不受應變(減小)以匹配矽處理基板68之晶格常數。鍺濃度可於整個共同介面層66中為均勻的且大於15%、25%、30%或40%，使得共同介面層66中鬆弛SiGe之晶格常數在300 K溫度下大於5.461，或大於5.482，或大於5.493，或大於5.515。
在此，共同矽磊晶層64直接生長於鬆弛共同介面層66下方，使得共同矽磊晶層64之晶格常數與鬆弛共同介面層66中之晶格常數匹配(同樣拉伸)。因此，共同應變矽磊晶層64中之晶格常數在300 K溫度下可大於5.461，或大於5.482，或大於5.493，或大於5.515，且因此大於鬆弛矽磊晶層中之晶格常數(例如，在300 K溫度下為5.431)。共同應變矽磊晶層64之電子遷移率可顯著高於鬆弛矽磊晶層之電子遷移率。共同矽磊晶層64之厚度可介於700奈米與2000奈米之間，共同介面層66之厚度可介於200 Å與600 Å之間，共同緩衝結構70之厚度可介於100奈米與1000奈米之間，且矽處理基板68之厚度可介於200微米與700微米之間。
於另一實施例中，共同介面層66可直接形成於矽處理基板68下方，及共同緩衝結構70可形成於共同介面層66與共同矽磊晶層64之間，如圖3B所示。在此，共同介面層66之晶格常數可受矽處理基板68應變(減小)。共同緩衝結構70可仍然係以具有一垂直分級鍺濃度之SiGe形成。共同緩衝結構70中之鍺濃度可從頂側之0%(緊挨著共同介面層66)增長至底側之X%(緊挨著共同矽磊晶層64)。X%可為15%，或25%，或30%，或40%。共同緩衝結構70之底側處晶格常數大於共同緩衝結構70之頂側處晶格常數。共同矽磊晶層64在此生長於共同緩衝結構70下方，且其晶格常數具有與共同緩衝結構70之底側處晶格常數匹配(共同拉伸)。因此，共同應變矽磊晶層64之晶格常數大於鬆弛矽磊晶層之晶格常數(例如，在300 K溫度下為5.431)。
於一些應用中，省略共同緩衝結構70(圖未示)。共同介面層66直接生長於矽處理基板68下方，且共同矽磊晶層64直接生長於共同介面層66下方。以此方式，將共同介面層66中之晶格常數應變(減小)以匹配矽處理基板68中之晶格常數，且共同矽磊晶層64中之晶格常數保持為原始鬆弛形式(與矽基板中晶格常數大致相同)。
接著，在起始晶圓62上執行互補式金屬氧化物半導體(CMOS)程序(圖3A)，以提供一具有若干完整元件區域14'之前導晶圓72，如圖4所示。各完整元件區域14'包括一完整FEOL部20'，其具有主動層24、接觸層26及完整絕緣段44'；及位於完整FEOL部20'下方之BEOL部22。為說明目的，完整FEOL部20'係配置為提供一開關FET。於不同應用中，完整FEOL部20'可具有不同FET配置或提供不同元件組件，例如二極體、電容器、電阻器及/或電感器。
於一種實施例中，各完整元件區域14'之完整絕緣段44'延伸通過共同矽磊晶層64、共同介面層66及共同緩衝結構70，並延伸進入矽處理基板68。以此方式，共同緩衝結構70分隔成若干單個緩衝結構70I，共同介面層66分隔成若干單個介面層66I，且共同矽磊晶層64分隔成若干單個矽磊晶層64I。各單個矽磊晶層64I用於在其中一個完整元件區域14'中形成一對應主動層24。完整絕緣段44'可由淺溝槽隔離(STI)形成。若主動層24係以一個具有應變(增大)晶格常數之單個矽磊晶層64I形成，則相比於以具有鬆弛晶格常數之鬆弛矽磊晶層形成之FET之開關速度(ON-電阻)，取決於主動層24之FET之開關速度(ON-電阻)較快(較低)。
主動層24之頂表面接觸對應介面層66I且位於對應緩衝結構70I下方。矽處理基板68位於各單個緩衝結構70I上方，且部分矽處理基板68可位於完整絕緣段44'上方。完整元件區域14'之BEOL部22包括至少多個連接層50及介電質層52，且形成於完整FEOL部20'之接觸層26下方。於BEOL部22之底表面處，通過介電質層52將特定連接層50之底部暴露在外。
在完成前導晶圓72之後，繼而將前導晶圓72接合至暫時載體74，如圖5所示。前導晶圓72可經由接合層76而接合至暫時載體74，從而將平面化表面提供至暫時載體74。基於成本及熱膨脹之考量，暫時載體74可為厚矽晶圓，但其材質亦可為玻璃、藍寶石或任何其他適合之載體材料。接合層76可為跨上式聚合物黏膜，例如布魯爾科技晶圓BOND系列暫時黏合材料。
隨後選擇性移除矽處理基板68以提供經蝕刻後之晶圓78，如圖6所示。選擇性移除停止在各單個緩衝結構70I或各介面層66I處。移除矽處理基板68可提供位於各主動層24上方且完整絕緣段44'中之開口79。移除矽處理基板68可藉由機械研磨程序及蝕刻程序提供，或藉由蝕刻程序本身提供。例如，可將矽處理基板68研磨至較薄厚度以減少下述蝕刻時間。繼而執行蝕刻程序以至少完全地移除剩餘矽處理基板68。由於矽處理基板68、單個緩衝結構70I及單個介面層66I具有不同鍺濃度，故他們可具有對相同蝕刻技術之不同反應(例如：相同蝕刻劑下不同蝕刻速度)。因此，蝕刻系統能夠辨識單個緩衝結構70I或單個介面層66I之存在(鍺存在)，並能夠指示何時停止蝕刻製程。通常，鍺濃度越高，矽處理基板68與單個緩衝結構70I之間(或矽處理基板68與單個介面層66I之間)之蝕刻選擇性越好。蝕刻程序可由具有蝕刻劑化學物之濕式蝕刻系統或幹式蝕刻系統來提供，蝕刻劑化學物為TMAH、KOH、NaOH、ACH及XeF2 中之至少一者，乾式蝕刻系統例如具有氯基氣體化學物之活性離子蝕刻系統。
在移除程序期間，完整絕緣段44'並未移除且保護各主動層24之側面。接合層76及暫時載體74保護各BEOL部22之底表面。在此，在移除步驟之後將各完整絕緣段44'之頂表面及各單個緩衝結構70I(或各單個介面層66I)之頂表面暴露在外。由於SiGe材料之窄帶隙特性，單個緩衝結構70I及/或單個介面層66I可具有傳導性(針對某類元件)。單個緩衝結構70I及/或單個介面層66I可在主動層24之源極28與汲極30之間造成可察知洩漏。因此，於一些應用中，例如FET開關應用，亦宜將單個緩衝結構70I及單個介面層66I移除，如圖7所示。各主動層24暴露於對應開口79之底部。單個緩衝結構70I及單個介面層66I可由與移除矽處理基板68相同之蝕刻程序移除，或可藉由例如氯基乾式蝕刻系統之另一蝕刻程序移除。在此，若各單個介面層66I足夠薄，則其在FEOL部20之源極28與汲極30之間不會造成任何可察知洩漏。在此情況下，可將單個介面層66I可保留(圖未示)。同樣地，若單個介面層66I及單個緩衝結構70I皆足夠薄，則其在FEOL部20之源極28與汲極30之間不會造成任何可察知洩漏。在此情況下，單個介面層66I及單個緩衝結構70I可保留(圖未示)。
於一些應用中，在移除矽處理基板68、單個緩衝結構70I及單個介電質層66I之後，可鈍化各主動層24以達成元件中適當低量電流洩漏。鈍化層48可形成於各完整FEOL部20'之各主動層24上方及開口79內，如圖8所示。鈍化層48可藉由一電漿增強沉積程序、一陽極氧化程序、一臭氧基氧化程序及若干其他的適當技術而以二氧化矽形成。鈍化層48係配置為終止主動層24頂表面之表面接合，避免造成不期望之洩漏。
接著，將完整絕緣段44'減薄作為絕緣段44，以提供具有一平面化頂表面之經減薄後之晶圓80，如圖9所示。經減薄後之晶圓80包括若干元件區域14，且各元件區域14之頂表面之結合形成經減薄後之晶圓80之平面化頂表面。在此，若施用鈍化層48，則各鈍化層48之頂表面與各絕緣段44之頂表面為共平面。若省略鈍化層48，而單個介面層66I(及/或單個緩衝結構70I存在)，則各絕緣段44之頂表面與各單個介面層66I之頂表面(或各單個緩衝結構70I之頂表面)為共平面(圖未示)。若省略鈍化層48、單個緩衝結構70I及單個介面層66I，則各主動層24之頂表面與各絕緣段44之頂表面為共平面(圖未示)。不論鈍化層48、單個緩衝結構70I及/或單個介面層66I存在與否，始終將各元件區域14之頂表面平面化。平面化步驟可藉由化學機械拋光(CMP)程序來達成，CMP程序利用一種適當漿料及拋光輪，或類似物。
繼而將轉移基板16接合至經減薄後之晶圓80之頂表面以提供一轉移元件晶圓82，如圖10所示。由於將經減薄後之晶圓80之頂表面平面化，轉移元件晶圓82在接合面積中不含任何孔隙或缺陷。轉移元件晶圓82包括若干轉移元件晶粒12，各轉移元件晶粒至少包括元件區域14及部分轉移基板16。轉移基板16之高熱導率係介於2 W/m·K與500 W/m·K之間，且其高電阻率係介於1E5 Ohm-cm與1E14 Ohm-cm之間。轉移基板16之材質可為藍寶石、熱導式石英、陶瓷材料(例如氮化鋁、氮化硼等)或氧化鈹。轉移基板16之厚度可介於10微米與1000微米之間。若干適當低溫接合程序可用於此步驟中，例如陽極接合、電漿接合、聚合物黏合等。於轉移基板16之接合程序中，暫時載體74為經減薄後之晶圓80提供機械強度及剛性。
於一些應用中，在接合轉移基板16之前於經減薄後之晶圓80之頂表面上方形成一阻障層(圖未示)。此阻障層係以氮化矽形成，其厚度係介於100 Å與5000 Å之間。阻障層係配置為提供一阻擋濕氣及雜質之卓越屏障作用，濕氣及雜質可擴散進入各主動層24之通道32中。此外，阻障層係配置為增強經減薄後之晶圓80與轉移基板16之間之黏附性。應知，不論阻障層、鈍化層48或單個介面層66I存在與否，轉移基板16內或轉移基板16與各主動層24之頂表面之間並不存有未含鍺、氮或氧之矽晶。阻障層、鈍化層48及單個介面層66I之材質皆為矽複合物。
繼而將暫時載體74自轉移元件晶圓82剝離，並清除轉移元件晶圓82上之接合層76，如圖11所示。可依據先前步驟所選用暫時載體74及接合層76之性質實施若干剝離程序及清潔程序。例如，可將堆疊體加熱至適當溫度，利用側刀程序以機械方式將暫時載體74剝離。若暫時載體74為透明材料，可使用紫外光輻射，其他適合之程序亦包括使用適當溶劑之化學剝離。接合層76之去除可經由濕式或乾式蝕刻程序達成，例如專有溶劑及電漿清洗。經剝離及清潔程序後，作為各轉移元件晶粒12之輸入/輸出(I/O)埠之特定連接層50之底部可經由各BEOL部22底表面之介電質層52而暴露在外。以此方式，可於此時以電性方式驗證轉移元件晶圓82中之各轉移元件晶粒12是否功能正常。
參照圖12至圖14，依據本發明之一種實施例，多層式重佈結構18形成於轉移元件晶圓82下方。儘管在此依序說明重佈步驟，但重佈步驟並非必須按照固定順序。一些步驟可透過與所示者不同之順序進行。再者，本說明範疇內之重佈步驟可較圖12-圖14所示者包括更少或更多步驟。
首先在各BEOL部22下方形成若干重佈互連54，如圖12所示。各重佈互連54電性耦接至BEOL部22中對應連接層50暴露在外之底部，並可延伸於BEOL部22之底表面上方。重佈互連54與連接層50間之連結係不經焊接而達成。隨後介電質圖案56形成於各BEOL部22下方，以部分封裝各重佈互連54，如圖13所示。以此方式，各重佈互連54之底部經由介電質圖案56而暴露在外。於不同應用中，可包含通過介電質圖案56而電性耦接至重佈互連54之外加重佈互連(圖未示)，以及形成於介電質圖案56下方之外加介電質圖案(圖未示)，使得各外加重佈互連之底部暴露在外。
接著，形成若干凸塊結構58以完成多層式重佈結構18並提供一晶圓級扇出型(WLFO)封裝體84，如圖14所示。各凸塊結構58形成於多層式重佈結構18之底部並電性耦接至對應重佈互連54通過介電質圖案56暴露在外之底部。因此，重佈互連54係配置為將凸塊結構58連接至BEOL部22中與FEOL部20電性連接之特定連接層50。以此方式，凸塊結構58經由對應重佈互連54及對應連接層50而電性連接至FEOL部20。此外，凸塊結構58彼此分離且從介電質圖案56垂直地突出。
多層式重佈結構18可不含玻璃纖維或不含玻璃。在此，玻璃纖維意指經撚搓成較大線股之玻璃線縷。而後可將此等玻璃線縷編成織品。重佈互連54可係以銅或其他適合之金屬形成，介電質圖案56可係以BCB、聚醯亞胺或其他介電質材料形成，且凸塊結構58可為焊球或銅柱。多層式重佈結構18之厚度係介於2微米與300微米之間。圖15示出將WLFO封裝體84切割成單個射頻元件10之最終步驟。所述切割步驟可藉由在特定絕緣段44實施針測及切割程序而達成。
於另一實施例中，圖16-圖21提供一種用於製造圖2所示替代RF元件10A之步驟之替代程序。儘管在此依序說明例示步驟，但各步驟並非必須按照固定順序。一些步驟可透過與所示者不同之順序進行。再者，本說明範疇內之程序可較圖16-圖21所示者包括更少或更多步驟。
經以剝離及清潔程序產生圖11所示之潔淨轉移元件晶圓82之後，執行切割步驟將轉移元件晶圓82切割成單個轉移元件晶粒12，如圖16所示。所述切割步驟可藉由在特定絕緣段44實施針測及切割程序而達成。在此，各轉移元件晶粒12可具有相同高度，且至少包括具有FEOL部20與BEOL部22之元件區域14，並包括轉移基板16。
接著，將模塑化合物60施用於轉移元件晶粒12之周圍及上方以提供一模塑元件晶圓86，如圖17所示。模塑化合物60封裝各轉移元件晶粒12之頂表面及側表面，但使各轉移元件晶粒12之底表面，即BEOL部22之底表面，暴露在外。模塑元件晶圓86之底表面為各轉移元件晶粒12之底表面與模塑化合物60之底表面之結合。在此，特定連接層50之底部保持暴露於各轉移元件晶粒12之底表面。模塑化合物60可藉由各種程序施用，例如片狀模製、包覆模製、壓縮模製、轉移模製、圍堰填充封裝或網版印刷封裝。不同於轉移基板16，模塑化合物60並不具有熱導率或電阻率要求。模塑化合物60可為有機環氧樹脂系統或類似物。之後使用固化程序(圖未示)使模塑化合物60硬化。固化溫度介於100ºC與320ºC之間，依據所用之模塑化合物60為何種材料而定。可執行研磨程序(圖未示)以提供模塑化合物60之平面化頂表面。
參照圖18至圖20，依據本發明之一種實施例，形成多層式重佈結構18。儘管在此依序說明重佈步驟，但重佈步驟並非必須按照固定順序。一些步驟可透過與所示者不同之順序進行。再者，本說明範疇內之重佈步驟可較圖18-圖20所示者包括更少或更多步驟。
首先於模塑元件晶圓86下方形成若干重佈互連54，如圖18所示。各重佈互連54電性耦接至BEOL部22內之對應連接層50，並可水平延伸超過對應轉移元件晶粒12並延伸於模塑化合物60下方。重佈互連54與連接層50間之連結係不經焊接而達成。而後介電質圖案56形成於模塑元件晶圓86下方，以部分封裝各重佈互連54，如圖19所示。以此方式，各重佈互連54之底部通過介電質圖案56而暴露在外。於不同應用中，可包含通過介電質圖案56而電性耦接至重佈互連54之外加重佈互連(圖未示)，以及形成於介電質圖案56下方之外加介電質圖案(圖未示)，使得各外加重佈互連之底部暴露在外。
接著，形成若干凸塊結構58以完成多層式重佈結構18並提供一替代WLFO封裝體84A，如圖20所示。各凸塊結構58形成於多層式重佈結構18之底部並電性耦接至對應重佈互連54通過介電質圖案56暴露在外之底部。因此，重佈互連54係配置為將凸塊結構58連接至BEOL部22中與FEOL部20電性連接之特定連接層50。以此方式，凸塊結構58經由對應重佈互連54及對應連接層50而電性連接至FEOL部20。在此，凸塊結構58可不受限於對應轉移元件晶粒12之外周。此外，凸塊結構58彼此分離且從介電質圖案56垂直地突出。
圖21示出將替代WLFO封裝體84A切割成單個替代RF元件10A之最終步驟。所述切割步驟可經由在模塑化合物60之水平位於相鄰轉移元件晶粒12間之部分實施針測及切割程序而達成。
熟悉此技藝人士應可領會本發明較佳實施例之改良及修改。所有此等之改良及修改均應屬於本發明概念及所附申請專利範圍之範疇。
10:射頻元件 10A:替代RF元件 12:轉移元件晶粒 14:元件區域 14':完整元件區域 16:轉移基板 18:多層式重佈結構 20:前段製程(FEOL)部 20':完整FEOL部 22:後段製程(BEOL)部 24:主動層 26:接觸層 28:源極 30:汲極 32:通道 34:閘極結構 36:源極接點 38:汲極接點 40:閘極接點 42:絕緣材料 44:絕緣段 44':完整絕緣段 48:鈍化層 50:特定連接層 52:介電質層 54:重佈互連 56:介電質圖案 58:凸塊結構 60:模塑化合物 62:起始晶圓 64:共同矽磊晶層 64I:單個矽磊晶層 66:共同介面層 66I:單個介面層 68:矽處理基板 70:共同緩衝結構 70I:單個緩衝結構 72:前導晶圓 74:暫時載體 76:接合層 78:經蝕刻後之晶圓 79:開口 80:經減薄後之晶圓 82:轉移元件晶圓 84:晶圓級扇出型(WLFO)封裝體 84A:替代WLFO封裝體 86:模塑元件晶圓
本說明書所附圖式說明本發明之數種態樣，且配合敘述內容共同闡明本發明之原理。
[圖1]示出依據本發明之一種實施例之具有增強性能之例示射頻(RF)元件。
[圖2]示出依據本發明之一種實施例之具有增強熱性能及電性能之替代RF元件。
[圖3A]-[圖15]示出一種例示晶圓級製作及封裝程序，其說明用於提供圖1所示例示RF元件之步驟。
[圖16]-[圖21]示出一種替代晶圓級製作及封裝程序，其說明用於提供圖2所示替代RF元件之步驟。
應知[圖1]-[圖21]未必依照比例繪製，以求圖式之明晰。
10:射頻元件
12:轉移元件晶粒
14:元件區域
16:轉移基板
18:多層式重佈結構
20:前段製程(FEOL)部
22:後段製程(BEOL)部
24:主動層
26:接觸層
28:源極
30:汲極
32:通道
34:閘極結構
36:源極接點
38:汲極接點
40:閘極接點
42:絕緣材料
44:絕緣段
48:鈍化層
50:連接層
52:介電質層
54:各重佈互連
56:介電質圖案
58:凸塊結構

Claims (20)

  1. 一種設備，其係包含： 轉移元件晶粒，包含元件區域及轉移基板，其中： 該元件區域包括前段製程(FEOL)部及位於該前段製程部下方之後段製程(BEOL)部，其中該前段製程部包含絕緣段及主動層，該絕緣段包圍該主動層，且該主動層並未垂直延伸超過該絕緣段； 將該元件區域之頂表面平面化；以及 該轉移基板位於該元件區域之該頂表面上方，其中該轉移基板內或該轉移基板與該元件區域內之該主動層之間並不存有未含鍺、氮或氧之矽晶；以及 多層式重佈結構，形成於該轉移元件晶粒之該後段製程部下方，其中該多層式重佈結構包含複數凸塊結構，該複數凸塊結構位於該多層式重佈結構之底表面上並電性耦接至該轉移元件晶粒之該前段製程部。
  2. 如申請專利範圍第1項所述之設備，其中該轉移基板具有大於10 W/m·K之熱導率及大於1E5 Ohm-cm之電阻率。
  3. 如申請專利範圍第2項所述之設備，其中該轉移基板之材質係藍寶石、熱導式石英、氮化鋁、氮化硼及氧化鈹中之一者。
  4. 如申請專利範圍第2項所述之設備，其中該轉移基板之厚度係介於10微米與1000微米之間。
  5. 如申請專利範圍第1項所述之設備，其中該主動層係以應變矽磊晶層形成，其中矽之晶格常數在300 K溫度下大於5.461。
  6. 如申請專利範圍第1項所述之設備，其中： 該後段製程部包含連接層； 該前段製程部進一步包含接觸層，其中該主動層及該絕緣段位於該接觸層上方，且該後段製程部位於該接觸層下方；以及 該多層式重佈結構進一步包含重佈互連，其中該複數凸塊結構經由該多層式重佈結構內之該重佈互連及該後段製程部內之該連接層而電性耦接至該轉移元件晶粒之該前段製程部。
  7. 如申請專利範圍第1項所述之設備，其中該元件區域進一步包括位於該主動層上方且受該絕緣段包圍之鈍化層，其中： 該鈍化層係以二氧化矽形成；且 各絕緣段之頂表面與該鈍化層之頂表面為共平面，且形成該元件區域之該頂表面。
  8. 如申請專利範圍第1項所述之設備，其中各絕緣段之頂表面與該主動層之頂表面為共平面，且形成該元件區域之該頂表面。
  9. 如申請專利範圍第1項所述之設備，其中該轉移元件晶粒進一步包含阻障層，其材質係氮化矽，耦接於該元件區域之該頂表面與該轉移基板之間。
  10. 如申請專利範圍第1項所述之設備，其中該前段製程部係配置為提供開關場效電晶體(FET)、二極體、電容器、電阻器或電感器中之至少一者。
  11. 一種設備，其係包含： 轉移元件晶粒，包含元件區域及轉移基板，其中： 該元件區域包括前段製程(FEOL)部及位於該前段製程部下方之後段製程(BEOL)部，其中該前段製程部包含絕緣段及主動層，該絕緣段包圍該主動層，且該主動層並未垂直延伸超過該絕緣段； 將該元件區域之頂表面平面化；以及 該轉移基板位於該元件區域之該頂表面上方，該轉移基板內或該轉移基板與該元件區域內之該主動層之間並不存有未含鍺、氮或氧之矽晶； 多層式重佈結構，形成於該轉移元件晶粒之該後段製程部下方，其中： 該多層式重佈結構水平延伸超過該轉移元件晶粒；且 該多層式重佈結構包含複數凸塊結構，該複數凸塊結構位於該多層式重佈結構之底表面上，並電性耦接至該轉移元件晶粒之該前段製程部；以及 模塑化合物，位於該多層式重佈結構上方以封裝該轉移元件晶粒。
  12. 如申請專利範圍第11項所述之設備，其中該轉移基板具有大於10 W/m·K之熱導率及大於1E5 Ohm-cm之電阻率。
  13. 如申請專利範圍第12項所述之設備，其中該轉移基板之材質係藍寶石、熱導式石英、氮化鋁、氮化硼及氧化鈹中之一者。
  14. 如申請專利範圍第12項所述之設備，其中該轉移基板之厚度係介於10微米與1000微米之間。
  15. 如申請專利範圍第11項所述之設備，其中該主動層係以應變矽磊晶層形成，其中矽之晶格常數在300 K溫度下大於5.461。
  16. 如申請專利範圍第11項所述之設備，其中： 該後段製程部包含連接層； 該前段製程部進一步包含接觸層，其中該主動層及該絕緣段位於該接觸層上方，且該後段製程部位於該接觸層下方；以及 該多層式重佈結構進一步包含重佈互連，其中該複數凸塊結構經由該多層式重佈結構內之該重佈互連及該後段製程部內之該連接層而電性耦接至該轉移元件晶粒之該前段製程部。
  17. 如申請專利範圍第11項所述之設備，其中該元件區域進一步包括位於該主動層上方且受該絕緣段包圍之鈍化層，其中： 該鈍化層係以二氧化矽形成；且 各絕緣段之頂表面與該鈍化層之頂表面為共平面，且形成該元件區域之該頂表面。
  18. 如申請專利範圍第11項所述之設備，其中各絕緣段之頂表面與該主動層之頂表面為共平面，且形成該元件區域之該頂表面。
  19. 如申請專利範圍第11項所述之設備，其中該轉移元件晶粒進一步包含阻障層，其材質係氮化矽，耦接於該元件區域之該頂表面與該轉移基板之間。
  20. 如申請專利範圍第11項所述之設備，其中該前段製程部係配置為提供開關場效電晶體(FET)、二極體、電容器、電阻器或電感器中之至少一者。
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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11646242B2 (en) 2018-11-29 2023-05-09 Qorvo Us, Inc. Thermally enhanced semiconductor package with at least one heat extractor and process for making the same
KR20210129658A (ko) 2019-01-23 2021-10-28 코르보 유에스, 인크. Rf 반도체 디바이스 및 이를 형성하는 방법
US20200235040A1 (en) 2019-01-23 2020-07-23 Qorvo Us, Inc. Rf devices with enhanced performance and methods of forming the same
US11646289B2 (en) 2019-12-02 2023-05-09 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11923238B2 (en) 2019-12-12 2024-03-05 Qorvo Us, Inc. Method of forming RF devices with enhanced performance including attaching a wafer to a support carrier by a bonding technique without any polymer adhesive
WO2022186857A1 (en) * 2021-03-05 2022-09-09 Qorvo Us, Inc. Selective etching process for si-ge and doped epitaxial silicon
US20230217598A1 (en) * 2021-12-30 2023-07-06 X Display Company Technology Limited Transfer printing high-precision devices

Family Cites Families (333)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS505733Y1 (zh) 1970-02-23 1975-02-18
JPS6013257B2 (ja) 1976-02-20 1985-04-05 松下電器産業株式会社 二次電子増倍体およびその製造方法
JPS5338954A (en) 1976-09-21 1978-04-10 Mitsubishi Electric Corp Strip line circulator
US4366202A (en) 1981-06-19 1982-12-28 Kimberly-Clark Corporation Ceramic/organic web
US5061663A (en) 1986-09-04 1991-10-29 E. I. Du Pont De Nemours And Company AlN and AlN-containing composites
US5069626A (en) 1987-07-01 1991-12-03 Western Digital Corporation Plated plastic castellated interconnect for electrical components
US5013681A (en) 1989-09-29 1991-05-07 The United States Of America As Represented By The Secretary Of The Navy Method of producing a thin silicon-on-insulator layer
US5362972A (en) 1990-04-20 1994-11-08 Hitachi, Ltd. Semiconductor device using whiskers
US5164687A (en) 1991-06-17 1992-11-17 Renaissance Electronics Corp. Compact lumped constant non-reciprocal circuit element
US5294295A (en) 1991-10-31 1994-03-15 Vlsi Technology, Inc. Method for moisture sealing integrated circuits using silicon nitride spacer protection of oxide passivation edges
JP2821830B2 (ja) 1992-05-14 1998-11-05 セイコーインスツルメンツ株式会社 半導体薄膜素子その応用装置および半導体薄膜素子の製造方法
DE69333545T2 (de) 1992-12-24 2005-08-25 Canon K.K. Kunststoffzusatzmittel, Kunststoffzusammensetzung und Kunststoffformmasse, die dieses enthalten
US5459368A (en) 1993-08-06 1995-10-17 Matsushita Electric Industrial Co., Ltd. Surface acoustic wave device mounted module
DE4329696C2 (de) 1993-09-02 1995-07-06 Siemens Ag Auf Leiterplatten oberflächenmontierbares Multichip-Modul mit SMD-fähigen Anschlußelementen
US5391257A (en) 1993-12-10 1995-02-21 Rockwell International Corporation Method of transferring a thin film to an alternate substrate
KR100648751B1 (ko) 1994-05-02 2007-03-02 지멘스 마츠시타 컴포넌츠 게엠베하 운트 콤파니 카게 전자부품용밀봉장치
US6124179A (en) 1996-09-05 2000-09-26 Adamic, Jr.; Fred W. Inverted dielectric isolation process
JP3301262B2 (ja) 1995-03-28 2002-07-15 松下電器産業株式会社 弾性表面波装置
US5729075A (en) 1995-06-12 1998-03-17 National Semiconductor Corporation Tuneable microelectromechanical system resonator
US6013948A (en) 1995-11-27 2000-01-11 Micron Technology, Inc. Stackable chip scale semiconductor package with mating contacts on opposed surfaces
US6137125A (en) 1995-12-21 2000-10-24 The Whitaker Corporation Two layer hermetic-like coating for on-wafer encapsulatuon of GaAs MMIC's having flip-chip bonding capabilities
DE69718693T2 (de) 1996-03-08 2003-11-27 Matsushita Electric Ind Co Ltd Elektronisches Bauteil und Herstellungsverfahren
US5709960A (en) 1996-06-21 1998-01-20 Motorola, Inc. Mold compound
US6250192B1 (en) 1996-11-12 2001-06-26 Micron Technology, Inc. Method for sawing wafers employing multiple indexing techniques for multiple die dimensions
US6117705A (en) 1997-04-18 2000-09-12 Amkor Technology, Inc. Method of making integrated circuit package having adhesive bead supporting planar lid above planar substrate
JPH11220077A (ja) 1997-10-15 1999-08-10 Toshiba Corp 半導体装置および半導体装置の製造方法
KR100253363B1 (ko) 1997-12-02 2000-04-15 김영환 반도체 패키지용 기판과 그 기판을 이용한 랜드 그리드 어레이반도체 패키지 및 그들의 제조 방법
JP3565547B2 (ja) 1998-07-31 2004-09-15 シャープ株式会社 カラー液晶表示装置およびその製造方法
FR2784261B1 (fr) 1998-10-05 2001-07-27 Ge Medical Syst Sa Materiau d'isolation electrique et de refroidissement de conductivite thermique accrue et application a l'isolation d'un dispositif d'alimentation haute tension
US6236061B1 (en) 1999-01-08 2001-05-22 Lakshaman Mahinda Walpita Semiconductor crystallization on composite polymer substrates
KR100643145B1 (ko) 1999-03-26 2006-11-10 히다찌긴조꾸가부시끼가이사 집중 정수형 비상반소자
US6271469B1 (en) 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package
US6154366A (en) 1999-11-23 2000-11-28 Intel Corporation Structures and processes for fabricating moisture resistant chip-on-flex packages
JP4528397B2 (ja) 1999-12-17 2010-08-18 ポリマテック株式会社 接着方法および電子部品
US6426559B1 (en) 2000-06-29 2002-07-30 National Semiconductor Corporation Miniature 3D multi-chip module
JP2002093957A (ja) 2000-09-11 2002-03-29 Sony Corp 電子回路装置およびその製造方法
US6713859B1 (en) 2000-09-13 2004-03-30 Intel Corporation Direct build-up layer on an encapsulated die package having a moisture barrier structure
JP3875477B2 (ja) 2000-09-25 2007-01-31 株式会社東芝 半導体素子
US6423570B1 (en) 2000-10-18 2002-07-23 Intel Corporation Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby
US6377112B1 (en) 2000-12-05 2002-04-23 Semiconductor Components Industries Llc Circuit and method for PMOS device N-well bias control
US20020070443A1 (en) 2000-12-08 2002-06-13 Xiao-Chun Mu Microelectronic package having an integrated heat sink and build-up layers
US6555906B2 (en) 2000-12-15 2003-04-29 Intel Corporation Microelectronic package having a bumpless laminated interconnection layer
JP4673986B2 (ja) 2001-02-23 2011-04-20 星和電機株式会社 表面実装方発光ダイオードの製造方法
US6703688B1 (en) 2001-03-02 2004-03-09 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6943429B1 (en) 2001-03-08 2005-09-13 Amkor Technology, Inc. Wafer having alignment marks extending from a first to a second surface of the wafer
US6706553B2 (en) 2001-03-26 2004-03-16 Intel Corporation Dispensing process for fabrication of microelectronic packages
US6596570B2 (en) 2001-06-06 2003-07-22 International Business Machines Corporation SOI device with reduced junction capacitance
US7332819B2 (en) 2002-01-09 2008-02-19 Micron Technology, Inc. Stacked die in die BGA package
US6841413B2 (en) 2002-01-07 2005-01-11 Intel Corporation Thinned die integrated circuit package
TW577160B (en) * 2002-02-04 2004-02-21 Casio Computer Co Ltd Semiconductor device and manufacturing method thereof
DE10206919A1 (de) 2002-02-19 2003-08-28 Infineon Technologies Ag Verfahren zur Erzeugung einer Abdeckung, Verfahren zum Herstellen eines gehäusten Bauelements
KR100476901B1 (ko) 2002-05-22 2005-03-17 삼성전자주식회사 소이 반도체기판의 형성방법
FR2842832B1 (fr) 2002-07-24 2006-01-20 Lumilog Procede de realisation par epitaxie en phase vapeur d'un film de nitrure de gallium a faible densite de defaut
US7042072B1 (en) 2002-08-02 2006-05-09 Amkor Technology, Inc. Semiconductor package and method of manufacturing the same which reduces warpage
US20040021152A1 (en) 2002-08-05 2004-02-05 Chanh Nguyen Ga/A1GaN Heterostructure Field Effect Transistor with dielectric recessed gate
US7710771B2 (en) 2002-11-20 2010-05-04 The Regents Of The University Of California Method and apparatus for capacitorless double-gate storage
US7067909B2 (en) 2002-12-31 2006-06-27 Massachusetts Institute Of Technology Multi-layer integrated semiconductor structure having an electrical shielding portion
US6855606B2 (en) 2003-02-20 2005-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor nano-rod devices
KR100486627B1 (ko) 2003-02-21 2005-05-03 엘지전자 주식회사 반도체 패키지
JP2004273604A (ja) 2003-03-06 2004-09-30 Fujitsu Ltd 半導体装置と半導体電子部品との製造方法と半導体電子部品
JP3917946B2 (ja) 2003-03-11 2007-05-23 富士通株式会社 積層型半導体装置
US6753239B1 (en) 2003-04-04 2004-06-22 Xilinx, Inc. Bond and back side etchback transistor fabrication process
US6864156B1 (en) 2003-04-04 2005-03-08 Xilinx, Inc. Semiconductor wafer with well contacts on back side
JP3826898B2 (ja) 2003-04-22 2006-09-27 松下電工株式会社 電子部品の製造方法及び半導体装置
US7109635B1 (en) 2003-06-11 2006-09-19 Sawtek, Inc. Wafer level packaging of materials with different coefficients of thermal expansion
US7596849B1 (en) 2003-06-11 2009-10-06 Triquint Semiconductor, Inc. Method of assembling a wafer-level package filter
US6951775B2 (en) 2003-06-28 2005-10-04 International Business Machines Corporation Method for forming interconnects on thin wafers
US20070069393A1 (en) 2003-07-24 2007-03-29 Toshiyuki Asahi Wiring board embedded with spherical semiconductor element
JP2005064188A (ja) 2003-08-11 2005-03-10 Sumitomo Electric Ind Ltd 基板の回収方法および再生方法、ならびに半導体ウエハの製造方法
KR20060120224A (ko) 2003-12-25 2006-11-24 제이에스알 가부시끼가이샤 열가소성 엘라스토머 조성물 및 그의 제조 방법 및 성형품
US7489032B2 (en) 2003-12-25 2009-02-10 Casio Computer Co., Ltd. Semiconductor device including a hard sheet to reduce warping of a base plate and method of fabricating the same
JP4271590B2 (ja) 2004-01-20 2009-06-03 新光電気工業株式会社 半導体装置及びその製造方法
JP3945483B2 (ja) 2004-01-27 2007-07-18 カシオ計算機株式会社 半導体装置の製造方法
US6992400B2 (en) 2004-01-30 2006-01-31 Nokia Corporation Encapsulated electronics device with improved heat dissipation
US20050212419A1 (en) 2004-03-23 2005-09-29 Eastman Kodak Company Encapsulating oled devices
JP3925809B2 (ja) 2004-03-31 2007-06-06 カシオ計算機株式会社 半導体装置およびその製造方法
US7312261B2 (en) 2004-05-11 2007-12-25 International Business Machines Corporation Thermal interface adhesive and rework
JP2005327984A (ja) 2004-05-17 2005-11-24 Shinko Electric Ind Co Ltd 電子部品及び電子部品実装構造の製造方法
US7307346B2 (en) 2004-05-18 2007-12-11 Infineon Technologies Ag Final passivation scheme for integrated circuits
JP4398305B2 (ja) 2004-06-02 2010-01-13 カシオ計算機株式会社 半導体装置およびその製造方法
JP3801601B2 (ja) 2004-06-15 2006-07-26 シャープ株式会社 蓋部を備えた半導体ウェハの製造方法及び半導体装置の製造方法
US7238560B2 (en) 2004-07-23 2007-07-03 Cree, Inc. Methods of fabricating nitride-based transistors with a cap layer and a recessed gate
US7591958B2 (en) 2004-09-14 2009-09-22 Stmicroelectronics Sa Thin glass chip for an electronic component and manufacturing method
US20060099733A1 (en) 2004-11-09 2006-05-11 Geefay Frank S Semiconductor package and fabrication method
US7098070B2 (en) 2004-11-16 2006-08-29 International Business Machines Corporation Device and method for fabricating double-sided SOI wafer scale package with through via connections
TWI259538B (en) 2004-11-22 2006-08-01 Au Optronics Corp Thin film transistor and fabrication method thereof
US7519257B2 (en) 2004-11-24 2009-04-14 Cornell Research Foundation, Inc. Waveguide structure for guiding light in low-index material
JP4581768B2 (ja) 2005-03-16 2010-11-17 ソニー株式会社 半導体装置の製造方法
US7393770B2 (en) 2005-05-19 2008-07-01 Micron Technology, Inc. Backside method for fabricating semiconductor components with conductive interconnects
US7619347B1 (en) 2005-05-24 2009-11-17 Rf Micro Devices, Inc. Layer acoustic wave device and method of making the same
WO2006134928A1 (ja) 2005-06-16 2006-12-21 Murata Manufacturing Co., Ltd. 圧電デバイス及びその製造方法
US20080076371A1 (en) 2005-07-11 2008-03-27 Alexander Dribinsky Circuit and method for controlling charge injection in radio frequency switches
US20070045738A1 (en) * 2005-08-26 2007-03-01 Memc Electronic Materials, Inc. Method for the manufacture of a strained silicon-on-insulator structure
JP4644577B2 (ja) 2005-09-30 2011-03-02 セイコーエプソン株式会社 半導体装置および半導体装置の製造方法
US8465175B2 (en) 2005-11-29 2013-06-18 GE Lighting Solutions, LLC LED lighting assemblies with thermal overmolding
US20090298219A1 (en) 2005-12-26 2009-12-03 Sharp Kabushiki Kaisha Method for Manufacturing Solid-State Image Pickup Device Module
JP4476939B2 (ja) 2006-01-12 2010-06-09 株式会社東芝 半導体装置
US20070194342A1 (en) 2006-01-12 2007-08-23 Kinzer Daniel M GaN SEMICONDUCTOR DEVICE AND PROCESS EMPLOYING GaN ON THIN SAPHIRE LAYER ON POLYCRYSTALLINE SILICON CARBIDE
US20070190747A1 (en) 2006-01-23 2007-08-16 Tessera Technologies Hungary Kft. Wafer level packaging to lidded chips
US7863727B2 (en) 2006-02-06 2011-01-04 Micron Technology, Inc. Microelectronic devices and methods for manufacturing microelectronic devices
JP4591378B2 (ja) 2006-02-21 2010-12-01 株式会社デンソー 半導体装置の製造方法
US20070243662A1 (en) 2006-03-17 2007-10-18 Johnson Donald W Packaging of MEMS devices
US7714535B2 (en) 2006-07-28 2010-05-11 Semiconductor Energy Laboratory Co., Ltd. Power storage device
US7569422B2 (en) 2006-08-11 2009-08-04 Megica Corporation Chip package and method for fabricating the same
KR20080017965A (ko) 2006-08-23 2008-02-27 삼성전자주식회사 가요성 표시 장치용 표시판의 제조 방법
US7749882B2 (en) 2006-08-23 2010-07-06 Micron Technology, Inc. Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
US7816231B2 (en) 2006-08-29 2010-10-19 International Business Machines Corporation Device structures including backside contacts, and methods for forming same
US7960218B2 (en) 2006-09-08 2011-06-14 Wisconsin Alumni Research Foundation Method for fabricating high-speed thin-film transistors
JP5018066B2 (ja) 2006-12-19 2012-09-05 信越半導体株式会社 歪Ｓｉ基板の製造方法
US7888742B2 (en) 2007-01-10 2011-02-15 International Business Machines Corporation Self-aligned metal-semiconductor alloy and metallization for sub-lithographic source and drain contacts
JP2008235490A (ja) 2007-03-19 2008-10-02 Sumitomo Bakelite Co Ltd 中空構造体の製造方法および中空構造体
US20080251927A1 (en) 2007-04-13 2008-10-16 Texas Instruments Incorporated Electromigration-Resistant Flip-Chip Solder Joints
US7960772B2 (en) 2007-04-26 2011-06-14 Peregrine Semiconductor Corporation Tuning capacitance to enhance FET stack voltage withstand
US8183151B2 (en) 2007-05-04 2012-05-22 Micron Technology, Inc. Methods of forming conductive vias through substrates, and structures and assemblies resulting therefrom
KR100923562B1 (ko) 2007-05-08 2009-10-27 삼성전자주식회사 반도체 패키지 및 그 형성방법
US7955955B2 (en) 2007-05-10 2011-06-07 International Business Machines Corporation Using crack arrestor for inhibiting damage from dicing and chip packaging interaction failures in back end of line structures
US20080277778A1 (en) 2007-05-10 2008-11-13 Furman Bruce K Layer Transfer Process and Functionally Enhanced Integrated Circuits Products Thereby
JP2008279567A (ja) 2007-05-11 2008-11-20 Denso Corp 半導体装置の製造方法
US7553752B2 (en) 2007-06-20 2009-06-30 Stats Chippac, Ltd. Method of making a wafer level integration package
KR20090004147A (ko) 2007-07-06 2009-01-12 삼성전자주식회사 반도체 소자 및 그 형성 방법
US20090014856A1 (en) 2007-07-10 2009-01-15 International Business Machine Corporation Microbump seal
JP5013467B2 (ja) 2007-07-18 2012-08-29 株式会社デンソー 半導体装置の製造方法
US9391588B2 (en) 2007-08-31 2016-07-12 Rf Micro Devices, Inc. MEMS vibrating structure using an orientation dependent single-crystal piezoelectric thin film layer
US9941245B2 (en) 2007-09-25 2018-04-10 Intel Corporation Integrated circuit packages including high density bump-less build up layers and a lesser density core or coreless substrate
US7704844B2 (en) 2007-10-04 2010-04-27 International Business Machines Corporation High performance MOSFET
US7868419B1 (en) 2007-10-18 2011-01-11 Rf Micro Devices, Inc. Linearity improvements of semiconductor substrate based radio frequency devices
US7790543B2 (en) 2008-01-11 2010-09-07 International Business Machines Corporation Device structures for a metal-oxide-semiconductor field effect transistor and methods of fabricating such device structures
JP4840373B2 (ja) 2008-01-31 2011-12-21 カシオ計算機株式会社 半導体装置およびその製造方法
JP4568337B2 (ja) 2008-02-22 2010-10-27 株式会社東芝 集積半導体装置
US7749814B2 (en) 2008-03-13 2010-07-06 Stats Chippac, Ltd. Semiconductor device with integrated passive circuit and method of making the same using sacrificial substrate
JP4666028B2 (ja) 2008-03-31 2011-04-06 カシオ計算機株式会社 半導体装置
US20110102002A1 (en) 2008-04-09 2011-05-05 Riehl Bill L Electrode and sensor having carbon nanostructures
JP5415823B2 (ja) 2008-05-16 2014-02-12 株式会社デンソー 電子回路装置及びその製造方法
US7745920B2 (en) 2008-06-10 2010-06-29 Micron Technology, Inc. Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
US20100012354A1 (en) 2008-07-14 2010-01-21 Logan Brook Hedin Thermally conductive polymer based printed circuit board
US8236609B2 (en) 2008-08-01 2012-08-07 Freescale Semiconductor, Inc. Packaging an integrated circuit die with backside metallization
US7843072B1 (en) 2008-08-12 2010-11-30 Amkor Technology, Inc. Semiconductor package having through holes
JP4638530B2 (ja) 2008-08-19 2011-02-23 日本電波工業株式会社 圧電部品及びその製造方法
US20100081237A1 (en) 2008-09-30 2010-04-01 Avago Technologies Fiber Ip (Singapore) Pte. Ltd. Integrated Circuit Assemblies and Methods for Encapsulating a Semiconductor Device
US8173547B2 (en) 2008-10-23 2012-05-08 Lam Research Corporation Silicon etch with passivation using plasma enhanced oxidation
US9059174B2 (en) 2008-11-05 2015-06-16 Stmicroelectronics, Inc. Method to reduce metal fuse thickness without extra mask
JP5161732B2 (ja) 2008-11-11 2013-03-13 新光電気工業株式会社 半導体装置の製造方法
JP5468242B2 (ja) 2008-11-21 2014-04-09 株式会社東芝 Ｍｅｍｓパッケージおよびｍｅｍｓパッケージの製造方法
US7927904B2 (en) 2009-01-05 2011-04-19 Dalsa Semiconductor Inc. Method of making BIOMEMS devices
JP5556072B2 (ja) 2009-01-07 2014-07-23 ソニー株式会社 半導体装置、その製造方法、ミリ波誘電体内伝送装置
SG163445A1 (en) 2009-01-12 2010-08-30 Kolan Ravi Kanth Method for manufacturing a low cost three dimensional stack package and resulting structures using through silicon vias and assemblies
JP4984179B2 (ja) 2009-02-06 2012-07-25 ソニー株式会社 半導体装置
KR101282995B1 (ko) 2009-05-27 2013-07-04 (주)파트론 비가역 회로소자
US8508056B2 (en) 2009-06-16 2013-08-13 Dongbu Hitek Co., Ltd. Heat releasing semiconductor package, method for manufacturing the same, and display apparatus including the same
JP5175803B2 (ja) 2009-07-01 2013-04-03 新光電気工業株式会社 半導体装置の製造方法
US8525335B2 (en) 2009-07-03 2013-09-03 Teramikros, Inc. Semiconductor construct and manufacturing method thereof as well as semiconductor device and manufacturing method thereof
US8921168B2 (en) 2009-07-15 2014-12-30 Silanna Semiconductor U.S.A., Inc. Thin integrated circuit chip-on-board assembly and method of making
US8067833B2 (en) * 2009-07-23 2011-11-29 Raytheon Company Low noise high thermal conductivity mixed signal package
US8432016B1 (en) 2009-07-29 2013-04-30 Rf Micro Devices, Inc. Stacked body-contacted field effect transistor
IN2012DN00452A (zh) 2009-07-30 2015-05-15 Megica Corp
DE112010003296T5 (de) 2009-08-17 2012-12-27 First Solar, Inc. Barriereschicht
US8164158B2 (en) 2009-09-11 2012-04-24 Stats Chippac, Ltd. Semiconductor device and method of forming integrated passive device
US8362599B2 (en) 2009-09-24 2013-01-29 Qualcomm Incorporated Forming radio frequency integrated circuits
WO2011060558A1 (en) 2009-11-18 2011-05-26 Sensirion Ag Sensor mounted in flip-chip technology on a substrate
US9202769B2 (en) 2009-11-25 2015-12-01 Stats Chippac, Ltd. Semiconductor device and method of forming thermal lid for balancing warpage and thermal management
CN102088014A (zh) 2009-12-04 2011-06-08 中国科学院微电子研究所 3d集成电路结构、半导体器件及其形成方法
US8299633B2 (en) 2009-12-21 2012-10-30 Advanced Micro Devices, Inc. Semiconductor chip device with solder diffusion protection
US8030145B2 (en) 2010-01-08 2011-10-04 International Business Machines Corporation Back-gated fully depleted SOI transistor
US9576919B2 (en) 2011-12-30 2017-02-21 Deca Technologies Inc. Semiconductor device and method comprising redistribution layers
US9196509B2 (en) 2010-02-16 2015-11-24 Deca Technologies Inc Semiconductor device and method of adaptive patterning for panelized packaging
JP5544986B2 (ja) 2010-04-01 2014-07-09 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法、及び貼り合わせｓｏｉウェーハ
US9431316B2 (en) 2010-05-04 2016-08-30 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming channels in back surface of FO-WLCSP for heat dissipation
JP5584011B2 (ja) 2010-05-10 2014-09-03 新光電気工業株式会社 半導体パッケージの製造方法
JP2011243596A (ja) 2010-05-14 2011-12-01 Panasonic Corp パッケージ部品の製造方法およびパッケージ部品
JP2011248072A (ja) 2010-05-26 2011-12-08 Hitachi Displays Ltd 画像表示装置の製造方法
US8557679B2 (en) 2010-06-30 2013-10-15 Corning Incorporated Oxygen plasma conversion process for preparing a surface for bonding
KR101698932B1 (ko) 2010-08-17 2017-01-23 삼성전자 주식회사 반도체 패키지 및 그 제조방법
US8551798B2 (en) 2010-09-21 2013-10-08 Taiwan Semiconductor Manufacturing Company, Ltd. Microstructure with an enhanced anchor
JP2012089566A (ja) * 2010-10-15 2012-05-10 Elpida Memory Inc 半導体装置及びその製造方法、並びにデータ処理システム
US20120094418A1 (en) 2010-10-18 2012-04-19 Triquint Semiconductor, Inc. Wafer Level Package and Manufacturing Method Using Photodefinable Polymer for Enclosing Acoustic Devices
US8716051B2 (en) 2010-10-21 2014-05-06 Taiwan Semiconductor Manufacturing Company, Ltd. MEMS device with release aperture
CN102456737B (zh) 2010-10-27 2016-03-30 中国科学院微电子研究所 半导体结构及其制造方法
KR20120053332A (ko) 2010-11-17 2012-05-25 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
JP5703010B2 (ja) 2010-12-16 2015-04-15 新光電気工業株式会社 半導体パッケージ及びその製造方法
US8492210B2 (en) 2010-12-17 2013-07-23 Institute of Microelectronics, Chinese Academy of Sciences Transistor, semiconductor device comprising the transistor and method for manufacturing the same
US8716800B2 (en) 2010-12-31 2014-05-06 Institute of Microelectronics, Chinese Academy of Sciences Semiconductor structure and method for manufacturing the same
US8917510B2 (en) 2011-01-14 2014-12-23 International Business Machines Corporation Reversibly adhesive thermal interface material
JP5715835B2 (ja) 2011-01-25 2015-05-13 新光電気工業株式会社 半導体パッケージ及びその製造方法
US8420447B2 (en) 2011-03-23 2013-04-16 Stats Chippac Ltd. Integrated circuit packaging system with flipchip leadframe and method of manufacture thereof
US8399957B2 (en) 2011-04-08 2013-03-19 International Business Machines Corporation Dual-depth self-aligned isolation structure for a back gate electrode
US8507989B2 (en) 2011-05-16 2013-08-13 International Business Machine Corporation Extremely thin semiconductor-on-insulator (ETSOI) FET with a back gate and reduced parasitic capacitance
US8415743B2 (en) 2011-05-24 2013-04-09 International Business Machines Corporation ETSOI CMOS with back gates
TWI575684B (zh) 2011-06-13 2017-03-21 矽品精密工業股份有限公司 晶片尺寸封裝件
US9633854B2 (en) 2011-06-23 2017-04-25 Institute of Microelectronics, Chinese Academy of Sciences MOSFET and method for manufacturing the same
US8772853B2 (en) 2011-07-12 2014-07-08 The Regents Of The University Of California All graphene flash memory device
US9390364B2 (en) 2011-08-08 2016-07-12 Féinics Amatech Teoranta Transponder chip module with coupling frame on a common substrate for secure and non-secure smartcards and tags
US20130037929A1 (en) 2011-08-09 2013-02-14 Kay S. Essig Stackable wafer level packages and related methods
US9064883B2 (en) 2011-08-25 2015-06-23 Intel Mobile Communications GmbH Chip with encapsulated sides and exposed surface
CN102983116B (zh) 2011-09-07 2015-09-30 中国科学院微电子研究所 半导体衬底、具有该半导体衬底的集成电路及其制造方法
US8963321B2 (en) 2011-09-12 2015-02-24 Infineon Technologies Ag Semiconductor device including cladded base plate
CN103000537B (zh) 2011-09-15 2015-12-09 万国半导体股份有限公司 一种晶圆级的封装结构及其制备方法
CN103000671B (zh) 2011-09-16 2015-07-15 中国科学院微电子研究所 Mosfet及其制造方法
US8803242B2 (en) 2011-09-19 2014-08-12 Eta Semiconductor Inc. High mobility enhancement mode FET
KR101906408B1 (ko) * 2011-10-04 2018-10-11 삼성전자주식회사 반도체 패키지 및 그 제조 방법
US9368429B2 (en) 2011-10-25 2016-06-14 Intel Corporation Interposer for hermetic sealing of sensor chips and for their integration with integrated circuit chips
US9190391B2 (en) 2011-10-26 2015-11-17 Maxim Integrated Products, Inc. Three-dimensional chip-to-wafer integration
US8664044B2 (en) 2011-11-02 2014-03-04 Stmicroelectronics Pte Ltd. Method of fabricating land grid array semiconductor package
US8643148B2 (en) 2011-11-30 2014-02-04 Taiwan Semiconductor Manufacturing Company, Ltd. Chip-on-Wafer structures and methods for forming the same
KR20130064289A (ko) 2011-12-08 2013-06-18 에스케이하이닉스 주식회사 반도체 소자 및 그 제조 방법
US20130193445A1 (en) 2012-01-26 2013-08-01 International Business Machines Corporation Soi structures including a buried boron nitride dielectric
JP2013162096A (ja) 2012-02-08 2013-08-19 Fujitsu Semiconductor Ltd 半導体チップの製造方法及びラミネート装置
KR101918608B1 (ko) 2012-02-28 2018-11-14 삼성전자 주식회사 반도체 패키지
JP6214132B2 (ja) 2012-02-29 2017-10-18 キヤノン株式会社 光電変換装置、撮像システムおよび光電変換装置の製造方法
JP5558595B2 (ja) 2012-03-14 2014-07-23 株式会社東芝 半導体装置及び半導体装置の製造方法
JP2013222745A (ja) 2012-04-13 2013-10-28 Ibiden Co Ltd 電子部品及びその製造方法
US8835978B2 (en) 2012-05-14 2014-09-16 Infineon Technologies Ag Lateral transistor on polymer
JP5903337B2 (ja) 2012-06-08 2016-04-13 新光電気工業株式会社 半導体パッケージ及びその製造方法
US8698323B2 (en) 2012-06-18 2014-04-15 Invensas Corporation Microelectronic assembly tolerant to misplacement of microelectronic elements therein
US8563403B1 (en) 2012-06-27 2013-10-22 International Business Machines Corporation Three dimensional integrated circuit integration using alignment via/dielectric bonding first and through via formation last
US8878360B2 (en) 2012-07-13 2014-11-04 Intel Mobile Communications GmbH Stacked fan-out semiconductor chip
US8653626B2 (en) 2012-07-18 2014-02-18 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures including a capacitor and methods of forming the same
US8963336B2 (en) 2012-08-03 2015-02-24 Samsung Electronics Co., Ltd. Semiconductor packages, methods of manufacturing the same, and semiconductor package structures including the same
KR101970291B1 (ko) 2012-08-03 2019-04-18 삼성전자주식회사 반도체 패키지의 제조 방법
JP6024400B2 (ja) 2012-11-07 2016-11-16 ソニー株式会社 半導体装置、半導体装置の製造方法、及びアンテナスイッチモジュール
US8796072B2 (en) 2012-11-15 2014-08-05 Amkor Technology, Inc. Method and system for a semiconductor device package with a die-to-die first bond
US9431369B2 (en) 2012-12-13 2016-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. Antenna apparatus and method
KR102031731B1 (ko) 2012-12-18 2019-10-14 삼성전자주식회사 반도체 패키지 및 이의 제조방법
US8927405B2 (en) 2012-12-18 2015-01-06 International Business Machines Corporation Accurate control of distance between suspended semiconductor nanowires and substrate surface
US8786105B1 (en) 2013-01-11 2014-07-22 Intel Mobile Communications GmbH Semiconductor device with chip having low-k-layers
US9733428B2 (en) 2013-02-04 2017-08-15 American Semiconductor, Inc. Flexible 3-D photonic device
US9583414B2 (en) 2013-10-31 2017-02-28 Qorvo Us, Inc. Silicon-on-plastic semiconductor device and method of making the same
US9214337B2 (en) * 2013-03-06 2015-12-15 Rf Micro Devices, Inc. Patterned silicon-on-plastic (SOP) technology and methods of manufacturing the same
US9812350B2 (en) 2013-03-06 2017-11-07 Qorvo Us, Inc. Method of manufacture for a silicon-on-plastic semiconductor device with interfacial adhesion layer
US20140252566A1 (en) 2013-03-06 2014-09-11 Rf Micro Devices, Inc. Silicon-on-dual plastic (sodp) technology and methods of manufacturing the same
US20140306324A1 (en) 2013-03-06 2014-10-16 Rf Micro Devices, Inc. Semiconductor device with a polymer substrate and methods of manufacturing the same
US8941248B2 (en) 2013-03-13 2015-01-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device package and method
US8987876B2 (en) 2013-03-14 2015-03-24 General Electric Company Power overlay structure and method of making same
US9070660B2 (en) 2013-03-15 2015-06-30 Intel Corporation Polymer thermal interface material having enhanced thermal conductivity
EP2976380B1 (en) 2013-03-22 2018-10-10 Henkel IP & Holding GmbH Diene/dienophile couples and thermosetting resin compositions having reworkability
US9349700B2 (en) 2013-04-24 2016-05-24 Stats Chippac, Ltd. Semiconductor device and method of forming stress-reduced conductive joint structures
EP2991111A4 (en) 2013-04-26 2017-04-05 Olympus Corporation Image pickup apparatus
US9467192B2 (en) 2013-04-29 2016-10-11 Broadcom Corporation MCM integration and power amplifier matching of non-reciprocal devices
US9275916B2 (en) 2013-05-03 2016-03-01 Infineon Technologies Ag Removable indicator structure in electronic chips of a common substrate for process adjustment
TWI570584B (zh) 2013-05-20 2017-02-11 新思科技有限公司 基於半局部彈道移動模型以模擬半導體裝置之方法及使用其之電腦系統
US9281198B2 (en) 2013-05-23 2016-03-08 GlobalFoundries, Inc. Method of fabricating a semiconductor device including embedded crystalline back-gate bias planes
KR102130700B1 (ko) 2013-05-30 2020-07-07 삼성디스플레이 주식회사 표시장치용 윈도우 및 이를 포함하는 표시 장치
US9059123B2 (en) 2013-07-24 2015-06-16 International Business Machines Corporation Active matrix using hybrid integrated circuit and bipolar transistor
JP6292049B2 (ja) * 2013-09-02 2018-03-14 ソニー株式会社 半導体装置およびその製造方法
US20150060956A1 (en) 2013-09-03 2015-03-05 Windtop Technology Corp. Integrated mems pressure sensor with mechanical electrical isolation
US9806422B2 (en) 2013-09-11 2017-10-31 International Business Machines Corporation Antenna-in-package structures with broadside and end-fire radiations
CN105556659A (zh) 2013-10-15 2016-05-04 英特尔公司 磁屏蔽的集成电路封装
US9627287B2 (en) 2013-10-18 2017-04-18 Infineon Technologies Ag Thinning in package using separation structure as stop
US9576930B2 (en) 2013-11-08 2017-02-21 Taiwan Semiconductor Manufacturing Co., Ltd. Thermally conductive structure for heat dissipation in semiconductor packages
CN103730429B (zh) 2013-12-05 2017-06-20 通富微电子股份有限公司 封装结构
US9269694B2 (en) * 2013-12-11 2016-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with thermal management features for reduced thermal crosstalk and methods of forming same
US9184128B2 (en) 2013-12-13 2015-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC package and methods of forming the same
US9352956B2 (en) 2014-01-16 2016-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. MEMS devices and methods for forming same
US10658358B2 (en) 2015-03-09 2020-05-19 Monolithic 3D Inc. 3D semiconductor wafer, devices, and structure
US9653443B2 (en) 2014-02-14 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Thermal performance structure for semiconductor packages and method of forming same
US10056267B2 (en) 2014-02-14 2018-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US9368455B2 (en) 2014-03-28 2016-06-14 Intel Corporation Electromagnetic interference shield for semiconductor chip packages
US20150311132A1 (en) 2014-04-28 2015-10-29 Taiwan Semiconductor Manufacturing Company, Ltd. Scribe line structure and method of forming same
US9165793B1 (en) 2014-05-02 2015-10-20 Invensas Corporation Making electrical components in handle wafers of integrated circuit packages
US9449837B2 (en) 2014-05-09 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. 3D chip-on-wafer-on-substrate structure with via last process
US10141201B2 (en) 2014-06-13 2018-11-27 Taiwan Semiconductor Manufacturing Company Integrated circuit packages and methods of forming same
KR102245003B1 (ko) 2014-06-27 2021-04-28 삼성전자주식회사 오버행을 극복할 수 있는 반도체 패키지 및 그 제조방법
US9397118B2 (en) 2014-06-30 2016-07-19 International Business Machines Corporation Thin-film ambipolar logic
WO2016007088A1 (en) 2014-07-08 2016-01-14 Massachusetts Institute Of Technology Method of manufacturing a substrate
TWI582847B (zh) 2014-09-12 2017-05-11 Ｒｆ微型儀器公司 包含具有聚合物基板之半導體裝置的印刷電路模組及其製造方法
US10085352B2 (en) 2014-10-01 2018-09-25 Qorvo Us, Inc. Method for manufacturing an integrated circuit package
US9530709B2 (en) 2014-11-03 2016-12-27 Qorvo Us, Inc. Methods of manufacturing a printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity handle layer
KR101647559B1 (ko) 2014-11-07 2016-08-10 앰코 테크놀로지 코리아 주식회사 반도체 패키지의 제조 방법 및 반도체 패키지
US9536853B2 (en) 2014-11-18 2017-01-03 International Business Machines Corporation Semiconductor device including built-in crack-arresting film structure
JP6233285B2 (ja) 2014-11-28 2017-11-22 三菱電機株式会社 半導体モジュール、電力変換装置
DE102014117594A1 (de) 2014-12-01 2016-06-02 Infineon Technologies Ag Halbleiter-Package und Verfahren zu seiner Herstellung
US9548273B2 (en) 2014-12-04 2017-01-17 Invensas Corporation Integrated circuit assemblies with rigid layers used for protection against mechanical thinning and for other purposes, and methods of fabricating such assemblies
US9960145B2 (en) 2015-03-25 2018-05-01 Qorvo Us, Inc. Flip chip module with enhanced properties
US9613831B2 (en) 2015-03-25 2017-04-04 Qorvo Us, Inc. Encapsulated dies with enhanced thermal performance
US9875971B2 (en) 2015-03-26 2018-01-23 Globalfoundries Singapore Pte. Ltd. Magnetic shielding of MRAM package
US9653428B1 (en) 2015-04-14 2017-05-16 Amkor Technology, Inc. Semiconductor package and fabricating method thereof
US20160343604A1 (en) 2015-05-22 2016-11-24 Rf Micro Devices, Inc. Substrate structure with embedded layer for post-processing silicon handle elimination
US9969614B2 (en) 2015-05-29 2018-05-15 Taiwan Semiconductor Manufacturing Company, Ltd. MEMS packages and methods of manufacture thereof
US9815685B2 (en) 2015-06-15 2017-11-14 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor sensing structure and manufacturing method thereof
US9461001B1 (en) 2015-07-22 2016-10-04 Advanced Semiconductor Engineering, Inc. Semiconductor device package integrated with coil for wireless charging and electromagnetic interference shielding, and method of manufacturing the same
US9899285B2 (en) 2015-07-30 2018-02-20 Semtech Corporation Semiconductor device and method of forming small Z semiconductor package
WO2017034929A1 (en) 2015-08-21 2017-03-02 Skyworks Solutions, Inc. Non-uniform spacing in transistor stacks
US9953941B2 (en) 2015-08-25 2018-04-24 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding
US10276495B2 (en) 2015-09-11 2019-04-30 Qorvo Us, Inc. Backside semiconductor die trimming
US9850126B2 (en) 2015-12-31 2017-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method of forming same
US10020405B2 (en) 2016-01-19 2018-07-10 Qorvo Us, Inc. Microelectronics package with integrated sensors
US20170256496A1 (en) 2016-03-01 2017-09-07 Xintec Inc. Chip package and method for forming the same
US10090262B2 (en) 2016-05-09 2018-10-02 Qorvo Us, Inc. Microelectronics package with inductive element and magnetically enhanced mold compound component
US10784149B2 (en) 2016-05-20 2020-09-22 Qorvo Us, Inc. Air-cavity module with enhanced device isolation
US10773952B2 (en) 2016-05-20 2020-09-15 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10103080B2 (en) * 2016-06-10 2018-10-16 Qorvo Us, Inc. Thermally enhanced semiconductor package with thermal additive and process for making the same
CN106098609B (zh) 2016-06-20 2019-03-26 西安电子科技大学 基于非晶化与尺度效应的AlN埋绝缘层上晶圆级单轴应变Si的制作方法
US9859254B1 (en) 2016-06-30 2018-01-02 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and a manufacturing method thereof
US10079196B2 (en) 2016-07-18 2018-09-18 Qorvo Us, Inc. Thermally enhanced semiconductor package having field effect transistors with back-gate feature
US11064609B2 (en) 2016-08-04 2021-07-13 X Display Company Technology Limited Printable 3D electronic structure
CN109844937B (zh) 2016-08-12 2023-06-27 Qorvo美国公司 具有增强性能的晶片级封装
CN109716511A (zh) 2016-08-12 2019-05-03 Qorvo美国公司 具有增强性能的晶片级封装
WO2018031995A1 (en) 2016-08-12 2018-02-15 Qorvo Us, Inc. Wafer-level package with enhanced performance
US9786586B1 (en) 2016-08-21 2017-10-10 Micron Technology, Inc. Semiconductor package and fabrication method thereof
US10109502B2 (en) 2016-09-12 2018-10-23 Qorvo Us, Inc. Semiconductor package with reduced parasitic coupling effects and process for making the same
US11069560B2 (en) * 2016-11-01 2021-07-20 Shin-Etsu Chemical Co., Ltd. Method of transferring device layer to transfer substrate and highly thermal conductive substrate
US10749518B2 (en) 2016-11-18 2020-08-18 Qorvo Us, Inc. Stacked field-effect transistor switch
US10068831B2 (en) 2016-12-09 2018-09-04 Qorvo Us, Inc. Thermally enhanced semiconductor package and process for making the same
DE112016007565T5 (de) 2016-12-30 2019-10-02 Intel Corporation Mikroelektronische bauelemente, entworfen mit 3d-gestapelten, ultradünnen gehäusemodulen für hochfrequenz-kommunikationen
US10529698B2 (en) 2017-03-15 2020-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming same
US10784348B2 (en) 2017-03-23 2020-09-22 Qualcomm Incorporated Porous semiconductor handle substrate
US10460987B2 (en) 2017-05-09 2019-10-29 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package device with integrated antenna and manufacturing method thereof
US10134837B1 (en) 2017-06-30 2018-11-20 Qualcomm Incorporated Porous silicon post processing
US10490471B2 (en) 2017-07-06 2019-11-26 Qorvo Us, Inc. Wafer-level packaging for enhanced performance
US10128199B1 (en) 2017-07-17 2018-11-13 International Business Machines Corporation Interchip backside connection
US10366972B2 (en) 2017-09-05 2019-07-30 Qorvo Us, Inc. Microelectronics package with self-aligned stacked-die assembly
US10784233B2 (en) 2017-09-05 2020-09-22 Qorvo Us, Inc. Microelectronics package with self-aligned stacked-die assembly
US10410999B2 (en) 2017-12-19 2019-09-10 Amkor Technology, Inc. Semiconductor device with integrated heat distribution and manufacturing method thereof
US11011502B2 (en) 2018-01-19 2021-05-18 Nepes Co., Ltd. Semiconductor package
US10727212B2 (en) * 2018-03-15 2020-07-28 Samsung Electronics Co., Ltd. Semiconductor package
US11152363B2 (en) 2018-03-28 2021-10-19 Qorvo Us, Inc. Bulk CMOS devices with enhanced performance and methods of forming the same utilizing bulk CMOS process
US10497648B2 (en) 2018-04-03 2019-12-03 General Electric Company Embedded electronics package with multi-thickness interconnect structure and method of making same
US20190312110A1 (en) 2018-04-04 2019-10-10 Qorvo Us, Inc. Gallium-nitride-based module with enhanced electrical performance and process for making the same
US10804246B2 (en) 2018-06-11 2020-10-13 Qorvo Us, Inc. Microelectronics package with vertically stacked dies
US20200006193A1 (en) 2018-07-02 2020-01-02 Qorvo Us, Inc. Rf devices with enhanced performance and methods of forming the same
WO2020017509A1 (ja) 2018-07-17 2020-01-23 国立大学法人山梨大学 導電性潤滑剤
US11069590B2 (en) 2018-10-10 2021-07-20 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US10964554B2 (en) 2018-10-10 2021-03-30 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US11646242B2 (en) 2018-11-29 2023-05-09 Qorvo Us, Inc. Thermally enhanced semiconductor package with at least one heat extractor and process for making the same
US11251139B2 (en) 2019-01-22 2022-02-15 X-Celeprint Limited Secure integrated-circuit systems
US11387157B2 (en) * 2019-01-23 2022-07-12 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US20200235074A1 (en) 2019-01-23 2020-07-23 Qorvo Us, Inc. Rf devices with enhanced performance and methods of forming the same
KR20210129656A (ko) 2019-01-23 2021-10-28 코르보 유에스, 인크. Rf 반도체 디바이스 및 이를 형성하는 방법
US20200234978A1 (en) 2019-01-23 2020-07-23 Qorvo Us, Inc. Rf devices with enhanced performance and methods of forming the same
US20200235040A1 (en) 2019-01-23 2020-07-23 Qorvo Us, Inc. Rf devices with enhanced performance and methods of forming the same
US20210134699A1 (en) 2019-11-01 2021-05-06 Qorvo Us, Inc. Rf devices with nanotube particles for enhanced performance and methods of forming the same
US11646289B2 (en) 2019-12-02 2023-05-09 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11923238B2 (en) 2019-12-12 2024-03-05 Qorvo Us, Inc. Method of forming RF devices with enhanced performance including attaching a wafer to a support carrier by a bonding technique without any polymer adhesive
US20210188624A1 (en) 2019-12-23 2021-06-24 Qorvo Us, Inc. Microelectronics package with vertically stacked mems device and controller device

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