TWI835983B - 具有增強性能之射頻元件及其形成方法 - Google Patents

具有增強性能之射頻元件及其形成方法 Download PDF

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Publication number
TWI835983B
TWI835983B TW109102892A TW109102892A TWI835983B TW I835983 B TWI835983 B TW I835983B TW 109102892 A TW109102892 A TW 109102892A TW 109102892 A TW109102892 A TW 109102892A TW I835983 B TWI835983 B TW I835983B
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layer
molding compound
silicon
active layer
common
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TW109102892A
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TW202046411A (zh
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朱力奧 Ｃ 科斯塔
麥可 卡羅爾
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美商科沃美國公司
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

本發明係關於一種射頻(RF)元件，其包括一模塑元件晶粒及一位於該模塑元件晶粒下方之多層式重佈結構。該模塑元件晶粒包括一元件區域，該元件區域具有一後段製程(BEOL)部及一位於該BEOL部上方之前段製程(FEOL)部，以及一第一模塑化合物。該FEOL部包括由一應變矽磊晶層形成之一主動層，其中一晶格常數在一300 K溫度下大於5.461。該第一模塑化合物位於該主動層上方。在此，矽晶並不存於該第一模塑化合物與該主動層之間。該多層式重佈結構包括若干凸塊結構，該等凸塊結構位於該多層式重佈結構之一底部且電性耦接至該模塑元件晶粒之該FEOL部。

Description

具有增強性能之射頻元件及其形成方法
本發明係關於一種射頻(RF)元件及其製作程序，更詳而言之，本發明係關於一種具有增強熱性能及電性能之射頻元件，及一種用以提供具有增強性能之射頻元件之晶圓級製作及封裝程序。相關申請案
本申請案主張2019年4月30日所提出之臨時專利申請第62/840,814號及2019年1月23日所提出之臨時專利申請第62/795,804號之優先權，該等申請案之整體經參照合併於此。
本申請係關於2019年11月8日同時提出申請且名為「具有增強性能之射頻元件及其形成方法」之美國專利申請第16/678,573號案，名為「具有增強性能之射頻元件及其形成方法」之美國專利申請第16/678,586號案，名為「具有增強性能之射頻元件及其形成方法」之美國專利申請第16/678,602號案，及名為「具有增強性能之射頻元件及其形成方法」之美國專利申請第16/678,619號案，該等申請案之整體經參照合併於此。
蜂巢式元件及無線元件之廣泛使用帶動射頻(RF)技術之快速發展。射頻元件所用之基板是射頻技術能否達成高階性能之重要因素。於習用矽基板上製作射頻元件具有多種優點，包括矽材料成本低、適合於大規模晶圓製造、現有完善半導體設計工具及現有完善半導體製造技術等多重優點。儘管利用習用矽基板製造射頻元件具有上述優點，業界鹹知習用矽基板對於射頻元件而言具有兩項不利特性，即諧波失真及低電阻率。諧波失真使建立於矽基板上之射頻元件難以達成高階直線性。
並且，高速高性能電晶體係以更高密度整合於射頻元件中。因此，由於射頻元件中所整合之電晶體數量大，通過電晶體之功率量大且/或電晶體之操作速度快等因素，射頻元件所產生之熱大幅增加。據此，宜將射頻元件封裝為利於散熱之配置。
晶圓級扇出型(WLFO)技術及嵌入晶圓級球格陣列(eWLB)技術目前於可攜式射頻應用領域中備受矚目。WLFO及eWLB技術可提供高密度輸入/輸出(I/O)埠而不增加封裝體之體積。因此可於單一晶圓中密集封裝入大量射頻元件。
為增強射頻元件之操作速度及性能，解決射頻元件增加之熱產生並減少射頻元件之諧波失真，同時發揮WLFO/eWLB技術之優點，因此本發明之目的在於提供一種用於射頻元件之改良之晶圓級製作及封裝程序。再者，提升射頻元件之性能但不增加元件尺寸亦為所冀。
本發明係關於一種具有增強性能之射頻(RF)元件及其製作程序。本發明之射頻元件包括一模塑元件晶粒及一多層式重佈結構。模塑元件晶粒包括一第一模塑化合物及一元件區域，元件區域具有一前段製程(FEOL)部及一位於該FEOL部下方之後段製程(BEOL)部。在此，FEOL部具有絕緣段及一主動層，絕緣段包圍主動層，且主動層並未垂直延伸超過絕緣段。主動層係以一應變矽磊晶層形成，其中一晶格常數在一300 K溫度下大於5.461。第一模塑化合物位於FEOL部之主動層上方。第一模塑化合物與主動層之間不存有未含鍺、氮及氧之矽晶。多層式重佈結構係形成於模塑元件晶粒之BEOL部下方，且包括若干凸塊結構。凸塊結構位於多層式重佈結構之一底表面上且電性耦接至模塑元件晶粒之FEOL部。
於該射頻元件之一種實施例中，FEOL部進一步包括一接觸層，主動層及絕緣段位於接觸層上方。BEOL部包括連接層且位於FEOL部之接觸層下方。多層式重佈結構進一步包括位於多層式重佈結構內之重佈互連。在此，經由多層式重佈結構內之重佈互連及BEOL部內之連接層，凸塊結構電性耦接至模塑元件晶粒之FEOL部。
於該射頻元件之一種實施例中，第一模塑化合物之部分位於絕緣段上方。
於該射頻元件之一種實施例中，絕緣段垂直延伸超過主動層之頂表面以在絕緣段內及主動層上方定義一開口。在此，第一模塑化合物填入開口。
依據另一實施例，射頻元件進一步包括一位於主動層之頂表面上方且位於開口中之鈍化層。在此，鈍化層係以二氧化矽、氮化矽或兩者之組合形成，且第一模塑化合物接觸鈍化層。
於該射頻元件之一種實施例中，第一模塑化合物接觸主動層之頂表面。
於該射頻元件之一種實施例中，各絕緣段之頂表面及主動層之頂表面為共平面。在此，第一模塑化合物位於主動層及絕緣段兩者上方。
於該射頻元件之一種實施例中，第一模塑化合物之熱導率大於1 W/m·K。
於該射頻元件之一種實施例中，第一模塑化合物之介電常數小於8。
於該射頻元件之一種實施例中，第一模塑化合物之介電常數介於3與5之間。
於該射頻元件之一種實施例中，FEOL部係配置為提供一開關場效電晶體(FET)、一二極體、一電容器、一電阻器、或一電感器中之至少一者。
依據另一實施例，一種替代射頻元件包括一模塑元件晶粒及一多層式重佈結構。模塑元件晶粒包括一第一模塑化合物及一元件區域，元件區域具有一FEOL部及一位於FEOL部下方之BEOL部。在此，FEOL部具有絕緣段及一主動層，絕緣段包圍主動層，且主動層並不垂直延伸超過絕緣段。主動層係以一應變矽磊晶層形成，其中一晶格常數在一300 K溫度下大於5.461。第一模塑化合物位於FEOL部之主動層上方。第一模塑化合物與主動層之間不存有未含鍺之矽晶。多層式重佈結構係形成於模塑元件晶粒之BEOL部下方，且包括若干凸塊結構。凸塊結構位於多層式重佈結構之一底表面上且電性耦接至模塑元件晶粒之FEOL部。多層式重佈結構水平延伸超過模塑元件晶粒。替代射頻元件進一步包括一位於多層式重佈結構上方之第二模塑化合物以封裝模塑元件晶粒。
於該替代射頻元件之一種實施例中，第一模塑化合物係以與第二模塑化合物相同之材料形成。
於該替代射頻元件之一種實施例中，第一模塑化合物與第二模塑化合物係以不同材料形成。
依據一例示程序，首先提供一前導晶圓，該前導晶圓具有若干元件區域、若干單個介面層及一矽處理基板。各元件區域包括一BEOL部及一位於BEOL部上方之FEOL部。FEOL部具有絕緣段及一主動層，絕緣段包圍主動層，且主動層並不垂直延伸超過絕緣段。在此，各主動層係以一單個應變矽磊晶層形成，其中一晶格常數在一300 K溫度下大於5.461。此外，各單個介面層位於一對應元件區域之主動層上方，且矽處理基板位於各單個介面層上方。各單個介面層係以具有一大於15%之鍺濃度之SiGe形成，且各單個介面層中之晶格常數在一300 K溫度下大於5.461。各單個介電層不受矽處理基板應變。繼而完全移除矽處理基板。隨後施用第一模塑化合物以提供一包括若干模塑元件晶粒之模塑元件晶圓。在此，第一模塑化合物係施用於各元件區域之主動層上方之矽處理基板移除處。各元件區域之主動層與第一模塑化合物之間並不存有未含鍺、氮或氧之矽晶。各模塑元件晶粒包括一對應元件區域及位於對應元件區域之主動層上方之部分第一模塑化合物。
依據另一實施例，例示程序進一步包括在移除矽處理基板之前經由一接合層將前導晶圓接合至一暫時載體，以及在施用第一模塑化合物之後剝離暫時載體並清潔模塑元件晶圓上之接合層。
依據另一實施例，例示程序進一步包括在模塑元件晶圓下方形成一多層式重佈結構。在此，多層式重佈結構包括若干位在多層式重佈結構之一底表面上之凸塊結構及位在多層式重佈結構中之重佈互連。經由多層式重佈結構內之重佈互連及對應模塑元件晶粒之BEOL部內之連接層，將各凸塊結構電性耦接至對應模塑元件晶粒之一個主動層。
依據另一實施例，例示程序進一步包括將模塑元件晶圓切割成若干單個模塑元件晶粒。而後將第二模塑化合物施用於單個模塑元件晶粒之周圍及上方以提供一雙重模塑元件晶圓。在此，第二模塑化合物封裝各單個模塑元件晶粒之一頂表面及側表面，而各單個模塑元件晶粒之一底表面則暴露在外。雙重模塑元件晶圓之一底表面為各單個模塑元件晶粒之底表面與第二模塑化合物之一底表面之結合。繼而於雙重模塑元件晶圓下方形成一多層式重佈結構。多層式重佈結構包括若干位於多層式重佈結構之一底表面上之凸塊結構及位於多層式重佈結構中之重佈互連。經由多層式重佈結構內之重佈互連及對應單個模塑元件晶粒之BEOL部內之連接層，將各凸塊結構電性耦接至對應單個模塑元件晶粒之一個主動層。
於例示程序之一種實施例中，前導晶圓進一步包括若干單個緩衝結構。在此，各單個介面層中鍺濃度為均勻的。各單個緩衝結構位於矽處理基板與對應單個介面層之間。各單個緩衝結構係以具有一垂直梯度鍺濃度之SiGe形成。各單個緩衝結構中之垂直梯度鍺濃度從矽處理基板至對應單個介面層增加。
依據另一實施例，例示程序進一步包括在施用第一模塑化合物之前移除各單個緩衝結構及各介面層，使得各元件區域之主動層在施用第一模塑化合物之後接觸第一模塑化合物。
依據另一實施例，例示程序進一步包括移除各單個緩衝結構及各單個介面層，及在施用第一模塑化合物之前將一鈍化層直接施用於各元件區域之主動層上方。鈍化層係以二氧化矽、氮化矽或兩者之組合形成，且鈍化層在施用第一模塑化合物之後接觸第一模塑化合物。
於例示程序之一種實施例中，提供前導晶圓之步驟始自提供一起始晶圓，其包括一共同應變矽磊晶層、一位於共同應變矽磊晶層上方之共同介面層以及一位於共同介面層上方之矽處理基板。於共同應變矽磊晶層中，一晶格常數在一300 K溫度下大於5.461。共同介面層係以具有一大於15%之鍺濃度之SiGe形成，且共同介電層中之一晶格常數在一300 K溫度下大於5.461。共同介電層不受矽處理基板應變。隨後執行互補式金屬氧化物半導體(CMOS)程序以提供前導晶圓。在此，絕緣段延伸通過共同應變矽磊晶層及共同介面層，並延伸進入矽處理基板，使得共同介面層分隔成若干單個介面層，且共同應變矽磊晶層分隔成若干單個應變矽磊晶層。元件區域之各主動層係以一對應單個應變矽磊晶層形成。各單個介面層位於一對應主動層之一頂表面上方，且矽處理基板位於單個介面層上方。
於例示程序之一種實施例中，起始晶圓進一步包括一介於矽處理基板與共同介面層之間之共同緩衝結構。在此，共同介面層中之鍺濃度為均勻的。共同緩衝結構係以具有一垂直梯度鍺濃度之SiGe形成。共同緩衝結構內之垂直梯度鍺濃度從矽處理基板至共同介面層增加。
於例示程序之一種實施例中，絕緣段延伸通過共同應變矽磊晶層、共同介面層、共同緩衝結構，並延伸進入矽處理基板，使得共同緩衝結構分隔成若干單個緩衝結構，共同介面層分隔成單個介面層，且共同應變矽磊晶層分隔成單個應變矽磊晶層。各單個緩衝結構位於一對應介面層上方，且矽處理基板位於各單個緩衝結構上方。
精於此技藝人士經參照附圖閱讀以下較佳實施例之詳細說明後，應可理解本發明之範疇並領會其各種態樣。
以下提供之實施例陳述供熟悉此技藝人士實施本發明所需之資訊，並說明實踐實施例之最佳方式。經參照附圖閱讀以下說明後，熟悉此技藝人士將可瞭解本發明之概念，且將領會此等概念未盡於本文之各種應用。應知此等概念及應用俱屬本發明及所附申請專利範圍之範疇。
儘管在此可能以第一、第二等術語描述各種元件，應知此等元件並不受限於此等術語。此等術語僅用於區分不同元件。例如，第一元件可改稱為第二元件，且同理，第二元件可改稱為第一元件，而不脫離本發明之範疇。如在此所用，術語「及/或」包括一或多種所列相關項目之任何及全部組合。
應知當於此稱一元件，例如一層體、區域或基板，為位於另一元件上或延伸至另一元件上，其可為直接在另一元件上或直接延伸至另一元件上，或其間亦可能存有其他中間元件。反之，當稱一元件為「直接」位於另一元件上或延伸至另一元件上，表示兩者之間並無其他中間元件存在。同理，應知當稱一元件，例如一層體、區域或基板，為在另一元件上或延伸至另一元件上，其可為直接在另一元件上或直接延伸至另一元件上方或其間亦可能存有其他中間元件。反之，當稱一元件為「直接」位於另一元件上或延伸至另一元件上方，表示兩者之間並無其他中間元件存在。亦應知，當稱一元件「連接」或「耦接」至另一元件，其可直接連接或耦接至另一元件，或其間亦可能存有其他中間元件。反之，當稱一元件「直接連接」或「直接耦接」至另一元件，表示兩者之間並無其他中間元件存在。
在此所用相對性術語，例如「在下」或「在上」或「上方」或「下方」或「水平」或「垂直」係為描述圖中一元件、層體或區域與另一元件、層體或區域之關係。應知此等術語及上文論述者意欲包含與圖中所示不同之元件方向。
在此所用術語僅為描述具體實施，且並非意圖限制本發明。除非上下文另有明確指定，否則在此所用單數形之「一」及「該」亦應包括複數形。亦應知，在此當以「包含」及/或「包括」指定所稱特徵、數值、步驟、操作、元件及/或組件之存在時，並不排除其他一或多種特徵、數值、步驟、操作、元件、組件及/或群組之存在或添加。
除非另有定義，否則在此使用之所有術語(包括技術及科學術語)均具有如同為熟悉本發明所屬技藝人士週知之意義。且應知在此所用術語應採與本說明書上下文及相關技藝中意義相符之解釋，且除非文中如此要求，否則不應採理想化或過度制式之解讀。
有鑑於習用射頻絕緣層上覆矽(RFSOI)晶圓在未來數年可預見之短缺，業界正以利用矽晶圓、富陷阱層形成及智切法SOI晶圓程序等方式研發替代技術，試圖免除高電阻之需求。一種替代技術是基於在矽基板與矽磊晶層之間使用矽鍺(SiGe)介面層取代埋入氧化層(BOX)，從而形成一種矽-矽鍺-矽(Si-SiGe-Si)結構，如圖1所示。然而，此項技術與RFSOI技術同樣難以倖免於來自矽基板之有害失真效應。
於例如300 K之一固定溫度下，鬆弛矽之晶格常數為5.431 Å，而鬆弛Si1-x Gex 之晶格常數取決於鍺濃度，諸如(5.431+0.2x+0.027x2 ) Å，其大於鬆弛鍺之晶格常數，如圖2所示。若矽在鬆弛SiGe上方生長，則矽之晶格常數將係應變的(拉伸的)以匹配下方鬆弛SiGe之晶格常數，如圖3所示。熟悉此技藝人士很清楚應變矽中電子(具有增長之晶格常數)相比於原始/鬆弛矽已經具有增強之遷移率，此係因矽原子彼此相隔很遠地移動，從而減少了原子力對電子遷移的幹擾。然而，於習用Si-SiGe-Si結構中，SiGe介面層生長於矽基板上方，使得SiGe介面層之晶格常數可能由矽基板應變(減小)，且矽磊晶層中晶格常數可保持為原始鬆弛形式(與矽基板中晶格常數大致相同)。因此，習用Si-SiGe-Si結構中之矽磊晶層可能不具有電子遷移率增強。本發明係關於一種射頻(RF)元件及一種製作射頻元件之晶圓級製作及封裝程序，且受益於具有電子遷移率增強而無來自矽基板之有害失真效應之應變矽層。
圖4圖示依據本發明之一種實施例之具有增強性能之例示射頻元件10。為了說明目的，例示射頻元件10包括一具有元件區域14及第一模塑化合物16之模塑元件晶粒12，以及一形成於模塑元件晶粒12下方之多層式重佈結構18。
詳言之，元件區域14包括一前段製程(FEOL)部20及一位於FEOL部20下方之後段製程(BEOL)部22。於一種實施例中，FEOL部20係配置為提供一開關場效電晶體(FET)，且包括一主動層24及一接觸層26。主動層24係以一應變矽磊晶層形成，且包括一源極28、一汲極30、及一介於源極28與汲極30之間之通道32。在此，應變矽磊晶層意指一矽磊晶層，其中矽之晶格常數大於鬆弛矽之晶格常數。應變矽磊晶層中之晶格常數在一300 K溫度下可能大於5.461，或大於5.482，或大於5.493，或大於5.515。以此方式，應變矽磊晶層中電子相比於鬆弛矽層可能具有增強之遷移率。因此，基於主動層24之FET係以應變矽磊晶層形成，且相比於由鬆弛矽層形成之FET可能具有更快速之開關速度。
接觸層26係形成於主動層24下方，且包括一閘極結構34、一源極接點36、一汲極接點38及一閘極接點40。閘極結構34可係以氧化矽形成，且水平延伸於通道32下方(即自源極28下方至汲極30下方)。源極接點36連接至並位於源極28下方，汲極接點38連接至並位於汲極30下方，且閘極接點40連接至並位於閘極結構34下方。源極接點36、汲極接點38、閘極結構34及閘極接點40周圍可形成有絕緣材料42以將源極28、汲極30與閘極結構34電性分隔。於不同應用中，FEOL部20可具有不同FET配置或提供不同元件組件，例如二極體、電容器、電阻器及/或電感器。
此外，FEOL部20亦包括絕緣段44，其位在接觸層26之絕緣材料42上方且包圍主動層24。絕緣段44係配置為將射頻元件10，特別是主動層24，與共同晶圓(圖未示)中之其他元件電性分隔。在此，絕緣段44可從接觸層26之頂表面延伸且垂直超過主動層24之頂表面以在絕緣段44中及主動層24上方定義一開口46。絕緣段44可係以二氧化矽形成，其可耐受例如氢氧化四甲铵(TMAH)、二氟化氙(XeF2 )、氫氧化鉀(KOH)、氫氧化鈉(NaOH)或乙醯膽鹼(ACH)等蝕刻化學藥劑，且可耐受例如具有氯基氣體化學物之活性離子蝕刻(RIE)系統。第一模塑化合物16可係以熱塑性或熱固性聚合物材料形成，例如聚苯硫醚(PPS)、摻雜有氮化硼、氧化鋁、奈米碳管或類鑽石熱添加物之包覆模製環氧化物或類似物。
於一些應用中，射頻元件10可進一步包括鈍化層48，其可係以二氧化矽、氮化矽、或兩者之組合在主動層24之頂表面上方及開口46中形成。以此方式，第一模塑化合物16直接位於鈍化層48上方。鈍化層48係配置為終止主動層24之表面接合，避免造成不期望之洩漏。鈍化層48亦可充當阻障層且係配置為保護主動層24免受濕氣或離子污染。於一些應用中，射頻元件10可進一步包括一介面層及/或一緩衝結構(圖未示)，其等材質為SiGe，位於主動層24之頂表面上方(於下文說明且在此未示)。若鈍化層48、緩衝結構、及介面層存在，則介面層及緩衝結構垂直介於主動層24與鈍化層48之間，且第一模塑化合物16位於鈍化層48上方。若省略鈍化層48，且存在緩衝結構及/或介面層，則介面層及/或緩衝結構垂直介於主動層24與第一模塑化合物16之間。若省略鈍化層48、緩衝結構、及介面層，則第一模塑化合物16可接觸主動層24之頂表面。應注意，不論鈍化層48或介面層存在與否，第一模塑化合物16與主動層24之頂表面之間並不存有未含鍺、氮或氧之矽晶。鈍化層48及介面層皆為矽复合物。
再者，於一些應用中，各絕緣段44之頂表面與主動層24之頂表面可為共平面(圖未示)，且未設開口46。第一模塑化合物16位在FEOL部20之主動層24及絕緣段44兩者之上方。應注意，主動層24不可垂直延伸超過絕緣段44，否則絕緣段44可能無法將主動層24與相同晶圓之其他元件分隔開來。
BEOL部22位在FEOL部20下方且包括多個形成於介電質層52中之連接層50。一些(用於內部連接)連接層50受介電質層52(圖未示)封裝，而一些連接層50之底部則未由介電質層52覆蓋。特定連接層50電性連接至FEOL部20。為說明目的，其中一連接層50連接至源極接點36，且另一連接層50連接至汲極接點38。
形成於模塑元件晶粒12之BEOL部22下方之多層式重佈結構18包括若干重佈互連54、一介電質圖案56及若干凸塊結構58。在此，各重佈互連54連接至BEOL部22中之對應連接層50且延伸在BEOL部22之底表面上方。重佈互連54與連接層50之連接係不經焊接而達成。介電質圖案56係形成於各重佈互連54之周圍及下方。一些重佈互連54(將模塑元件晶粒12連接至相同晶圓形成之其他元件部件)可由介電質圖案56(圖未示)封裝，而一些重佈互連54具有經由介電質圖案56暴露之底部。各凸塊結構58經由介電質圖案56而形成於多層式重佈結構18之底表面且電性耦接至對應重佈互連54。以此方式，重佈互連54係配置為將凸塊結構58連接至BEOL部22中與FEOL部20電性連接之特定連接層50。因此，凸塊結構58經由對應重佈互連54及對應連接層50而電性連接至FEOL部20。此外，凸塊結構58彼此分隔且從介電質圖案56突出。
於一些應用中，可設有經由介電質圖案56電性耦接至重佈互連54之外加重佈互連(圖未示)，以及形成於介電質圖案56下方之外加介電質圖案(圖未示)，使得一些外加重佈互連之底部可暴露在外。因此，各凸塊結構58經由外加介電質圖案(圖未示)而耦接至一對應外加重佈互連。不論重佈互連及/或介電質圖案之層數，多層式重佈結構18可不含玻璃纖維或不含玻璃。在此，玻璃纖維意指經撚搓成較大線股之玻璃線縷。而後可將此等玻璃線縷編成織品。重佈互連54可係以銅或其他適合之金屬形成。介電質圖案56可係以苯並環丁烯(BCB)、聚醯亞胺或其他介電質材料形成。凸塊結構58可為焊球或銅柱。多層式重佈結構18之厚度介於2微米與300微米之間。
元件區域14產生之熱可向上到達位於主動層24上方之第一模塑化合物16之底部，繼而向下通過元件區域14並由多層式重佈結構18將熱散出。因此，非常需要第一模塑化合物16具有高熱導率，尤其對於緊挨著主動層24之部分。第一模塑化合物16之熱導率可介於1 W/m·K與100 W/m·K之間，或介於7 W/m·K與20 W/m·K之間。此外，第一模塑化合物16可具有低介電常數，其可小於8，或介於3與5之間，以降低射頻耦合。第一模塑化合物16之厚度取決於射頻元件10所需熱性能、元件佈局、與多層式重佈結構18相隔距離以及封裝體及組體之詳情。第一模塑化合物16之厚度可介於200微米與500微米之間。
圖5顯示一替代射頻元件10A，其進一步包括一對照圖4所示射頻元件10之第二模塑化合物60。在此，多層式重佈結構18可水平延伸超過模塑元件晶粒12，且第二模塑化合物60位在多層式重佈結構18之上方以封裝模塑元件晶粒12。於此實施例中，多層式重佈結構18之重佈互連54可水平延伸超過模塑元件晶粒12，且多層式重佈結構18之凸塊結構58可不受限於模塑元件晶粒12之外周內。第二模塑化合物60之材質可與第一模塑化合物16相同或不同。不同於第一模塑化合物16，第二模塑化合物60可不具熱導率或介電常數要求。
圖6-圖17提供一種例示晶圓級製作及封裝程序，其說明用於製造圖4所示例示射頻元件10之步驟。儘管例示步驟係按順序說明，但例示步驟並非必須按照固定順序。一些步驟可透過與所示者不同之順序進行。再者，本說明範疇內之程序可較圖6-圖17所示者包括更少或更多步驟。
首先提供如圖6所示之起始晶圓62。起始晶圓62包括一共同應變矽磊晶層64、一位於共同應變矽磊晶層64上方之共同介面層66及一位在共同介面層66上方之矽處理基板68。在此，矽處理基板68可由傳統低成本、低電阻及高介電常數之矽構成，且在一300 K溫度下可具有約5.431之晶格常數。共同介面層66可係以SiGe形成。對於鬆弛Si1-x Gex ，其晶格常數取決於鍺濃度，例如在300 K溫度下之(5.431+0.2x+0.027x2 ) Å，且因此大於矽處理基板68中之晶格常數。
於一種實施例中，共同緩衝結構70可係形成於矽處理基板68與共同介面層66之間，其允許從矽處理基板68至共同介面層66之晶格常數轉換。共同緩衝結構70可包括多個層且可係以具有一垂直梯度鍺濃度之SiGe形成。共同緩衝結構70中之鍺濃度可從頂側之0%(緊挨著矽處理基板68)增長至底側之X%(緊挨著共同介面層66)。X%可取決於共同介面層66中之鍺濃度，例如15%、或25%、或30%、或40%。共同介面層66在此生長於共同緩衝結構70上方，且可將其晶格常數保持為鬆弛形式，且可不受應變(減小)以匹配矽處理基板68之晶格常數。鍺濃度可於整個共同介面層66中為均勻的且大於15%、25%、30%、或40%，使得共同介面層66中鬆弛SiGe之晶格常數在300 K溫度下大於5.461，或大於5.482，或大於5.493，或大於5.515。
共同應變矽磊晶層64可係以元件級矽材料形成，且具有形成電子元件所需之矽磊晶特性。在此，共同應變矽磊晶層64直接生長於共同介面層66上方，使得共同應變矽磊晶層64之晶格常數與下方共同介面層66(鬆弛SiGe)中之晶格常數匹配(同樣拉伸)。因此，共同應變矽磊晶層64中之晶格常數在300 K溫度下可大於5.461，或大於5.482，或大於5.493，或大於5.515，且因此大於鬆弛矽磊晶層中之晶格常數(例如，在300 K溫度下為5.431)。共同應變矽磊晶層64可具有顯著高於鬆弛矽磊晶層之電子遷移率。共同應變矽磊晶層64之厚度可介於700奈米與2000奈米之間，共同介面層66之厚度可介於200 Å與600 Å之間，共同緩衝結構70之厚度可介於10 Å與5000 Å之間，且矽處理基板68之厚度可介於200微米與700微米之間。
於另一實施例中，共同介面層66可直接形成於矽處理基板68上方，及共同緩衝結構70可形成於共同介面層66與共同應變矽磊晶層64(圖未示)之間。在此，共同介面層66之晶格常數可由矽處理基板68應變(減小)。共同緩衝結構70可仍然係以具有一垂直梯度鍺濃度之SiGe形成。共同緩衝結構70中之鍺濃度可從頂側之0%(緊挨著共同介面層66)增長至底側之X%(緊挨著共同應變矽磊晶層64)。X%可為15%，或25%，或30%，或40%。共同緩衝結構70之底側處晶格常數大於共同緩衝結構70之頂側處晶格常數。共同應變矽磊晶層64在此生長於共同緩衝結構70上方，且具有與共同緩衝結構70之底側處晶格常數匹配(共同拉伸)之晶格常數。因此，共同應變矽磊晶層64之晶格常數大於鬆弛矽磊晶層之晶格常數(例如，在300 K溫度下為5.431)。
繼而在起始晶圓62上執行互補式金屬氧化物半導體(CMOS)程序，以提供一具有若干元件區域14之前導晶圓72，如圖7A所示。為說明目的，各元件區域14之FEOL部20係配置為提供一開關FET。於不同應用中，FEOL部20可具有不同FET配置或提供不同元件組件，例如二極體、電容器、電阻器及/或電感器。
於一種實施例中，各元件區域14之絕緣段44延伸通過共同應變矽磊晶層64、共同介面層66、及共同緩衝結構70，並延伸進入矽處理基板68。以此方式，共同緩衝結構70分隔成若干單個緩衝結構70I，共同介面層66分隔成若干單個介面層66I，且共同應變矽磊晶層64分隔成若干單個應變矽磊晶層64I。各單個應變矽磊晶層64I用於在其中一個元件區域14中形成一對應主動層24。絕緣段44可係以淺溝槽隔離(STI)形成。在此，由於主動層24係以一個單個應變矽磊晶層64I形成，其中晶格常數大於鬆弛矽磊晶層中之晶格常數，取決於主動層24之FET之開關速度(ON-電阻)比取決於鬆弛/習用矽磊晶層之FET快(低)。
主動層24之頂表面接觸對應介面層66I且位於對應緩衝結構70I下方。矽處理基板68位於各單個緩衝結構70I上方，且部分矽處理基板68可位於絕緣段44上方。元件區域14之BEOL部22包括至少多個連接層50及介電層52，且形成於FEOL部20之接觸層26下方。於BEOL部22之底表面處，經由介電質層52將特定連接層50之底部暴露在外。
於另一實施例中，絕緣段44可不延伸進入矽處理基板68中。反之，絕緣段44可僅延伸通過共同應變矽磊晶層64且延伸進入共同介面層66，如圖7B所示。在此，共同介面層66保持連續，且位於各主動層24之頂表面上方及各絕緣段44之頂表面上方。共同緩衝結構70及矽處理基板68保持完好。此外，絕緣段44可延伸通過共同應變矽磊晶層64及共同介面層66，且延伸進入共同緩衝結構70(圖未示)。共同緩衝結構70保持連續且位於各單個介面層66I及各絕緣段44上方。矽處理基板68保持在共同緩衝結構70上方。此外，絕緣段44可延伸通過共同應變矽磊晶層64，但並不延伸進入共同介面層66(圖未示)。各絕緣段44之頂表面與各主動層24之頂表面可為共平面(圖未示)。共同介面層66、共同緩衝結構70、及矽處理基板68保持完好。共同介面層66位於各絕緣段44及各主動層24上方，共同緩衝結構70保持在共同介面層66上方，且矽處理基板68保持在共同緩衝結構70上方。
在前導晶圓72完成之後，繼而將前導晶圓72接合至暫時載體74，如圖8所示。前導晶圓72可經由接合層76而接合至暫時載體74，接合層76將平坦表面提供至暫時載體74。基於成本及熱膨脹之考量，暫時載體74可為厚矽晶圓，但亦可為玻璃、藍寶石或任何其他適合之載體材料。接合層76可為跨上式聚合黏膠膜，例如布魯爾科技晶圓BOND系列之暫時黏合材料。
隨後選擇性移除矽處理基板68以提供經蝕刻後之晶圓78，如圖9所示。選擇性移除停止在各單個緩衝結構70I或各介面層66I(圖未示)處。若絕緣段44垂直延伸超過各單個緩衝結構70I，則移除矽處理基板68將在各主動層24上方且絕緣段44中提供開口46。移除矽處理基板68可藉由機械研磨製程及蝕刻製程提供，或藉由蝕刻製程本身提供。例如，可將矽處理基板68研磨至較薄厚度，以縮短下述蝕刻時間。而後執行蝕刻製程以至少完全地移除剩餘矽處理基板68。由於矽處理基板68、單個緩衝結構70I、及單個介面層66I具有不同鍺濃度，其對於相同蝕刻技術可能產生不同反應(例如：相同蝕刻劑下不同蝕刻速度)。因此，蝕刻系統能夠辨識單個緩衝結構70I或單個介面層66I之存在(鍺存在)，並能夠指示何時停止蝕刻製程。通常，鍺濃度越高，矽處理基板68與單個緩衝結構70I之間(或矽處理基板68與單個介面層66I之間)之蝕刻選擇性越好。蝕刻製程可由具有蝕刻劑化學藥劑之濕式蝕刻系統或乾式蝕刻系統來提供，蝕刻劑化學藥劑為TMAH、KOH、NaOH、ACH、及XeF2 中之至少一者，乾式蝕刻系統例如具有氯基氣體化學物之活性離子蝕刻系統。
在移除製程期間，絕緣段44並不移除且保護各FEOL部20之側面。接合層76及暫時載體74保護各BEOL部22之底表面。在此，在移除步驟之後將各絕緣段44之頂表面及各單個緩衝結構70I(或各單個介面層66I)之頂表面暴露在外。若絕緣段44僅延伸進入共同緩衝結構70，或僅延伸進入共同介面層66，或各絕緣段44之頂表面與各主動層24之頂表面為共平面的，則僅有共同緩衝結構70或共同介面層66之頂表面可暴露在外(圖未示)。
由於SiGe材料之窄帶隙特性，單個緩衝結構70I及/或單個介面層66I可能具有傳導性(針對某類元件)。單個緩衝結構70I及/或單個介面層66I可在主動層24之源極28與汲極30之間造成可察知洩漏。因此，於一些應用中，例如FET開關應用，亦宜將單個緩衝結構70I及單個介面層66I移除，如圖10所示。若有一個開口46位於各主動層24上，則將各主動層24暴露在對應開口46之底部。單個緩衝結構70I及單個介面層66I可由與移除矽處理基板68之蝕刻製程相同之蝕刻製程移除，或可藉由例如氯基乾式蝕刻系統之另一蝕刻製程移除。在此，若各單個介面層66I足夠薄，則其在FEOL部20之源極28與汲極30之間可不造成任何可察知洩漏。在此情況下，可將單個介面層66I完整保留(圖未示)。同樣地，若單個介面層66I及單個緩衝結構70I皆足夠薄，則其在FEOL部20之源極28與汲極30之間可不造成任何可察知洩漏。在此情況下，可將單個介面層66I及單個緩衝結構70I完整保留(圖未示)。
於一些應用中，在移除矽處理基板68、單個緩衝結構70I及單個介電層66I之後，可鈍化主動層24以達成元件中適當低洩電流水平。鈍化層48可直接形成於各FEOL部20之各主動層24上方，如圖11所示。鈍化層48可藉由化學氣相沉積(CVD)介電質成膜或鈍化電漿而以二氧化矽、氮化矽或兩者組合形成。若各主動層24上及絕緣段44内有開口46，則鈍化層48形成於開口46中。鈍化層48係配置為終止主動層24頂表面處之表面接合，避免造成不期望之洩漏。
繼而將第一模塑化合物16施用於經蝕刻後晶圓78上方以提供一模塑元件晶圓80，如圖12所示。模塑元件晶圓80包括若干模塑元件晶粒12，其各包括元件區域14，以及第一模塑化合物16之部分。在此，第一模塑化合物16填入各開口46且接觸開口46中之鈍化層48。此外，第一模塑化合物16之部分可延伸於絕緣段44上方。若各開口46中未形成有鈍化層48，則第一模塑化合物16可接觸各主動層24之頂表面(圖未示)。若各單個介面層66I保持在各主動層24之頂表面上方，則第一模塑化合物16可接觸單個介面層66I(圖未示)。若單個介面層66I及單個緩衝結構70I皆保持在各主動層24之頂表面上方，則第一模塑化合物16可接觸單個緩衝結構70I(圖未示)。第一模塑化合物16始終位於各主動層24上方。應注意，不論鈍化層48或單個介面層66I存在與否，第一模塑化合物16與各主動層24之頂表面之間並不存有未含鍺、氮或氧之矽晶。鈍化層48及單個介面層66I皆為矽複合物。
第一模塑化合物16可藉由各種程序施用，例如壓縮模製、片狀模塑、包覆模製、轉移模製、圍堰填充封裝及網版印刷封裝。第一模塑化合物16可具有介於1 W/m·K與100 W/m·K之間，或介於7 W/m·K與20 W/m·K之間的熱導率。第一模塑化合物16可具有小於8或介於3與5之間的介電常數。於第一模塑化合物16之模製程序中，暫時載體74為蝕刻後之晶圓78提供機械強度及剛性。隨後以固化程序(圖未示)使第一模塑化合物16硬化。固化溫度介於100℃與320℃之間，這取決於哪種材料用作第一模塑化合物16。經固化程序後，可對第一模塑化合物16進行減薄及/或平坦化處理(圖未示)。
繼而將暫時載體74自模塑元件晶圓80剝離，並清除模塑元件晶圓80上之接合層76，如圖13所示。可依據先前步驟所選用暫時載體74及接合層76之性質實施若干剝離程序及清潔程序。例如，可將堆疊體加熱至適當溫度，利用側刀程序以機械方式將暫時載體74剝離。若暫時載體74為透明材料，可使用紫外光輻射，其他適合之程序亦包括使用適當溶劑之化學剝離。接合層76之移除可經由濕式或乾式蝕刻程序達成，例如專有溶劑及電漿清洗。經剝離及清潔程序後，作為模塑元件晶粒12之輸入/輸出(I/O)埠之特定連接層50之底部可經由各BEOL部22底表面之介電質層52而暴露在外。以此方式，可於此時以電性方式驗證模塑元件晶圓80中之各模塑元件晶粒12是否功能正常。
參照圖14至圖16，依據本發明之一種實施例，多層式重佈結構18係形成於模塑元件晶圓80下方。儘管在此依序說明重佈步驟，但重佈步驟並非必須按照固定順序。一些步驟可透過與所示者不同之順序進行。再者，本說明範疇內之重佈步驟可較圖14-圖16所示者包括更少或更多步驟。
首先在各BEOL部22下方形成若干重佈互連54，如圖14所示。各重佈互連54電性耦接至BEOL部22中對應連接層50暴露在外之底部，且可延伸於BEOL部22之底表面上方。重佈互連54與連接層50間之連結係不經焊接而達成。接著介電質圖案56形成於各BEOL部22下方，以部分封裝各重佈互連54，如圖15所示。以此方式，各重佈互連54之底部經由介電質圖案56而暴露在外。於不同應用中，可包含經由介電質圖案56而電性耦接至重佈互連54之外加重佈互連(圖未示)，以及形成於介電質圖案56下方之外加介電質圖案(圖未示)，使得各外加重佈互連之底部暴露在外。
接著，形成若干凸塊結構58以完成多層式重佈結構18並提供一晶圓級扇出型(WLFO)封裝體82，如圖16所示。各凸塊結構58形成於多層式重佈結構18之底部並電性耦接至對應重佈互連54經由介電質圖案56暴露在外之底部。因此，重佈互連54係配置為將凸塊結構58連接至BEOL部22中與FEOL部20電性連接之特定連接層50。以此方式，凸塊結構58經由對應重佈互連54及對應連接層50而電性連接至FEOL部20。此外，凸塊結構58彼此分離且從介電質圖案56突出。
多層式重佈結構18可不含玻璃纖維或不含玻璃。在此，玻璃纖維意指經撚搓成較大線股之玻璃線縷。而後可將此等玻璃線縷編成織品。重佈互連54可係以銅或其他適合之金屬形成，介電質圖案56可係以BCB、聚醯亞胺或其他介電質材料形成，且凸塊結構58可為焊球或銅柱。多層式重佈結構18之厚度介於2微米與300微米之間。圖17顯示將WLFO封裝體82切割成單個射頻元件10之最終步驟。所述切割步驟可藉由在特定絕緣段44實施針測及切割程序而達成。
於另一實施例中，圖18-圖23提供一種用於製造圖5所示替代射頻元件10A之步驟之替代程序。儘管在此依序說明例示步驟，但各步驟並非必須按照固定順序。一些步驟可透過與所示者不同之順序進行。再者，本說明範疇內之程序可較圖18-圖23所示者包括更少或更多步驟。
經以剝離及清潔程序產生圖13所示之潔淨模塑元件晶圓80之後，執行切割步驟將模塑元件晶圓80切割成單個模塑元件晶粒12，如圖18所示。所述切割步驟可藉由在特定絕緣段44實施針測及切割程序而達成。在此，各模塑元件晶粒12可具有相同高度，且包括具有FEOL部20與BEOL部22之元件區域14，並包括第一模塑化合物16。
而後，將第二模塑化合物60施用於模塑元件晶粒12之周圍及上方以提供一雙重模塑元件晶圓84，如圖19所示。第二模塑化合物60封裝各模塑元件晶粒12之頂表面及側表面，但使各模塑元件晶粒12之底表面，即BEOL部22之底表面，暴露在外。雙重模塑元件晶圓84之底表面為各模塑元件晶粒12之底表面與第二模塑化合物60之底表面之結合。在此，特定連接層50之底部保持暴露於各模塑元件晶粒12之底表面。第二模塑化合物60可藉由各種程序施用，例如片狀模塑、包覆模製、壓縮模製、轉移模製、圍堰填充封裝或網版印刷封裝。第二模塑化合物60之材料可與第一模塑化合物16相同或不同。然而，不同於第一模塑化合物16，第二模塑化合物60並不具有熱導率或電阻率要求。第二模塑化合物60可為有機環氧樹脂系統或類似物。之後使用固化程序(圖未示)使第二模塑化合物60硬化。固化溫度介於100℃與320℃之間，這取決於哪種材料用作第二模塑化合物60。可執行研磨程序(圖未示)以提供第二模塑化合物60之平坦頂表面。
參照圖20至圖22，依據本發明之一種實施例，形成多層式重佈結構18。儘管在此依序說明重佈步驟，但重佈步驟並非必須按照固定順序。一些步驟可透過與所示者不同之順序進行。再者，本說明範疇內之重佈步驟可較圖20-圖22所示者包括更少或更多步驟。
首先於雙重模塑元件晶圓84下方形成若干重佈互連54，如圖20所示。各重佈互連54係電性耦接至BEOL部22內之對應連接層50，且可水平延伸超過對應模塑元件晶粒12並延伸於第二模塑化合物60下方。重佈互連54與連接層50間之連結係不經焊接而達成。而後介電質圖案56形成於雙重模塑元件晶圓84下方，以部分封裝各重佈互連54，如圖21所示。以此方式，各重佈互連54之底部經由介電質圖案56而暴露在外。於不同應用中，可包含經由介電質圖案56而電性耦接至重佈互連54之外加重佈互連(圖未示)，以及形成於介電質圖案56下方之外加介電質圖案(圖未示)，使得各外加重佈互連之底部暴露在外。
接著，形成若干凸塊結構58以完成多層式重佈結構18並提供一替代WLFO封裝體82A，如圖22所示。各凸塊結構58形成於多層式重佈結構18之底部並電性耦接至對應重佈互連54經由介電質圖案56暴露在外之底部。因此，重佈互連54係配置為將凸塊結構58連接至BEOL部22中與FEOL部20電性連接之特定連接層50。以此方式，凸塊結構58經由對應重佈互連54及對應連接層50而電性連接至FEOL部20。在此，凸塊結構58可不受限於對應模塑元件晶粒12之外周中。此外，凸塊結構58彼此分離且從介電質圖案56垂直地突出。
圖23顯示將替代WLFO封裝體82A切割成單個替代射頻元件10A之最終步驟。所述切割步驟可經由在第二模塑化合物60之水平位於相鄰模塑元件晶粒12間之部分實施針測及切割程序而達成。
熟悉此技藝人士應可領會本發明較佳實施例之改良及修改。所有此等之改良及修改均應屬於本發明概念及所附申請專利範圍之範疇。
10:射頻元件 10A:替代射頻元件 12:模塑元件晶粒 14:元件區域 16:第一模塑化合物 18:多層式重佈結構 20:前段製程(FEOL)部 22:後段製程(BEOL)部 24:主動層 26:接觸層 28:源極 30:汲極 32:通道 34:閘極結構 36:源極接點 38:汲極接點 40:閘極接點 42:絕緣材料 44:絕緣段 46:開口 48:鈍化層 50:連接層 52:介電質層 54:重佈互連 56:介電質圖案 58:凸塊結構 60:第二模塑化合物 62:起始晶圓 64:矽磊晶層 64I: 單個應變矽磊晶層 66:共同介面層 66I:介面層 68:矽處理基板 70:共同緩衝結構 70I: 單個緩衝結構 72:前導晶圓 74:暫時載體 76:接合層 78:經蝕刻後之晶圓 80:模塑元件晶圓 82A:替代WLFO封裝體 82:晶圓級扇出型(WLFO)封裝體 84:雙重模塑元件晶圓
本說明書所附圖式說明本發明之數種態樣，且配合敘述內容共同闡明本發明之原理。
[圖1]圖示一種典型矽-矽鍺-矽(Si - SiGe - Si)結構。
[圖2]圖示鬆弛矽及鬆弛矽鍺。
[圖3]圖示在鬆弛矽鍺上方生長之應變矽。
[圖4]圖示依據本發明之一種實施例之具有增強性能之例示射頻(RF)元件。
[圖5]圖示依據本發明之一種實施例之具有增強熱性能及電性能之替代射頻元件。
[圖6]-[圖17]圖示一種例示晶圓級製作及封裝程序，其說明用於提供圖4所示例示射頻元件之步驟。
[圖18]-[圖23]圖示一種替代晶圓級製作及封裝程序，其說明用於提供圖5所示替代射頻元件之步驟。
應知[圖1]-[圖23]未必依照比例繪製，以求圖式之明晰。
10:射頻元件
12:模塑元件晶粒
14:元件區域
16:第一模塑化合物
18:多層式重佈結構
20:前段製程(FEOL)部
22:後段製程(BEOL)部
24:主動層
26:接觸層
28:源極
30:汲極
32:通道
34:閘極結構
36:源極接點
38:汲極接點
40:閘極接點
42:絕緣材料
44:絕緣段
46:開口
48:鈍化層
50:連接層
52:介電質層
54:重佈互連
56:介電質圖案
58:凸塊結構

Claims (26)

  1. 一種射頻(RF)元件，其係包含：模塑元件晶粒，包含元件區域及第一模塑化合物，其中：該元件區域包括前段製程(FEOL)部及位於該前段製程部下方之後段製程(BEOL)部，其中該前段製程部包含絕緣段及主動層，該絕緣段由二氧化矽構成，該主動層被該絕緣段包圍，且該主動層並未垂直延伸超過該絕緣段；該主動層係由應變矽磊晶層形成，其中矽晶格常數在300 K溫度下大於5.461；以及該第一模塑化合物位於該前段製程部之該主動層上方，該第一模塑化合物與該主動層之間並不存有未含鍺、氮及氧之矽晶；以及多層式重佈結構，形成於該模塑元件晶粒之該後段製程部下方，其中該多層式重佈結構包含複數凸塊結構，該複數凸塊結構位於該多層式重佈結構之底表面上且電性耦接至該模塑元件晶粒之該前段製程部。
  2. 如申請專利範圍第1項所述之射頻元件，其中：該後段製程部包含連接層；該前段製程部進一步包含接觸層，其中該主動層及該絕緣段位於該接觸層上方，且該後段製程部位於該接觸層下方；以及該多層式重佈結構進一步包含重佈互連，其中該複數凸塊結構係經由該多層式重佈結構內之該重佈互連及該後段製程部內之該連接層而電性耦接至該模塑元件晶粒之該前段製程部。
  3. 如申請專利範圍第1項所述之射頻元件，其中該第一模塑化合物之一部分位於該絕緣段上方。
  4. 如申請專利範圍第1項所述之射頻元件，其中該絕緣段垂直延伸 超過該主動層之頂表面以在該絕緣段內及該主動層上方定義開口，其中該第一模塑化合物填入該開口。
  5. 如申請專利範圍第4項所述之射頻元件，進一步包含位於該主動層之該頂表面上方且在該開口內之鈍化層，其中：該鈍化層係由二氧化矽、氮化矽、或兩者之組合形成；且該第一模塑化合物接觸該鈍化層。
  6. 如申請專利範圍第4項所述之射頻元件，其中該第一模塑化合物接觸該主動層之該頂表面。
  7. 如申請專利範圍第1項所述之射頻元件，其中各絕緣段之頂表面與該主動層之頂表面為共平面，其中該第一模塑化合物位於該主動層及該絕緣段兩者上方。
  8. 如申請專利範圍第1項所述之射頻元件，其中該第一模塑化合物之熱導率大於1W/m．K。
  9. 如申請專利範圍第1項所述之射頻元件，其中該第一模塑化合物之介電常數小於8。
  10. 如申請專利範圍第1項所述之射頻元件，其中該第一模塑化合物之介電常數介於3與5之間。
  11. 如申請專利範圍第1項所述之射頻元件，其中該前段製程部係配置為提供開關場效電晶體(FET)、二極體、電容器、電阻器、或電感器中之至少一者。
  12. 一種射頻(RF)元件，其係包含：模塑元件晶粒，包含元件區域及第一模塑化合物，其中：該元件區域包含前段製程(FEOL)部及位於該前段製程部下方之後段製程 (BEOL)部，其中該前段製程部包含絕緣段及主動層，該絕緣段包圍該主動層，且該主動層並未垂直延伸超過該絕緣段；該主動層係由應變矽磊晶層形成，其中晶格常數在300 K溫度下大於5.461；以及該第一模塑化合物位於該前段製程部之該主動層上方，該第一模塑化合物與該主動層之間並不存有未含鍺、氮及氧之矽晶；多層式重佈結構，形成於該模塑元件晶粒之該後段製程部下方，其中：該多層式重佈結構水平延伸超過該模塑元件晶粒；且該多層式重佈結構包含複數凸塊結構，該複數凸塊結構位於該多層式重佈結構之底表面上，且電性耦接至該模塑元件晶粒之該前段製程部；以及第二模塑化合物，位於該多層式重佈結構上方以封裝該模塑元件晶粒。
  13. 如申請專利範圍第12項所述之射頻元件，其中該第一模塑化合物係以與該第二模塑化合物相同之材料形成。
  14. 如申請專利範圍第12項所述之射頻元件，其中該第一模塑化合物與該第二模塑化合物係以不同材料形成。
  15. 一種用於製造射頻(RF)元件的方法，其係包含：提供前導晶圓，其包含複數元件區域、複數單個介面層、及矽處理基板，其中：各該元件區域包括後段製程(BEOL)部及位於該後段製程部上方之前段製程(FEOL)部，其中該前段製程部包含絕緣段及主動層，該絕緣段包圍該主動層，且該主動層並未垂直延伸超過該絕緣段；各該單個介面層直接位於對應元件區域之一個主動層上方，其中各該單個介面層係由具有大於15%之均勻鍺濃度之矽鍺(SiGe)形成； 該矽處理基板位於各該單個介面層上方，其中各該單個介面層不受該矽處理基板應變，且其晶格常數在300 K溫度下大於5.461；且以單個應變矽磊晶層形成之各主動層生長於對應單個介面層上方，其中該單個應變矽磊晶層中之矽晶格常數在300 K溫度下大於5.461；完全移除該矽處理基板；以及施用第一模塑化合物以提供模塑元件晶圓，該模塑元件晶圓包括複數模塑元件晶粒；其中：該第一模塑化合物係施用於各該元件區域之該主動層上方的該矽處理基板移除處；各該元件區域之該主動層與該第一模塑化合物之間並不存有未含鍺、氮及氧之矽晶；且各該模塑元件晶粒包括對應元件區域及該第一模塑化合物在該對應元件區域之該主動層上方之一部分。
  16. 如申請專利範圍第15項所述之方法，進一步包含：在移除該矽處理基板之前經由接合層將該前導晶圓接合至暫時載體；以及在施用該第一模塑化合物之後剝離該暫時載體並清潔該模塑元件晶圓上之該接合層。
  17. 如申請專利範圍第15項所述之方法，進一步包含在該模塑元件晶圓下方形成多層式重佈結構，其中：該多層式重佈結構包含複數凸塊結構，該複數凸塊結構位於該多層式重佈結構之底表面上，以及該多層式重佈結構內之重佈互連；且經由該多層式重佈結構內之該重佈互連及該對應模塑元件晶粒之該後段製程部內之連接層，將各該凸塊結構電性耦接至對應模塑元件晶粒之一個主動層。
  18. 如申請專利範圍第15項所述之方法，進一步包含：將該模塑元件晶圓切割成複數單個模塑元件晶粒；將第二模塑化合物施用於該複數單個模塑元件晶粒周圍及上方以提供雙重模塑元件晶圓，其中：該第二模塑化合物封裝各該單個模塑元件晶粒之頂表面及側表面，而各該單個模塑元件晶粒之底表面則暴露在外；以及該雙重模塑元件晶圓之底表面為各該單個模塑元件晶粒之該底表面與該第二模塑化合物之底表面的結合；以及在該雙重模塑元件晶圓下方形成多層式重佈結構，其中：該多層式重佈結構包含複數凸塊結構，該複數凸塊結構位於該多層式重佈結構之底表面上，以及該多層式重佈結構內之重佈互連；以及經由該多層式重佈結構內之該重佈互連及該對應單個模塑元件晶粒之該後段製程部內之連接層，將各該凸塊結構電性耦接至對應單個模塑元件晶粒之一個主動層。
  19. 如專利申請範圍第15項所述之方法，其中該前導晶圓進一步包含複數單個緩衝結構，其中：各該單個緩衝結構位於該矽處理基板與對應單個介面層之間；各該單個緩衝結構係以具有垂直梯度鍺濃度之SiGe形成；且各該單個緩衝結構內之該垂直梯度鍺濃度從該矽處理基板至該對應單個介面層增加。
  20. 如申請專利範圍第19項所述之方法，進一步包含在移除該矽處理基板之後且在施用該第一模塑化合物之前移除各該單個緩衝結構及各該單個介面層。
  21. 如申請專利範圍第20項所述之方法，其中在施用該第一模塑化合物之後各該元件區域之該主動層接觸該第一模塑化合物。
  22. 如申請專利範圍第20項所述之方法，進一步包含：在移除各該單個緩衝結構及各該單個介面層之後，且在施用該第一模塑化合物之前，將鈍化層施用於各該元件區域之該主動層上方，其中：該鈍化層係以二氧化矽、氮化矽、或兩者之組合形成；且各鈍化層在施用該第一模塑化合物之後接觸該第一模塑化合物。
  23. 如申請專利範圍第15項所述之方法，其中提供該前導晶圓包含：提供起始晶圓，其包括共同應變矽磊晶層、位於該共同應變矽磊晶層上方之共同介面層、以及位於該共同介面層上方之該矽處理基板，其中：該共同介面層係以具有大於15%之均勻鍺濃度之SiGe形成，其中該共同介面層不受該矽處理基板應變，且其晶格常數在300 K溫度下大於5.461；以及該共同應變矽磊晶層中之矽晶格常數受該共同介面層應變，且在300 K溫度下大於5.461；以及執行互補式金屬氧化物半導體(CMOS)程序以提供該前導晶圓，其中：該絕緣段延伸通過該共同應變矽磊晶層及該共同介面層，並延伸進入該矽處理基板，使得該共同介面層分隔成該複數單個介面層，且該共同應變矽磊晶層分隔成複數單個應變矽磊晶層；該複數元件區域之各主動層係以對應應變矽磊晶層形成；以及各該單個介面層位於對應主動層之頂表面上方，且該矽處理基板位於該複數單個介面層上方。
  24. 如申請專利範圍第23項所述之方法，其中該起始晶圓進一步包 括介於該矽處理基板與該共同介面層之間之共同緩衝結構，其中：該共同介面層內之該鍺濃度係均勻的；該共同緩衝結構係以具有垂直梯度鍺濃度之SiGe形成；且該共同緩衝結構內之該垂直梯度鍺濃度從該矽處理基板至該共同介面層增加。
  25. 如申請專利範圍第24項所述之方法，其中：該絕緣段延伸通過該共同應變矽磊晶層、該共同介面層、該共同緩衝結構，並延伸進入該矽處理基板，使得該共同緩衝結構分隔成該複數單個緩衝結構，該共同介面層分隔成該複數單個介面層，且該共同應變矽磊晶層分隔成該複數單個應變矽磊晶層；且各該單個緩衝結構位於對應介面層上方，且該矽處理基板直接位於該複數單個緩衝結構上方。
  26. 如申請專利範圍第15項所述之方法，其中該絕緣段由二氧化矽構成。
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US12046570B2 (en) 2024-07-23
US11961813B2 (en) 2024-04-16
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