SG163445A1 - Method for manufacturing a low cost three dimensional stack package and resulting structures using through silicon vias and assemblies - Google Patents

Method for manufacturing a low cost three dimensional stack package and resulting structures using through silicon vias and assemblies

Info

Publication number
SG163445A1
SG163445A1 SG200900306-2A SG2009003062A SG163445A1 SG 163445 A1 SG163445 A1 SG 163445A1 SG 2009003062 A SG2009003062 A SG 2009003062A SG 163445 A1 SG163445 A1 SG 163445A1
Authority
SG
Singapore
Prior art keywords
silicon chip
face
assemblies
manufacturing
low cost
Prior art date
Application number
SG200900306-2A
Inventor
Kolan Ravi Kanth
Original Assignee
Kolan Ravi Kanth
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kolan Ravi Kanth filed Critical Kolan Ravi Kanth
Priority to SG200900306-2A priority Critical patent/SG163445A1/en
Priority to PCT/SG2009/000021 priority patent/WO2010080068A1/en
Publication of SG163445A1 publication Critical patent/SG163445A1/en

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    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06541Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
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    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2924/102Material of the semiconductor or solid state bodies
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    • H01L2924/181Encapsulation
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    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161Exposing the passive side of the semiconductor or solid-state body of a flip chip

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

A Wafer level stacked package , comprising a main silicon chip having first face and second face and having plurality of dielectric and metal trace patterns on first and second faces. The silicon chip having plurality of through silicon metal filled vias linking, the metal trace patterns of first and second faces of the main silicon chip. The silicon chip having plurality of bumps at the first face. The silicon chip having a bottom encapsulant member covering the first face and the bumps, with bump connections extended outside the encapsulant surface and with bottom encapsulant extending sideways and exactly equal to the size of the main silicon chip. FIG: 7
SG200900306-2A 2009-01-12 2009-01-12 Method for manufacturing a low cost three dimensional stack package and resulting structures using through silicon vias and assemblies SG163445A1 (en)

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SG200900306-2A SG163445A1 (en) 2009-01-12 2009-01-12 Method for manufacturing a low cost three dimensional stack package and resulting structures using through silicon vias and assemblies
PCT/SG2009/000021 WO2010080068A1 (en) 2009-01-12 2009-01-12 Method for manufacturing a low cost three dimensional stack package and resulting structures using through silicon vias and assemblies

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