KR970067805A - 반도체장치 및 그 제조방법 - Google Patents

반도체장치 및 그 제조방법 Download PDF

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Publication number
KR970067805A
KR970067805A KR1019970009768A KR19970009768A KR970067805A KR 970067805 A KR970067805 A KR 970067805A KR 1019970009768 A KR1019970009768 A KR 1019970009768A KR 19970009768 A KR19970009768 A KR 19970009768A KR 970067805 A KR970067805 A KR 970067805A
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South Korea
Prior art keywords
wiring
wiring board
semiconductor chip
integrated circuit
circuit device
Prior art date
Application number
KR1019970009768A
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English (en)
Other versions
KR100559276B1 (ko
Inventor
쥬이치 미야자키
유키하루 아키야마
마사노리 시바모토
도모아키 구다이시
이치로 안죠
구니히코 니시
아사오 니시무라
히데키 다나카
료스케 기모토
구니히로 츠보사키
아키오 하세베
Original Assignee
가나이 츠토무
히다치세사쿠쇼 주식회사
요네야마 사다오
히다치마이컴시스템 주식회사
스트키 진이치로
히다치초엘에스아이 엔지니어링 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 가나이 츠토무, 히다치세사쿠쇼 주식회사, 요네야마 사다오, 히다치마이컴시스템 주식회사, 스트키 진이치로, 히다치초엘에스아이 엔지니어링 주식회사 filed Critical 가나이 츠토무
Publication of KR970067805A publication Critical patent/KR970067805A/ko
Priority to KR1020050129904A priority Critical patent/KR100576668B1/ko
Priority to KR1020050129890A priority patent/KR100659635B1/ko
Priority to KR1020050129903A priority patent/KR100661424B1/ko
Priority to KR1020050129900A priority patent/KR100659634B1/ko
Application granted granted Critical
Publication of KR100559276B1 publication Critical patent/KR100559276B1/ko

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    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49169—Assembling electrical component directly to terminal or elongated conductor

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Abstract

반도체 집적회로장치에 관한 것으로서, 탄성구조체를 고정밀도로 안정하게 배선기판에 탑재하고 반도체칩의 접착공정을 안정하게 하여 제조효율이 높은 조립을 실행할 수 있도록 하기 위해서, 볼 그리드 어레이형식의 반도체 패키지로서 본딩패드가 형성된 반도체칩, 반도체칩에 접착되는 일래스토머, 일래스토머에 접착되고 반도체칩의 본딩패드에 한쪽끝이 접속되는 배선이 형성된 플렉시블 배선기판, 플렉시블 배선기판의 주면상에 형성되는 땜납레지스트 및 다른쪽 끝에 접속되는 땜납범프로 구성하였다. 이러한 구성에 의해 탄성구조체를 보다 고정밀도로 안정하게 공극없이 베이스재에 탑재할 수 있고, 또 탄성구조체의 치수형상이 안정하므로 반도체칩의 접착공정도 안정하고 제조효율이 높은 조립을 실행하는 것이 가능하게 된다는 효과가 얻어진다.

Description

반도체장치 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 실시형태 1인 반도체 집적회로장치를 도시한 평면도, 제2도는 본 발명의 실시형태 1에 있어서 도1의A-A´ 절단선에 있어서의 단면도, 제3도는 본 발명의 실시형태 1에 있어서의 반도체 집적회로 장치의 실장기판으로서의 실장상태를 도시한 평면도, 제4도는 본 발명의 실시형태 1에 있어서의 반도체 집적회로 장치의 실장기판으로서의 실장상태를 도시한 단면도, 제5도는 본 발명의 실시형태 1에 있어서의 반도체 집적회로 장치의 실장기판으로서의 실장상태를 도시한 흐름도.

Claims (20)

  1. 반도체칩의 주면상에 탄성구조체를 거쳐서 배선기판을 마련하고, 상기 배선기판의 배선의 한쪽끝측을 상기 반도체칩의 주면상의 외부단자와 전기적으로 접속시키고 또한 상기 배선기판의 배선의 다른쪽끝단을 범프 전극과 전기적으로 접속시켜서 이루어지는 반도체 집적회로장치로서, 상기 배선기판은 절연테이프와 그 주면상에 형성된 배선을 갖고, 상기 절연테이프측에 상기 탄성구조체를 배치시키고 또한 상기 배선측에 범프전극이 형성되는 것을 특징으로 하는 반도체 집적회로장치.
  2. 제1항에 있어서, 상기 반도체칩의 외부단자는 상기 반도체칩의 중앙부에 배치되는 것을 특징으로 하는 반도체 집적회로장치.
  3. 제1항에 있어서, 상기 범프전극은 상기 반도체칩의 외주보다 내측의 영역에 배치되는 것을 특징으로 하는 반도체 집적회로장치.
  4. 제1항에 있어서, 상기 반도체칩의 외부단자는 상기 반도체칩의 주변부에 배치되는 것을 특징으로 하는 반도체 집적회로장치.
  5. 반도체칩의 주면상에 탄성구조체를 거쳐서 배선기판을 마련하고, 상기 배선기판의 배선의 한쪽끝부를 상기 반도체칩의 주면상의 외부단자와 전기적으로 접속시키고 또한 상기 배선기판의 배선의 다른쪽끝부를 범프 전극과 전기적으로 접속시켜서 이루어지는 반도체 집적회로장치로서, 상기 반도체 집적회로장치의 외주부측에 있어서의 상기 배선기판의 기판베이스재의 끝부와 상기 탄성구조체의 끝부의 거리를 Ｍ1로 하는 경우에
    Ｍ1＞Ｍ2＞０
    의 관계를 만족시키는 범위에서 상기 Ｍ2와 상기 Ｍ1을 설정하는 것을 특징으로 하는 반도체 집적회로장치.
  6. 반도체칩의 주면상에 탄성구조체를 거쳐서 배선기판을 마련하고, 상기 배선기판의 배선의 한쪽끝부를 상기 반도체칩의 주면상의 외부단자와 전기적으로 접속시키고 또한 상기 배선기판의 배선의 다른쪽끝부를 범프 전극과 전기적으로 접속시켜서 이루어지는 반도체 집적회로장치로서, 상기 배선기판의 배선의 다른쪽끝부를 범프전극과 전기적으로 접속시켜서 이루어지는 반도체 집적회로장치로서, 상기 배선기판의 배선은 상기 배선기판의 기판베이스재와의 고정부분과 상기 반도체칩의 외부단자에 접속되는 선단부분을 적어도 상기 배선의 폭 이상 변위된 형상으로 형성하는 것을 특징으로 하는 반도체 집적회로장치.
  7. 반도체칩의 주면상에 탄성구조체를 거쳐서 배선기판을 마련하고, 상기 배선기판의 배선의 한쪽끝부를 상기 반도체칩의 주면상의 외부단자와 전기적으로 접속시키고 또한 상기 배선기판의 배선의 다른쪽끝부를 범프 전극과 전기적으로 접속시켜서 이루어지는 반도체 집적회로장치로서, 상기 배선기판의 배선의 다른쪽끝부를 범프전극과 전기적으로 접속시켜서 이루어지는 반도체 집적회로장치로서, 상기 배선기판의 배선은 상기 배선기판의 기판베이스재에 한쪽이 고정되고 다른쪽이 자유단에 형성되어 있는 것을 특징으로 하는 반도체 집적회로장치.
  8. 반도체칩의 주면상에 탄성구조체를 거쳐서 배선기판을 마련하고, 상기 배선기판의 배선의 한쪽끝부를 상기 반도체칩의 주면상의 외부단자와 전기적으로 접속시키고 또한 상기 배선기판의 배선의 다른쪽끝부를 범프 전극과 전기적으로 접속시켜서 이루어지는 반도체 집적회로장치로서, 상기 배선기판의 배선의 다른쪽끝부를 범프전극과 전기적으로 접속시켜서 이루어지는 반도체 집적회로장치로서, 상기 반도체칩상의 표면보호막의 개구부의 끝부는 적어도 본딩공구를 내려뜨리는 측에 있어서 상기 본딩공구를 내려뜨렸을 때 상기 배선이 상기 표면 보호막에 간섭하지 않는 범위의 치수로 설정되어 있는 것을 특징으로 하는 반도체 집적회로장치.
  9. 반도체칩의 주면상에 탄성구조체를 거쳐서 배선기판을 마련하고, 상기 배선기판의 배선의 한쪽끝부를 상기 반도체칩의 주면상의 외부단자와 전기적으로 접속시키고 또한 상기 배선기판의 배선의 다른쪽끝부를 랜드부를 범프전극과 전기적으로 접속시켜서 이루어지는 반도체 집적회로장치로서,상기 배선기판의 배선은 상기 배선의 노치종단측에 있어서의 배선부분의 유효면적을 크게 형성시키고 있는 것을 특징으로 하는 반도체 집적회로장치.
  10. 제9항에 있어서, 상기 노치종단측의 배선부분은 대향하는 배선의 랜드부에 연결되거나 배선의 빈영역으로 종방향 또는 횡방향으로 연장시키거나 또는 인접하는 배선끼리를 연결시켜서 이루어지는 것을 특징으로 하는 반도체 집적회로장치.
  11. 반도체칩의 주면상에 탄성구조체를 거쳐서 배선기판을 마련하고, 상기 배선기판의 배선의 한쪽끝부를 상기 반도체칩의 주면상의 외부단자와 전기적으로 접속시키고 또한 상기 배선기판의 배선의 다른쪽끝부를 범프 전극과 전기적으로 접속시켜서 이루어지는 반도체 집적회로장치로서, 상기 탄성구조체는 상기 반도체칩의 외형치수에 비해서 적어도 상기 탄성구조체에 형성되는 외주 돌기폭 이상으로 전체 둘레에 걸쳐서 큰 범위로 형성되어 있는 것을 특징으로 하는 반도체 집적회로장치.
  12. 반도체칩의 주면상에 탄성구조체를 거쳐서 배선기판을 마련하고, 상기 배선기판의 배선의 한쪽끝부를 상기 반도체칩의 주면상의 외부단자와 전기적으로 접속시키고 또한 상기 배선기판의 배선의 다른쪽끝부를 범프 전극과 전기적으로 접속시켜서 이루어지는 반도체 집적회로장치로서, 상기 탄성구조체를 상기 반도체칩의 외부 단자상에 접착하지 않도록 분할해서 형성하는 경우에 상기 분할된 탄성구조체의 대향하는 공간의 각각의 끝부를 홈형상으로 형성하는 것을 특징으로 하는 반도체 집적회로장치.
  13. 제12항에 있어서, 상기 분할된 탄성구체의 대향하는 공간의 각각의 끝부의 홈에는 봉지공정시에 미리 본지재 흐름방지용 댐을 형성하는 것을 특징으로 하는 반도체 집적회로장치.
  14. 반도체칩의 주면상에 탄성구조체를 거쳐서 배선기판을 마련하고, 상기 배선기판의 배선의 한쪽끝부를 상기 반도체칩의 주면상의 외부단자와 전기적으로 접속시키고 또한 상기 배선기판의 배선의 다른쪽끝부를 범프 전극과 전기적으로 접속시켜서 이루어지는 반도체 집적회로장치로서, 상기 배선기판의 배선구조는 상기 배선의 폭치수를 상기 배선기판의 기판베이스재와의 끝부에서 배선선단쪽으로 점차 가늘게 하고, 상기 기판베이스재의 끝부에 있어서 발생하는 구부림 σ0에 대해서 상기 기판베이스재의 끝부와 배선선단부의 중간에서 발생하는 최대응력 σ1로 했을 때의 구부림 응력비 α가
    α= σ1/σ0
    으로 나타내어지는 경우에 상기 구부림 응력비 α가 1.2∼1.5로 되도록 상기 배선의 치수 및 형상을 설정시켜서 이루어지는 것을 특징으로 하는 반도체 집적회로장치.
  15. 제14항에 있어서, 상기 배선기판의 배선구조는 상기 배선의 폭치수를 상기 배선기판의 기판베이스재의 끝부에서 배선선단쪽으로 점차 가늘게 하고, 소정의 위치에서 일정한 폭치수로 되도록 형성하고, 테이퍼길이를 L1, 배선길이를 L2, 테이퍼폭을 b1, 배선폭을 b2로 했을 때의 구부림 응력비 α가
    α= b1 × (L2 - L1)/ (b2×L2)로 나타내어지는 경우에 상기 구부림 응력비 α가 1.2∼1.5로 되도록 상기 배선의 치수 및 형상을 설정시켜서 이루어지는 것을 특징으로 하는 반도체 집적회로장치.
  16. 반도체칩의 주면상에 탄성구조체를 거쳐서 배선기판을 마련하고, 상기 배선기판의 배선의 한쪽끝부를 휘어진 상태로 상기 반도체칩의 주면상의 외부단자와 전기적으로 접속시키고 또한 상기 배선기판의 배선의 다른쪽끝인 랜드부를 범프전극과 전기적으로 접속시켜서 이루어지는 반도체 집적회로장치로서,상기 배선기판의 배선구조는 Cu를 심재로 해서 표면에 Au도금을 실시해서 이루어지는 것을 특징으로 하는 반도체 집적회로장치.
  17. 반도체칩의 주면상에 탄성구조체를 거쳐서 배선기판을 마련하고, 상기 배선기판의 배선의 한쪽끝부를 상기 반도체칩의 주면상의 외부단자와 전기적으로 접속시키고 또한 상기 배선기판의 배선의 다른쪽끝부를 범프 전극과 전기적으로 접속시켜서 이루어지는 반도체 집적회로장치로서, 상기 배선기판은 절연테이프와 그 주면에 형성된 배선을 갖고, 상기 배선측에 절연막을 형성시키고 상기 절연막상에 상기 탄성구조체를 배치시키는 것을 특징으로 하는 반도체 집적회로장치.
  18. 기판베이스재상에 배선이 형성된 배선기판의 이면상에 탄성구조체를 형성하는 공정, 상기 탄성구조체의 이면상에 상기 배선의 리이드부와 반도체칩의 외부단자의 상대위치가 일치하도록 상기 반도체칩을 접착하는 공정, 상기 배선의 리이드부를 상기 반도체칩의 외부단자에 접속하는 공정, 상기 반도체칩의 외부단자와 상기 배선의 접속부분을 수지봉지하는 공정, 상기 반도체칩의 외부단자에 접속하는 공정, 상기 반도체칩의 외부단자와 상기 배선의 접속부분을 수지봉지하는 공정, 상기 반도체칩의 외주보다 약간 외측에 있어서 상기 배선기판의 기판베이스재를 절단하는 공정, 상기 배선의 주면상에 절연막을 형성하는 공정, 상기 절연막의 상기 배선의 랜드부와 범프전극이 접합되는 위치에 개구부를 형성하는 공정 및 상기 개구부를 거쳐서 상기 배선의 랜드부에 접합시켜서 범프전극을 형성하는 공정을 포함하는 것을 특징으로 하는 반도체 집적회로장치의 제조방법.
  19. 제18항에 있어서, 상기 절연막의 개구부는 상기 절연막을 형성하는 공정에 있어서, 상기 절연막의 재료의 도포범위를 규정하는 것에 의해 형성하는 것을 특징으로 하는 반도체 집적회로장치의 제조방법.
  20. 제18항에 있어서, 상기 절연막의 두께는 상기 절연막을 형성하는 공정에 있어서, 상기 절연막의 재료의 도포조건을 규정하는 것에 의해 설정하는 것을 특징으로 하는 반도체 집적회로장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
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