KR20120062714A - 메모리 모듈 상의 분배된 바이트-와이즈 버퍼들을 이용하는 시스템 및 방법 - Google Patents
메모리 모듈 상의 분배된 바이트-와이즈 버퍼들을 이용하는 시스템 및 방법 Download PDFInfo
- Publication number
- KR20120062714A KR20120062714A KR1020127004038A KR20127004038A KR20120062714A KR 20120062714 A KR20120062714 A KR 20120062714A KR 1020127004038 A KR1020127004038 A KR 1020127004038A KR 20127004038 A KR20127004038 A KR 20127004038A KR 20120062714 A KR20120062714 A KR 20120062714A
- Authority
- KR
- South Korea
- Prior art keywords
- memory
- data transmission
- memory devices
- data
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/066—Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
- Memory System (AREA)
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/504,131 | 2009-07-16 | ||
| US12/504,131 US8417870B2 (en) | 2009-07-16 | 2009-07-16 | System and method of increasing addressable memory space on a memory board |
| US12/761,179 US8516185B2 (en) | 2009-07-16 | 2010-04-15 | System and method utilizing distributed byte-wise buffers on a memory module |
| US12/761,179 | 2010-04-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20120062714A true KR20120062714A (ko) | 2012-06-14 |
Family
ID=42610062
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020127004038A Abandoned KR20120062714A (ko) | 2009-07-16 | 2010-07-01 | 메모리 모듈 상의 분배된 바이트-와이즈 버퍼들을 이용하는 시스템 및 방법 |
Country Status (10)
| Country | Link |
|---|---|
| US (5) | US8516185B2 (enExample) |
| EP (3) | EP2454735B1 (enExample) |
| JP (1) | JP2012533793A (enExample) |
| KR (1) | KR20120062714A (enExample) |
| CN (2) | CN105161126B (enExample) |
| CZ (1) | CZ31172U1 (enExample) |
| DE (1) | DE202010018501U1 (enExample) |
| PL (2) | PL2454735T3 (enExample) |
| TW (2) | TWI446167B (enExample) |
| WO (1) | WO2011008580A1 (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9812186B2 (en) | 2013-04-27 | 2017-11-07 | Huawei Technologies Co., Ltd. | Reducing latency in an expanded memory system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US9812186B2 (en) | 2013-04-27 | 2017-11-07 | Huawei Technologies Co., Ltd. | Reducing latency in an expanded memory system |
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| EP3404660B1 (en) | 2021-06-23 |
| US8516185B2 (en) | 2013-08-20 |
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| US20170337125A1 (en) | 2017-11-23 |
| CN105161126A (zh) | 2015-12-16 |
| US20140040568A1 (en) | 2014-02-06 |
| US10949339B2 (en) | 2021-03-16 |
| CN102576565A (zh) | 2012-07-11 |
| US20240394177A1 (en) | 2024-11-28 |
| US9606907B2 (en) | 2017-03-28 |
| TWI446167B (zh) | 2014-07-21 |
| JP2012533793A (ja) | 2012-12-27 |
| PL3404660T3 (pl) | 2022-01-03 |
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