WO1994007242A1

WO1994007242A1 - High speed redundant memory

Info

Publication number: WO1994007242A1
Application number: PCT/US1993/004231
Authority: WO
Inventors: Saroj Pathak; Glen A. Rosendale; James E. Payne
Original assignee: Atmel Corporation
Priority date: 1992-09-21
Filing date: 1993-05-05
Publication date: 1994-03-31

Abstract

A memory circuit (10) in which redundant cell groups are located in a second memory bank (14; 88) to replace any defective cell groups present in a first memory bank (12; 86). Each bank has its own address decoders (16, 18; 90, 92, 94, 96) and read/write circuits. When an address corresponding to a defective cell group is received, the first bank is enabled as usual, while a fast logic circuit (40; 100) enables the second bank, so that both banks are simultaneously enabled. A signal (32; 102) is transmitted by the logic circuit to an output selector (20; 98) where data from a redundant cell group in the second bank is selected for output (34; 84). The time needed to detect an address corresponding to a defective cell group, is masked by the longer time required by the decoders and sense amplifiers of the respective banks.

Description

Description High Speed Redundant Memory

Technical Field The invention relates to monolithic integrated memory circuits, particularly those adapted for reliable operation through the use of redundant memory cells.

Background Art Many of today's large-scale ("LSI") and very-large-scale ("VLSI") integrated circuit memories would be rejected during manufacture if the presence of a few de¬ fective memory cells could not be dealt with in an effective manner. One common solution is to provide spare memory cells and some means of selecting these to replace the de¬ fective cells. U.S. Pat. No's 4,947,375 and 4,908,798 are typical examples. In such an arrangement, post-production wafer testing is used to identify the addresses of defective cells. At the factory, these addresses are programmed into a cell selection logic circuit, typically independent of the normal address decoders.

During normal operation this independent selection circuit compares a received memory address with the factory programmed addresses of the previously identified groups of defective cells. Typically, when a defective group of cells is addressed, signals are generated by the circuit to dese¬ lect the defective cells and to substitute a group of spare replacement cells. In this way a memory having such a re¬ dundant architecture can operate reliably despite the presence of a few defective memory cells.

The prior art typically places the spare memory cells in one of two locations, either in a separate region of the same array as the defective cells (U.S. Pat. No's 4,947,375, 5,058,069, 5,058,070 and 5,058,071 are examples of this approach) , or in a separate array dedicated for that purpose (U.S. Pat. No's 4,908,798 and 5,033,024 are examples of this latter approach) . These devices, while quite valu¬ able in saving an otherwise defective chip, sacrifice speed because the delay resulting from address decoding, redundant group selection, and defective normal group deselection, is added to other delays typically associated with the speed of memory circuits. The deselection time in particular results in a slowing of memory speed.

Two recent U.S. patents have attacked the speed problem in interesting ways. Kondo, in U.S. Pat. No. 4,918,662, teaches a redundant structure in which the spare memory cells are placed in the same array and use the same sense amplifiers as the normal memory cells. Kondo recog¬ nizes the slowing effect of the stray capacitance of an overly long normal cell group selection-inhibit-signal. Kondo partitions this length among many shorter inhibit sig¬ nal paths, thereby reducing stray capacitance and reducing the "in line" delays. In a completely different approach, Busch et al., in U.S. Pat. No. 4,992,984, disclose a memory module made up of a plurality of identical memory "chips," each having several arrays of storage elements. Factory testing identifies arrays within each chip which are good and those arrays which contain defects. A memory address is applied to all chips in common. A control circuit inside each chip responds to previously programmed addresses corre¬ sponding to known defective arrays. The control circuit in the chip having the defective array and the control circuit in the chip having the replacement array both respond to an address corresponding to a known defective array. Both ar¬ rays are addressed, but the output data of the replacement array is enabled, while the output data of the defective array is disabled.

Summary of the Invention

The invention is a monolithic integrated circuit memory which contains at least two banks of normal data cells. These cells, which can be SRAMs, DRAMs, PROMs, EPROMs, EEPROMs or flash cells, are arranged in rows and columns, and a few of the normal data cells may be defec¬ tive. Each bank has its own address decoders and the banks can be simultaneously enabled. The integrated circuit memo¬ ry has address lines for receiving a memory address and at least one data output line. The address space is parti¬ tioned among the memory banks so that normally only one bank responds to a given memory address.

Each bank has redundant rows or columns which con¬ tain one or more memory elements which are programmed with data in a defective element of another bank. In accord with the invention, an entire row or column of one bank is sub- stituted for the row or column containing the defective ele¬ ment of another bank. The redundant row or column is read by the same sense amplifier which reads the rows or columns of the non-redundant elements in the memory bank.

A programmable logic device is programmed to re- ceive all memory address signals and to respond to addresses with a bad memory element. Rather than deselect a bad row or column in the first memory bank, the logic device selects the redundant row or column in the second memory bank and then directs the sense amplifier output from the redundant row or column as the memory output. An output from the sense amplifier with the defective element is available, but is not selected. A selector circuit, operating as a multi¬ plexer, is connected to both memory banks and responds to the logic device for selection of an output from an appro- priate memory bank. In the case of an address for a non- defective cell in a first memory bank, the output from a sense amplifier associated with the first bank is selected. In the case of an address for a defective cell in the first memory bank, the output from a sense amplifier associated with the second bank is selected.

The logic circuit operates at a speed faster than memory bank decoders and sense amplifiers combined so that redundant row or column data is available faster than normal data. Since the defective row or column is not deselected, only ignored by the selector circuit, the delay normally present with deselection of a defective row or column is not present and memory output data is delayed by only an amount required by the logic circuit and the selector switch. Since a switch can be very fast, the total delay of the log¬ ic device and the selector can be comparable, or faster, than the speed of a normal decoder. In this way, the use of a redundant memory element is transparent with respect to time delay and no time delay is experienced from deselection of a row or column containing a defective element.

The key ingredients of the present invention in¬ clude placing a backup row or column for a defective memory bank address into a different memory bank, simultaneously selecting both the defective and backup row or column, and selecting the outputs of the memory bank containing the backup row or column when a defective element is addressed. A fast logic device and a fast selector switch is used, com¬ pared to the speed of an address decoder. In a read-only memory application, the correct data must exist in the back¬ up row so that when both defective and redundant rows are selected, the correct data will be available at the sense amplifiers of the bank containing the redundant row. When writing is done, the data is written into the backup rows or columns, and later will be retrieved from the backup row or column.

Brief Description of the Drawings

Fig. 1 is a schematic block diagram showing the present invention in which redundant rows may be substitut¬ ed.

Fig. 2 is pictorial version of Fig. 1 showing se¬ lection of a redundant row.

Fig. 3 is a schematic block diagram showing the present invention in which redundant row or columns may be substituted.

Best Mode for Carrying Out the Invention

With reference to Fig. 1 there is shown a high speed redundant memory 10 capable of reliable operation in the presence of a small number of defective memory cells.

The memory contains first and second memory banks,

12 and 14, each bank includes memory elements which are ar- ranged in rows and columns. Each memory bank has its own row decoder 16, 18 and each column has its own sense ampli¬ fiers, 26, 30. Selector 20 is used to select the output of either first bank sense amplifiers along lines 36 or second bank sense amplifiers along lines 38 depending upon the lev¬ el of a select signal 32. Selector 20 provides the selected data as memory output data on lines 34.

Each bank includes at least one redundant row of memory elements which share the sense amplifiers for the bank but are not selectable by the row decoder for the bank. Redundant_Row_0 is shown in the first bank 12 and is select¬ able by logic 40 using a signal carried on line 42. Redun- dant_Row_l is shown in the second bank 14 and is selectable by a signal carried on line 44. The normal rows of each memory bank are shown as

Row_0 through Row_511 for first bank 12 and Row_512 through Row_1023 for second bank 14. The normal rows of first bank 12 are selectable by row decoder 16 output signals carried on lines 46, while the normal rows of second bank 14 are selectable by row decoder 18 output signals carried on lines

48. Row select lines 46, 48 are connected to the individual rows of the respective memory banks, generally indicated by the arrows.

Redundant memory 10 receives memory address sig- nals on lines 50. Appropriate subsets of these memory sig¬ nals are connected as inputs to row decoders 16, 18.

A factory programmable logic device 40 contains a map of bad cells derived from factory probe testing. The map lists the addresses of the bad cells and a corresponding replacement row. The logic circuit is made of non-volatile memory devices, such as PROMs, EPROMs, EEPROMs or flash cells. The speed of logic circuit 40 is about 2 nanosec¬ onds, low compared to the speed of address decoder 16 or 18 which is about 7 nanoseconds. The address decoder 20 has a speed of several nanoseconds. The combined speed of the logic circuit is comparable or less than the speed of an address decoder and associated sense amplifier. When the logic circuit 40 receives memory address signals from lines 50 for bad cells it produces a predetermined signal carried on lines 32, 42 and 44.

In operation, a first predetermined memory address signal corresponding to the address of a defective row cell in second bank 14 is decoded by logic circuit 40 to generate a signal carried on line 42 to select Redundant_Row_0 in first bank 12. This occurs because logic circuit 40 has been programmed with the address of the bad element and re¬ sponds to the bad address. The logic circuit 40 also gener- ates a signal carried on line 32 to cause selector 20 to select the output of the sense amplifiers 26 of first bank 12 for presentation on memory data output lines 34.

Another operational example is as follows. A sec¬ ond predetermined memory address signal corresponding to the address of a defective row cell in first bank 12 is decoded by logic circuit 40 to generate a signal carried on line 44 to select Redundant_Row_l in second bank 14. The same predetermined memory signal is decoded by logic circuit 40 to generate a signal carried on line 32 to cause selector 20 to select the output of the sense amplifiers 30 of second bank 14 for presentation on memory data output lines 34.

Fig. 2 depicts the embodiment shown in Fig. 1 in a pictorial fashion to emphasize the basic operation of the invention. In this example, a memory address is received on lines 50 which corresponds to a cell in Defective_Row_K in first bank 12. Defective_Row_K is shown being selected by an output of row decoder 16. Programmable logic circuit 40 receives and responds to the memory address by generating a row selection signal on line 44 connected to and selecting Redundant_Row_l in second bank 14 at the same time Defec- tive_Row_K is being selected. The contents of each selected row is available at the outputs of the respective sense am¬ plifiers, 26, 30. The outputs of second bank sense amplifi¬ ers 30 are selected by selector 20 for output on lines 34 as the memory output data. Programmable logic circuit 40 gen¬ erates an output select signal on line 32 for this purpose. The row decoder 18 for second bank 14 has no active output signal because the normal rows in second bank 14 do not re- spond to addresses found the address space of first bank 12.

Fig. 3 depicts a high speed redundant memory 80 capable of reliable operation in the presence of a few bad cells in defective rows or columns. The memory has first and second memory banks, 86 and 88 respectively. Each bank may have bad cells which define a defective row or column and includes at least one redundant row, depicted as Redun- dant_Row_0 and Redundant_Row_l, and one redundant column, 116 and 118. Each bank has its own row decoder, 90 and 94, and its own column decoder, 92 and 96. A factory programma¬ ble logic circuit 100 receives a memory address on lines 82 and generates select signals 102, 104 and 106 in response to programmed addresses. All columns in each bank share a com¬ mon sense amplifier, 108 and 110. Select signal 102 is used by selector 98 to select the output of one sense amplifier as the single output bit Data_Out on line 84. Select signal 104 is made active in response to the programmed address of a known defective row or column and is applied through pro¬ grammable switch 112 to select either Redundant_Row_0 or redundant column 116. Similarly, select signal 106 may be programmably connected via switch 114 to select Redun- dant_Row_l or redundant column 118. The normal rows and columns or each bank partition the memory address space such that only a single row and column in one bank will be se- lected at one time.

When the address of a known defective cell group is received on lines 82, both memory banks are enabled and the defective row or column is selected by its address de¬ coders producing a defective output at the bank sense ampli- fier. Simultaneously, select signal 104 or 106 selects a redundant row or column and a good output is available at the sense amplifier of the bank containing the redundant cell group. Select signal 102 is made active in response to the memory address to select the good sense amplifier output and connect the good output to line 84.

Without loss of generality, the structures depicted in Figs. 1, 2 and 3 can be extended, by means well known to those having ordinary skill in the art, to include a redundant memory having both read and write capability. Other embodiments are contemplated. The backup for bank A can be located in bank B, the backup for B locat¬ ed in C, for C in D, and for D in A, so long as both the bank of the defective row and its backup bank are simultane¬ ously enabled and the output of the backup bank selected. Each memory bank may be a portion of a chip, a chip or a laser module, such as a SIMM or SIP.

Claims

1. A high-speed redundant memory, comprising: a memory having first and second banks of storage cells, each bank having its own address decoders and at least one sense amplifier, each bank having redundant memor cell groups which are not selectable by the address decod¬ ers; logic circuit means for receiving and decoding a memory address which corresponds with a defective cell in one bank and for generating a logic signal in response thereto having an address which corresponds to a redundant cell group in the other bank; switch means responsive to the logic signal to enable said other bank, said switch means connected to the first and second banks for using the logic signal to select an output signal of a sense amplifier of the other bank as the memory output signal.

2. The redundant memory of claim 1 wherein the redundant memory cell group comprises at least one row.

3. The redundant memory of claim 1 wherein the redundant memory cell group comprises at least one column.

4. The redundant memory of claim 1 wherein the redundant cell group has a redundant sense amplifier.

5. The redundant memory of claim 1 wherein the logic cir¬ cuit means comprises non-volatile memory cells.

6. The redundant memory of claim 1 wherein the redundant memory cell groups include at least one redundant row and at least one redundant column. 7. The redundant memory of claim 1 wherein said storage cells are selected from the group of SRAM, DRAM, PROM, EPROM, EEPROM or flash memory cells.

8. The redundant memory of claim 1 comprising pairs of memory banks such that the redundant storage cell groups of each bank of a pair serve as substitutes for defective cells in the other bank of the pair, and the decoding of a memory address corresponding to a defective cell group in either bank of the pair results in at least both banks of the pair being simultaneously enabled and wherein the output of the at least one sense amplifier of the bank having the selected replacement group is output by the memory as output data.

9. A high-speed redundant memory for operation in the presence of defective memory elements, comprising: a plurality of memory banks each with an array of memory elements with regular addresses and each array having its own address decoding means and having redundant elements with addresses whose contents may be read via each bank's associated sense amplifiers, logic means for recognizing the address of a de¬ fective memory element with a regular address in a first memory bank and for selecting a redundant element with an address in a second memory bank, and selecting outputs of the sense amplifiers of the second memory bank when the ad¬ dress of a defective memory element is recognized; and a selector means responsive to the logic means for outputting data from a redundant memory element in the sec- ond memory bank when an address of a defective memory ele¬ ment in the first memory bank is received and otherwise out¬ putting data from a memory element with an address in the first memory bank, said first and second memory banks simul¬ taneously enabled when an address of a defective memory ele- ment is received, the combined speed of the logic means be¬ ing faster than said decoder means and associated sense am¬ plifiers. 10. A method for addressing a redundant memory, comprising the steps of: providing a memory having first and second banks, each having its own address decoders and sense amplifiers and having redundant memory cells which are not selectable by the address decoders; receiving and decoding a memory address which cor¬ responds to a defective cell group in a first bank and gen¬ erating a signal in response thereto; while the first bank is enabled to read the defec¬ tive cell group, using the signal (i) to select a redundant cell group in the second bank, (ii) to simultaneously enable the second bank, and (iii) to select an output signal of the sense amplifiers of the second bank; and outputting the selected output signal of the sec¬ ond bank as memory output data.

AMENDED CLAIMS

[received by the International Bureau on 30 November 1993 (30.11.93) ; original claims 1, 9 and 10 amended ; new claim 11 added ; other claims unchanged ( 3 pages)]

1. A high-speed redundant memory, comprising: a memory having first and second banks of storage cells, each bank having an address decoder and at least one sense amplifier, each bank having redundant memory cell groups which are not selectable by the address decoder of a respective bank; logic circuit means for receiving and decoding a memory address which corresponds with a defective cell in one bank and for generating a logic signal in response thereto having an address which corresponds to a redun¬ dant cell group in the other bank, the logic circuit means operating at a speed faster than the address decod- er and sense amplifier combined of either of said first and second banks, switch means connected to the first and second banks and to the logic circuit means for using the logic signal of the logic circuit means to select an output signal of a sense amplifier of the other bank as the memory output signal.

5. The redundant memory of claim 1 wherein the logic circuit means comprises non-volatile memory cells.

6. The redundant memory of claim 1 wherein the redundant memory cell groups include at least one redundant row and at least one redundant column.

7. The redundant memory of claim 1 wherein said storage cells are selected from the group of SRAM, DRAM, PROM, EPROM, EEPROM or flash memory cells.

9. A high-speed redundant memory for operation in the presence of defective memory elements, comprising: a plurality of memory banks each with an array of memory elements with regular addresses and each array having an address decoding means and having redundant elements with addresses whose contents may be read via sense amplifiers associated with each bank, logic means for recognizing the address of a defective memory element with a regular address in a first memory bank and for selecting a redundant element with an address in a second memory bank, and a selector means responsive to the logic means for outputting data from a redundant memory element in the second memory bank when an address of a defective memory element in the first memory bank is received and otherwise outputting data from a memory element with an address in the first memory bank, said first and second memory banks simultaneously enabled when an address of a defective memory element is received, the speed of the logic means being faster than the combined speed of said address decoding means and associated sense amplifiers of any memory bank.

10. A method for addressing a redundant memory, compris¬ ing the steps of: addressing a memory having first and second banks, each having an address decoder and sense amplifi- ers and having redundant memory cells which are not se¬ lectable by the address decoders of a respective bank, addressing a logic circuit with a memory ad¬ dress which corresponds to a defective cell group in a first bank and generating a signal from the logic circuit in response thereto in a second amount of time less than the first amount of time; while the first bank is enabled to read the defective cell group, using the signal from the logic circuit (i) to select a redundant cell group in the sec- ond bank, (ii) to simultaneously enable the second bank and (iii) to select an output signal of the sense ampli¬ fiers of the second bank, and outputting the selected output signal of the second bank as memory output data.

11. The memory of claim 1 wherein said logic circuit means is a programmable logic device.

STATEMENT UNDER ARTICLE 19

In response to the International Search Report, claims 1, 9 and 10 were rewritten to point out that the logic means operates faster than the combined speed of the decoder and sense amplifiers, thereby distinguishing applicant's invention from the prior art cited in the International Search Report. In addition, a new claim 11 has been added to point out that the applicant achieves increased speed with a programmable logic device.

Applicant predicates patentability on the basis that the redundant memory element is transparent with respect to time delay in that no time delay is experienced from deselection of a row or column containing a defective element. Applicant achieves this result by having the logic circuit operate at a speed faster than both the memory decoders and sense amplifiers combined. This configuration makes available redundant row or column data faster than normal data.