KR100551641B1 - 반도체 장치의 제조 방법 및 반도체 장치 - Google Patents
반도체 장치의 제조 방법 및 반도체 장치 Download PDFInfo
- Publication number
- KR100551641B1 KR100551641B1 KR1020010081051A KR20010081051A KR100551641B1 KR 100551641 B1 KR100551641 B1 KR 100551641B1 KR 1020010081051 A KR1020010081051 A KR 1020010081051A KR 20010081051 A KR20010081051 A KR 20010081051A KR 100551641 B1 KR100551641 B1 KR 100551641B1
- Authority
- KR
- South Korea
- Prior art keywords
- substrate
- semiconductor device
- mold
- semiconductor chips
- conductor pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W42/00—Arrangements for protection of devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/65—Shapes or dispositions of interconnections
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/01—Manufacture or treatment
- H10W74/014—Manufacture or treatment using batch processing
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/01—Manufacture or treatment
- H10W74/016—Manufacture or treatment using moulds
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
- H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
- H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W46/00—Marks applied to devices, e.g. for alignment or identification
- H10W46/101—Marks applied to devices, e.g. for alignment or identification characterised by the type of information, e.g. logos or symbols
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W46/00—Marks applied to devices, e.g. for alignment or identification
- H10W46/601—Marks applied to devices, e.g. for alignment or identification for use after dicing
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/681—Shapes or dispositions thereof comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/0198—Manufacture or treatment batch processes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W99/00—Subject matter not provided for in other groups of this subclass
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Injection Moulding Of Plastics Or The Like (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000387825A JP3619773B2 (ja) | 2000-12-20 | 2000-12-20 | 半導体装置の製造方法 |
| JPJP-P-2000-00387825 | 2000-12-20 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20020050148A KR20020050148A (ko) | 2002-06-26 |
| KR100551641B1 true KR100551641B1 (ko) | 2006-02-14 |
Family
ID=18854673
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020010081051A Expired - Lifetime KR100551641B1 (ko) | 2000-12-20 | 2001-12-19 | 반도체 장치의 제조 방법 및 반도체 장치 |
Country Status (6)
| Country | Link |
|---|---|
| US (4) | US6596561B2 (https=) |
| JP (1) | JP3619773B2 (https=) |
| KR (1) | KR100551641B1 (https=) |
| CN (1) | CN1230882C (https=) |
| SG (1) | SG92821A1 (https=) |
| TW (1) | TW526598B (https=) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101101669B1 (ko) * | 2009-12-01 | 2011-12-30 | 삼성전기주식회사 | 전자부품 제조장치 및 전자부품 제조방법 |
Families Citing this family (92)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1154658A (ja) * | 1997-07-30 | 1999-02-26 | Hitachi Ltd | 半導体装置及びその製造方法並びにフレーム構造体 |
| WO2000007235A1 (fr) * | 1998-07-28 | 2000-02-10 | Seiko Epson Corporation | Dispositif a semi-conducteurs, procede de fabrication, module a semi-conducteurs, et dispositif electronique comprenant une carte imprimee et une carte equipee |
| JP4586316B2 (ja) * | 2001-08-21 | 2010-11-24 | 日本テキサス・インスツルメンツ株式会社 | 半導体チップ搭載用基板及びそれを用いた半導体装置 |
| JP3892703B2 (ja) * | 2001-10-19 | 2007-03-14 | 富士通株式会社 | 半導体基板用治具及びこれを用いた半導体装置の製造方法 |
| AU2003234812A1 (en) | 2002-06-05 | 2003-12-22 | Hitachi Ulsi Systems Co., Ltd. | Semiconductor device |
| JP3812500B2 (ja) * | 2002-06-20 | 2006-08-23 | セイコーエプソン株式会社 | 半導体装置とその製造方法、電気光学装置、電子機器 |
| JP2004055860A (ja) | 2002-07-22 | 2004-02-19 | Renesas Technology Corp | 半導体装置の製造方法 |
| EP1549472B1 (en) * | 2002-08-05 | 2008-09-24 | Nxp B.V. | Method for manufacturing a packaged semiconductor device, packaged semiconductor device obtained with such a method and metal carrier suitable for use in such a method |
| US7064426B2 (en) * | 2002-09-17 | 2006-06-20 | Chippac, Inc. | Semiconductor multi-package module having wire bond interconnect between stacked packages |
| US20040061213A1 (en) * | 2002-09-17 | 2004-04-01 | Chippac, Inc. | Semiconductor multi-package module having package stacked over die-up flip chip ball grid array package and having wire bond interconnect between stacked packages |
| US7034387B2 (en) * | 2003-04-04 | 2006-04-25 | Chippac, Inc. | Semiconductor multipackage module including processor and memory package assemblies |
| US7045887B2 (en) * | 2002-10-08 | 2006-05-16 | Chippac, Inc. | Semiconductor multi-package module having inverted second package stacked over die-up flip-chip ball grid array (BGA) package |
| JP4519398B2 (ja) * | 2002-11-26 | 2010-08-04 | Towa株式会社 | 樹脂封止方法及び半導体装置の製造方法 |
| JP4607429B2 (ja) * | 2003-03-25 | 2011-01-05 | 東レ・ダウコーニング株式会社 | 半導体装置の製造方法および半導体装置 |
| JP4796271B2 (ja) * | 2003-07-10 | 2011-10-19 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| US20050047106A1 (en) * | 2003-08-29 | 2005-03-03 | Martino Peter Miguel | Substrate reinforcing in an LGA package |
| TWI222186B (en) * | 2003-09-04 | 2004-10-11 | Advanced Semiconductor Eng | Method for manufacturing package substrate strip and structure from the same |
| JP2005116762A (ja) * | 2003-10-07 | 2005-04-28 | Fujitsu Ltd | 半導体装置の保護方法及び半導体装置用カバー及び半導体装置ユニット及び半導体装置の梱包構造 |
| JP2005150350A (ja) * | 2003-11-14 | 2005-06-09 | Renesas Technology Corp | 半導体装置の製造方法 |
| JP4488733B2 (ja) * | 2003-12-24 | 2010-06-23 | 三洋電機株式会社 | 回路基板の製造方法および混成集積回路装置の製造方法。 |
| JP2006073586A (ja) * | 2004-08-31 | 2006-03-16 | Renesas Technology Corp | 半導体装置の製造方法 |
| US7791180B2 (en) * | 2004-10-01 | 2010-09-07 | Yamaha Corporation | Physical quantity sensor and lead frame used for same |
| US7595548B2 (en) * | 2004-10-08 | 2009-09-29 | Yamaha Corporation | Physical quantity sensor and manufacturing method therefor |
| CN100416807C (zh) * | 2004-10-20 | 2008-09-03 | 力晶半导体股份有限公司 | 半导体封装结构及其制造方法 |
| JP2006190771A (ja) | 2005-01-05 | 2006-07-20 | Renesas Technology Corp | 半導体装置 |
| DE102005002862A1 (de) * | 2005-01-20 | 2006-07-27 | Infineon Technologies Ag | Vefahren zur Herstellung eines FBGA-Bauelementes und Substrat zur Durchführung des Verfahrens |
| TWI283050B (en) * | 2005-02-04 | 2007-06-21 | Phoenix Prec Technology Corp | Substrate structure embedded method with semiconductor chip and the method for making the same |
| JP2006269486A (ja) * | 2005-03-22 | 2006-10-05 | Renesas Technology Corp | 半導体装置の製造方法 |
| US8461675B2 (en) * | 2005-12-13 | 2013-06-11 | Sandisk Technologies Inc. | Substrate panel with plating bar structured to allow minimum kerf width |
| JP4741383B2 (ja) * | 2006-02-17 | 2011-08-03 | 富士通セミコンダクター株式会社 | 電子部品の樹脂封止方法 |
| US20070269929A1 (en) * | 2006-05-17 | 2007-11-22 | Chih-Chin Liao | Method of reducing stress on a semiconductor die with a distributed plating pattern |
| US20070267759A1 (en) * | 2006-05-17 | 2007-11-22 | Chih-Chin Liao | Semiconductor device with a distributed plating pattern |
| WO2007136651A2 (en) * | 2006-05-17 | 2007-11-29 | Sandisk Corporation | Semiconductor device with a distributed plating pattern |
| JP2007335581A (ja) * | 2006-06-14 | 2007-12-27 | Renesas Technology Corp | 半導体装置の製造方法 |
| JP2008004855A (ja) * | 2006-06-26 | 2008-01-10 | Nitto Denko Corp | Tab用テープキャリア |
| JP2008016630A (ja) * | 2006-07-06 | 2008-01-24 | Matsushita Electric Ind Co Ltd | プリント配線板およびその製造方法 |
| JP5117692B2 (ja) * | 2006-07-14 | 2013-01-16 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| JP2008047573A (ja) * | 2006-08-11 | 2008-02-28 | Matsushita Electric Ind Co Ltd | 樹脂封止型半導体装置の製造装置、樹脂封止型半導体装置の製造方法、および樹脂封止型半導体装置 |
| US20080036078A1 (en) * | 2006-08-14 | 2008-02-14 | Ciclon Semiconductor Device Corp. | Wirebond-less semiconductor package |
| JP5037071B2 (ja) * | 2006-08-29 | 2012-09-26 | 新光電気工業株式会社 | 樹脂封止型半導体装置の製造方法 |
| US7616451B2 (en) * | 2006-10-13 | 2009-11-10 | Stmicroelectronics S.R.L. | Semiconductor package substrate and method, in particular for MEMS devices |
| DE102006058010B9 (de) * | 2006-12-08 | 2009-06-10 | Infineon Technologies Ag | Halbleiterbauelement mit Hohlraumstruktur und Herstellungsverfahren |
| DE102006062473A1 (de) * | 2006-12-28 | 2008-07-03 | Qimonda Ag | Halbleiterbauelement mit auf einem Substrat montiertem Chip |
| KR100849792B1 (ko) * | 2007-04-23 | 2008-07-31 | 삼성전기주식회사 | 칩 부품의 제조방법 |
| US8637972B2 (en) * | 2007-06-08 | 2014-01-28 | Sandisk Technologies Inc. | Two-sided substrate lead connection for minimizing kerf width on a semiconductor substrate panel |
| KR100878194B1 (ko) * | 2007-07-20 | 2009-01-13 | 세크론 주식회사 | 반도체 몰딩 장치 |
| JP4659802B2 (ja) * | 2007-09-25 | 2011-03-30 | シャープ株式会社 | 絶縁性配線基板、これを用いた半導体パッケージ、および絶縁性配線基板の製造方法 |
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| US9117714B2 (en) * | 2007-10-19 | 2015-08-25 | Visera Technologies Company Limited | Wafer level package and mask for fabricating the same |
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| JP5203045B2 (ja) * | 2008-05-28 | 2013-06-05 | 日本特殊陶業株式会社 | 多層配線基板の中間製品、多層配線基板の製造方法 |
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| JP5985136B2 (ja) | 2009-03-19 | 2016-09-06 | ソニー株式会社 | 半導体装置とその製造方法、及び電子機器 |
| FR2943849B1 (fr) * | 2009-03-31 | 2011-08-26 | St Microelectronics Grenoble 2 | Procede de realisation de boitiers semi-conducteurs et boitier semi-conducteur |
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| KR101037450B1 (ko) * | 2009-09-23 | 2011-05-26 | 삼성전기주식회사 | 패키지 기판 |
| EP2330618A1 (en) * | 2009-12-04 | 2011-06-08 | STMicroelectronics (Grenoble 2) SAS | Rebuilt wafer assembly |
| JP5503466B2 (ja) * | 2010-08-31 | 2014-05-28 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| JP5666211B2 (ja) * | 2010-09-01 | 2015-02-12 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 配線基板及び半導体装置の製造方法 |
| US8456021B2 (en) * | 2010-11-24 | 2013-06-04 | Texas Instruments Incorporated | Integrated circuit device having die bonded to the polymer side of a polymer substrate |
| US8759153B2 (en) * | 2011-09-06 | 2014-06-24 | Infineon Technologies Ag | Method for making a sensor device using a graphene layer |
| US8373269B1 (en) * | 2011-09-08 | 2013-02-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Jigs with controlled spacing for bonding dies onto package substrates |
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2000
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2001
- 2001-11-13 SG SG200107100A patent/SG92821A1/en unknown
- 2001-11-15 US US09/987,532 patent/US6596561B2/en not_active Expired - Lifetime
- 2001-11-20 TW TW090128724A patent/TW526598B/zh not_active IP Right Cessation
- 2001-12-19 KR KR1020010081051A patent/KR100551641B1/ko not_active Expired - Lifetime
- 2001-12-20 CN CNB011338032A patent/CN1230882C/zh not_active Expired - Lifetime
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- 2003-06-04 US US10/453,606 patent/US6723583B2/en not_active Expired - Lifetime
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101101669B1 (ko) * | 2009-12-01 | 2011-12-30 | 삼성전기주식회사 | 전자부품 제조장치 및 전자부품 제조방법 |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20020050148A (ko) | 2002-06-26 |
| SG92821A1 (en) | 2002-11-19 |
| US20050127535A1 (en) | 2005-06-16 |
| JP2002190488A (ja) | 2002-07-05 |
| TW526598B (en) | 2003-04-01 |
| US20030205797A1 (en) | 2003-11-06 |
| CN1360344A (zh) | 2002-07-24 |
| US20020074650A1 (en) | 2002-06-20 |
| US20040164428A1 (en) | 2004-08-26 |
| CN1230882C (zh) | 2005-12-07 |
| US7015069B2 (en) | 2006-03-21 |
| US6723583B2 (en) | 2004-04-20 |
| US6596561B2 (en) | 2003-07-22 |
| JP3619773B2 (ja) | 2005-02-16 |
| US6872597B2 (en) | 2005-03-29 |
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