JP5696960B2 - 縦型チャネルメモリーとその製造方法および稼働方法 - Google Patents

縦型チャネルメモリーとその製造方法および稼働方法 Download PDF

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JP5696960B2
JP5696960B2 JP2007265550A JP2007265550A JP5696960B2 JP 5696960 B2 JP5696960 B2 JP 5696960B2 JP 2007265550 A JP2007265550 A JP 2007265550A JP 2007265550 A JP2007265550 A JP 2007265550A JP 5696960 B2 JP5696960 B2 JP 5696960B2
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layer
channel
nitride
vertical channel
vertical
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JP2008172195A5 (https=
JP2008172195A (ja
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フシュ ツ−フシュアン
フシュ ツ−フシュアン
ルエ ハン−ティン
ルエ ハン−ティン
シン イェン−ハオ
シン イェン−ハオ
ウ チア−ウェイ
ウ チア−ウェイ
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旺宏電子股▲ふん▼有限公司
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0413—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having charge-trapping gate insulators, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2007265550A 2006-10-11 2007-10-11 縦型チャネルメモリーとその製造方法および稼働方法 Active JP5696960B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/545,575 2006-10-11
US11/545,575 US7811890B2 (en) 2006-10-11 2006-10-11 Vertical channel transistor structure and manufacturing method thereof
US11/785,322 US8772858B2 (en) 2006-10-11 2007-04-17 Vertical channel memory and manufacturing method thereof and operating method using the same
US11/785,322 2007-04-17

Publications (3)

Publication Number Publication Date
JP2008172195A JP2008172195A (ja) 2008-07-24
JP2008172195A5 JP2008172195A5 (https=) 2013-12-12
JP5696960B2 true JP5696960B2 (ja) 2015-04-08

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Country Link
US (1) US8772858B2 (https=)
EP (1) EP1912254B1 (https=)
JP (1) JP5696960B2 (https=)
KR (1) KR101402131B1 (https=)
CN (1) CN104282761A (https=)
TW (1) TWI359498B (https=)

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