JP4096774B2 - 半導体装置、電子デバイス、電子機器、半導体装置の製造方法及び電子デバイスの製造方法 - Google Patents

半導体装置、電子デバイス、電子機器、半導体装置の製造方法及び電子デバイスの製造方法 Download PDF

Info

Publication number
JP4096774B2
JP4096774B2 JP2003081221A JP2003081221A JP4096774B2 JP 4096774 B2 JP4096774 B2 JP 4096774B2 JP 2003081221 A JP2003081221 A JP 2003081221A JP 2003081221 A JP2003081221 A JP 2003081221A JP 4096774 B2 JP4096774 B2 JP 4096774B2
Authority
JP
Japan
Prior art keywords
carrier substrate
semiconductor package
semiconductor
bonding
opening
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2003081221A
Other languages
English (en)
Japanese (ja)
Other versions
JP2004289002A5 (enExample
JP2004289002A (ja
Inventor
哲理 青▲柳▼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2003081221A priority Critical patent/JP4096774B2/ja
Priority to CNA2008100854035A priority patent/CN101241906A/zh
Priority to US10/805,499 priority patent/US7091619B2/en
Priority to CNB2004100301876A priority patent/CN100380660C/zh
Publication of JP2004289002A publication Critical patent/JP2004289002A/ja
Publication of JP2004289002A5 publication Critical patent/JP2004289002A5/ja
Application granted granted Critical
Publication of JP4096774B2 publication Critical patent/JP4096774B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06555Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/10All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
    • H01L2225/1011All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
    • H01L2225/1017All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/10All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
    • H01L2225/1011All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
    • H01L2225/1047Details of electrical connections between containers
    • H01L2225/1058Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/10Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431Details of mounted components
    • H05K2201/10507Involving several components
    • H05K2201/10515Stacked components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431Details of mounted components
    • H05K2201/10507Involving several components
    • H05K2201/1053Mounted components directly electrically connected to each other, i.e. not via the PCB
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10734Ball grid array [BGA]; Bump grid array
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP2003081221A 2003-03-24 2003-03-24 半導体装置、電子デバイス、電子機器、半導体装置の製造方法及び電子デバイスの製造方法 Expired - Fee Related JP4096774B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2003081221A JP4096774B2 (ja) 2003-03-24 2003-03-24 半導体装置、電子デバイス、電子機器、半導体装置の製造方法及び電子デバイスの製造方法
CNA2008100854035A CN101241906A (zh) 2003-03-24 2004-03-19 半导体装置及制法、半导体封装、电子设备及制法、电子仪器
US10/805,499 US7091619B2 (en) 2003-03-24 2004-03-19 Semiconductor device, semiconductor package, electronic device, electronic apparatus, and manufacturing methods of semiconductor device and electronic device
CNB2004100301876A CN100380660C (zh) 2003-03-24 2004-03-19 半导体装置及制法、半导体封装、电子设备及制法、电子仪器

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003081221A JP4096774B2 (ja) 2003-03-24 2003-03-24 半導体装置、電子デバイス、電子機器、半導体装置の製造方法及び電子デバイスの製造方法

Publications (3)

Publication Number Publication Date
JP2004289002A JP2004289002A (ja) 2004-10-14
JP2004289002A5 JP2004289002A5 (enExample) 2005-06-02
JP4096774B2 true JP4096774B2 (ja) 2008-06-04

Family

ID=33294857

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003081221A Expired - Fee Related JP4096774B2 (ja) 2003-03-24 2003-03-24 半導体装置、電子デバイス、電子機器、半導体装置の製造方法及び電子デバイスの製造方法

Country Status (3)

Country Link
US (1) US7091619B2 (enExample)
JP (1) JP4096774B2 (enExample)
CN (2) CN101241906A (enExample)

Families Citing this family (65)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3891123B2 (ja) * 2003-02-06 2007-03-14 セイコーエプソン株式会社 半導体装置、電子デバイス、電子機器、及び半導体装置の製造方法
JP4110992B2 (ja) * 2003-02-07 2008-07-02 セイコーエプソン株式会社 半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法
JP2004259886A (ja) * 2003-02-25 2004-09-16 Seiko Epson Corp 半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法
JP4069771B2 (ja) * 2003-03-17 2008-04-02 セイコーエプソン株式会社 半導体装置、電子機器および半導体装置の製造方法
JP2004281818A (ja) * 2003-03-17 2004-10-07 Seiko Epson Corp 半導体装置、電子デバイス、電子機器、キャリア基板の製造方法、半導体装置の製造方法および電子デバイスの製造方法
JP2004281920A (ja) * 2003-03-18 2004-10-07 Seiko Epson Corp 半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法
JP3680839B2 (ja) * 2003-03-18 2005-08-10 セイコーエプソン株式会社 半導体装置および半導体装置の製造方法
JP2004281919A (ja) * 2003-03-18 2004-10-07 Seiko Epson Corp 半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法
JP4096774B2 (ja) 2003-03-24 2008-06-04 セイコーエプソン株式会社 半導体装置、電子デバイス、電子機器、半導体装置の製造方法及び電子デバイスの製造方法
JP2004349495A (ja) * 2003-03-25 2004-12-09 Seiko Epson Corp 半導体装置、電子デバイス、電子機器および半導体装置の製造方法
US20060267174A1 (en) * 2005-02-09 2006-11-30 William Macropoulos Apparatus and method using stackable substrates
US20070013042A1 (en) * 2005-06-20 2007-01-18 Nokia Corporation Electronic module assembly with heat spreader
JP2007042736A (ja) * 2005-08-01 2007-02-15 Seiko Epson Corp 半導体装置及び電子モジュール、並びに、電子モジュールの製造方法
JP5116268B2 (ja) * 2005-08-31 2013-01-09 キヤノン株式会社 積層型半導体装置およびその製造方法
JP4703356B2 (ja) * 2005-10-19 2011-06-15 パナソニック株式会社 積層型半導体装置
JP4637720B2 (ja) * 2005-10-28 2011-02-23 パナソニック株式会社 半導体装置およびその製造方法
KR101131138B1 (ko) 2006-01-04 2012-04-03 삼성전자주식회사 다양한 크기의 볼 패드를 갖는 배선기판과, 그를 갖는반도체 패키지 및 그를 이용한 적층 패키지
JP4719009B2 (ja) 2006-01-13 2011-07-06 ルネサスエレクトロニクス株式会社 基板および半導体装置
JP2007266111A (ja) * 2006-03-27 2007-10-11 Sharp Corp 半導体装置、それを用いた積層型半導体装置、ベース基板、および半導体装置の製造方法
JP4191204B2 (ja) * 2006-05-12 2008-12-03 エルピーダメモリ株式会社 半導体装置およびその製造方法
JP2008166373A (ja) 2006-12-27 2008-07-17 Nec Electronics Corp 半導体装置およびその製造方法
JP2008166440A (ja) * 2006-12-27 2008-07-17 Spansion Llc 半導体装置
US7803693B2 (en) * 2007-02-15 2010-09-28 John Trezza Bowed wafer hybridization compensation
US8709934B2 (en) * 2007-06-05 2014-04-29 Stats Chippac Ltd. Electronic system with vertical intermetallic compound
JP5192860B2 (ja) * 2008-03-18 2013-05-08 日本特殊陶業株式会社 パッケージ
JP5193898B2 (ja) * 2009-02-12 2013-05-08 新光電気工業株式会社 半導体装置及び電子装置
US8716868B2 (en) 2009-05-20 2014-05-06 Panasonic Corporation Semiconductor module for stacking and stacked semiconductor module
JP4676013B2 (ja) * 2009-06-30 2011-04-27 株式会社東芝 電子機器
US8471154B1 (en) * 2009-08-06 2013-06-25 Amkor Technology, Inc. Stackable variable height via package and method
KR101096039B1 (ko) * 2009-11-09 2011-12-19 주식회사 하이닉스반도체 인쇄회로기판 및 이를 이용한 반도체 패키지
JP2011171427A (ja) 2010-02-17 2011-09-01 Canon Inc 積層型半導体装置
US8183696B2 (en) * 2010-03-31 2012-05-22 Infineon Technologies Ag Packaged semiconductor device with encapsulant embedding semiconductor chip that includes contact pads
US8847376B2 (en) 2010-07-23 2014-09-30 Tessera, Inc. Microelectronic elements with post-assembly planarization
KR101712043B1 (ko) * 2010-10-14 2017-03-03 삼성전자주식회사 적층 반도체 패키지, 상기 적층 반도체 패키지를 포함하는 반도체 장치 및 상기 적층 반도체 패키지의 제조 방법
US8299596B2 (en) 2010-12-14 2012-10-30 Stats Chippac Ltd. Integrated circuit packaging system with bump conductors and method of manufacture thereof
US8613135B2 (en) 2011-05-06 2013-12-24 National Tsing Hua University Method for non-planar chip assembly
US9155881B2 (en) 2011-05-06 2015-10-13 Iridium Medical Technology Co, Ltd. Non-planar chip assembly
KR20130005465A (ko) * 2011-07-06 2013-01-16 삼성전자주식회사 반도체 스택 패키지 장치
WO2013025205A1 (en) 2011-08-16 2013-02-21 Intel Corporation Offset interposers for large-bottom packages and large-die package-on-package structures
US9030022B2 (en) 2011-10-24 2015-05-12 Taiwan Semiconductor Manufacturing Company, Ltd. Packages and methods for forming the same
JP6184061B2 (ja) * 2012-05-29 2017-08-23 キヤノン株式会社 積層型半導体装置及び電子機器
US8859335B2 (en) * 2012-11-02 2014-10-14 Fujitsu Limited Method and system for controlling chip inclination during flip-chip mounting
TWI546911B (zh) * 2012-12-17 2016-08-21 巨擘科技股份有限公司 封裝結構及封裝方法
US20140233166A1 (en) * 2013-02-19 2014-08-21 Norman E. O'Shea Flexible powered cards and devices, and methods of manufacturing flexible powered cards and devices
US20140231993A1 (en) * 2013-02-21 2014-08-21 Marvell World Trade Ltd. Package-on-package structures
US8970051B2 (en) * 2013-06-28 2015-03-03 Intel Corporation Solution to deal with die warpage during 3D die-to-die stacking
CN104377181B (zh) * 2013-08-15 2018-06-15 日月光半导体制造股份有限公司 半导体封装件及其制造方法
US9795038B2 (en) * 2014-09-25 2017-10-17 Intel Corporation Electronic package design that facilitates shipping the electronic package
KR102341794B1 (ko) * 2015-01-15 2021-12-21 삼성디스플레이 주식회사 가요성 표시 장치 및 그 제조 방법
US9449912B1 (en) * 2015-06-11 2016-09-20 Stmicroelectronics Pte Ltd Integrated circuit (IC) card having an IC module and reduced bond wire stress and method of forming
JP2017017238A (ja) * 2015-07-03 2017-01-19 株式会社ジェイデバイス 半導体装置及びその製造方法
JP6256431B2 (ja) * 2015-08-21 2018-01-10 Tdk株式会社 磁気センサ装置
KR20170060372A (ko) * 2015-11-24 2017-06-01 에스케이하이닉스 주식회사 휘어진 칩을 이용한 플렉서블 패키지
JP6486855B2 (ja) * 2016-03-16 2019-03-20 東芝メモリ株式会社 半導体装置および半導体装置の製造方法
US9960137B1 (en) * 2016-11-01 2018-05-01 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method for forming the same
CN110007117A (zh) * 2018-01-05 2019-07-12 旺矽科技股份有限公司 探针卡
KR102509642B1 (ko) * 2018-09-27 2023-03-16 삼성전자주식회사 도전성 볼 부착 장치
US10964660B1 (en) * 2018-11-20 2021-03-30 Flex Ltd. Use of adhesive films for 3D pick and place assembly of electronic components
US11694984B2 (en) * 2019-08-30 2023-07-04 Advanced Semiconductor Engineering, Inc. Package structure including pillars and method for manufacturing the same
JP2021048195A (ja) * 2019-09-17 2021-03-25 キオクシア株式会社 半導体装置及び半導体装置の製造方法
JP7676108B2 (ja) * 2019-12-06 2025-05-14 富士電機株式会社 半導体装置及び半導体装置の製造方法
CN111192869B (zh) * 2020-01-08 2022-08-02 錼创显示科技股份有限公司 基板和显示设备
TWI720772B (zh) * 2020-01-08 2021-03-01 錼創顯示科技股份有限公司 基板和顯示裝置
CN114284174B (zh) * 2021-12-14 2025-09-23 苏州华星光电技术有限公司 印刷网、显示装置的制作方法及显示装置
US12261139B1 (en) * 2024-02-29 2025-03-25 Ciena Corporation Managing stress in semiconductor chips

Family Cites Families (76)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3871015A (en) * 1969-08-14 1975-03-11 Ibm Flip chip module with non-uniform connector joints
US5120678A (en) 1990-11-05 1992-06-09 Motorola Inc. Electrical component package comprising polymer-reinforced solder bump interconnection
US5222014A (en) 1992-03-02 1993-06-22 Motorola, Inc. Three-dimensional multi-chip pad array carrier
GB9312328D0 (en) 1993-06-15 1993-07-28 Lexor Technology Limited A method of brazing
US6835898B2 (en) * 1993-11-16 2004-12-28 Formfactor, Inc. Electrical contact structures formed by configuring a flexible wire to have a springable shape and overcoating the wire with at least one layer of a resilient conductive material, methods of mounting the contact structures to electronic components, and applications for employing the contact structures
KR970000214B1 (ko) 1993-11-18 1997-01-06 삼성전자 주식회사 반도체 장치 및 그 제조방법
US5642261A (en) * 1993-12-20 1997-06-24 Sgs-Thomson Microelectronics, Inc. Ball-grid-array integrated circuit package with solder-connected thermal conductor
US5432358A (en) * 1994-03-24 1995-07-11 Motorola, Inc. Integrated electro-optical package
JPH07307410A (ja) * 1994-05-16 1995-11-21 Hitachi Ltd 半導体装置
JPH08115989A (ja) 1994-08-24 1996-05-07 Fujitsu Ltd 半導体装置及びその製造方法
US6870272B2 (en) * 1994-09-20 2005-03-22 Tessera, Inc. Methods of making microelectronic assemblies including compliant interfaces
JPH092685A (ja) 1995-06-20 1997-01-07 Ricoh Co Ltd 画像形成装置
AU7096696A (en) 1995-11-28 1997-06-19 Hitachi Limited Semiconductor device, process for producing the same, and packaged substrate
US5660321A (en) * 1996-03-29 1997-08-26 Intel Corporation Method for controlling solder bump height and volume for substrates containing both pad-on and pad-off via contacts
US5940729A (en) * 1996-04-17 1999-08-17 International Business Machines Corp. Method of planarizing a curved substrate and resulting structure
JP2806357B2 (ja) 1996-04-18 1998-09-30 日本電気株式会社 スタックモジュール
JPH1084076A (ja) 1996-09-05 1998-03-31 Hitachi Ltd 半導体装置およびその製造方法
US6121689A (en) * 1997-07-21 2000-09-19 Miguel Albert Capote Semiconductor flip-chip package and method for the fabrication thereof
US5796169A (en) * 1996-11-19 1998-08-18 International Business Machines Corporation Structurally reinforced ball grid array semiconductor package and systems
JPH10163386A (ja) 1996-12-03 1998-06-19 Toshiba Corp 半導体装置、半導体パッケージおよび実装回路装置
US5994166A (en) 1997-03-10 1999-11-30 Micron Technology, Inc. Method of constructing stacked packages
JP2964983B2 (ja) 1997-04-02 1999-10-18 日本電気株式会社 三次元メモリモジュール及びそれを用いた半導体装置
JPH10294423A (ja) * 1997-04-17 1998-11-04 Nec Corp 半導体装置
JP3564946B2 (ja) 1997-06-09 2004-09-15 株式会社デンソー フリップチップの実装構造
JPH1174312A (ja) * 1997-08-28 1999-03-16 Mitsubishi Electric Corp 半導体装置およびはんだバンプの形成方法
JP3230487B2 (ja) 1998-04-20 2001-11-19 住友金属工業株式会社 三次元パッケージおよびその製造方法
US6369444B1 (en) 1998-05-19 2002-04-09 Agere Systems Guardian Corp. Packaging silicon on silicon multichip modules
JP2000040713A (ja) 1998-07-23 2000-02-08 Citizen Watch Co Ltd 半導体パッケージの製造方法
JP3201353B2 (ja) 1998-08-04 2001-08-20 日本電気株式会社 半導体装置とその製造方法
US6133634A (en) 1998-08-05 2000-10-17 Fairchild Semiconductor Corporation High performance flip chip package
TW434767B (en) 1998-09-05 2001-05-16 Via Tech Inc Package architecture of ball grid array integrated circuit device
WO2000049656A1 (fr) 1999-02-17 2000-08-24 Hitachi, Ltd. Dispositif semi-conducteur et procede de fabrication associe
US6444563B1 (en) * 1999-02-22 2002-09-03 Motorlla, Inc. Method and apparatus for extending fatigue life of solder joints in a semiconductor device
US6023097A (en) 1999-03-17 2000-02-08 Chipmos Technologies, Inc. Stacked multiple-chip module micro ball grid array packaging
US6034425A (en) 1999-03-17 2000-03-07 Chipmos Technologies Inc. Flat multiple-chip module micro ball grid array packaging
JP2001015633A (ja) 1999-06-29 2001-01-19 Hitachi Ltd 半導体装置
TW417839U (en) * 1999-07-30 2001-01-01 Shen Ming Tung Stacked memory module structure and multi-layered stacked memory module structure using the same
US6122171A (en) * 1999-07-30 2000-09-19 Micron Technology, Inc. Heat sink chip package and method of making
TW415056B (en) 1999-08-05 2000-12-11 Siliconware Precision Industries Co Ltd Multi-chip packaging structure
JP2001156212A (ja) 1999-09-16 2001-06-08 Nec Corp 樹脂封止型半導体装置及びその製造方法
JP3668074B2 (ja) 1999-10-07 2005-07-06 松下電器産業株式会社 半導体装置およびその製造方法
JP3798597B2 (ja) 1999-11-30 2006-07-19 富士通株式会社 半導体装置
JP3881488B2 (ja) 1999-12-13 2007-02-14 株式会社東芝 回路モジュールの冷却装置およびこの冷却装置を有する電子機器
US6369448B1 (en) 2000-01-21 2002-04-09 Lsi Logic Corporation Vertically integrated flip chip semiconductor package
US6396116B1 (en) * 2000-02-25 2002-05-28 Agilent Technologies, Inc. Integrated circuit packaging for optical sensor devices
US6731009B1 (en) 2000-03-20 2004-05-04 Cypress Semiconductor Corporation Multi-die assembly
KR100408616B1 (ko) * 2000-03-21 2003-12-03 미쓰비시덴키 가부시키가이샤 반도체 장치, 전자 기기의 제조 방법, 전자 기기 및 휴대정보 단말
JP2001339011A (ja) 2000-03-24 2001-12-07 Shinko Electric Ind Co Ltd 半導体装置およびその製造方法
US7247932B1 (en) * 2000-05-19 2007-07-24 Megica Corporation Chip package with capacitor
JP2001352035A (ja) 2000-06-07 2001-12-21 Sony Corp 多層半導体装置の組立治具及び多層半導体装置の製造方法
US6461881B1 (en) 2000-06-08 2002-10-08 Micron Technology, Inc. Stereolithographic method and apparatus for fabricating spacers for semiconductor devices and resulting structures
JP2002057273A (ja) 2000-08-07 2002-02-22 Orient Semiconductor Electronics Ltd 集積回路パッケージ用積み重ねダイセット
JP2002134650A (ja) 2000-10-23 2002-05-10 Rohm Co Ltd 半導体装置およびその製造方法
JP4451559B2 (ja) 2000-10-26 2010-04-14 パナソニック株式会社 半導体装置およびその製造方法
US6734539B2 (en) 2000-12-27 2004-05-11 Lucent Technologies Inc. Stacked module package
KR20020065045A (ko) * 2001-02-05 2002-08-13 삼성전자 주식회사 확장 패드들을 포함하는 반도체 칩 패키지
JP3854819B2 (ja) 2001-04-27 2006-12-06 株式会社ルネサステクノロジ 半導体装置の製造方法
JP4629912B2 (ja) 2001-05-25 2011-02-09 富士通セミコンダクター株式会社 はんだバンプの形成方法
US6586684B2 (en) * 2001-06-29 2003-07-01 Intel Corporation Circuit housing clamp and method of manufacture therefor
US6686225B2 (en) 2001-07-27 2004-02-03 Texas Instruments Incorporated Method of separating semiconductor dies from a wafer
US6787916B2 (en) 2001-09-13 2004-09-07 Tru-Si Technologies, Inc. Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity
KR20030029743A (ko) * 2001-10-10 2003-04-16 삼성전자주식회사 플랙서블한 이중 배선기판을 이용한 적층 패키지
JP3866591B2 (ja) 2001-10-29 2007-01-10 富士通株式会社 電極間接続構造体の形成方法および電極間接続構造体
KR20030044255A (ko) * 2001-11-29 2003-06-09 한국전자통신연구원 플립칩 본딩 광모듈 패키지 및 그 패키징 방법
JP2003218150A (ja) 2002-01-23 2003-07-31 Fujitsu Media Device Kk モジュール部品
JP2003318361A (ja) 2002-04-19 2003-11-07 Fujitsu Ltd 半導体装置及びその製造方法
US6903458B1 (en) 2002-06-20 2005-06-07 Richard J. Nathan Embedded carrier for an integrated circuit chip
JP4072020B2 (ja) 2002-08-09 2008-04-02 日本電波工業株式会社 表面実装水晶発振器
JP2004079923A (ja) 2002-08-22 2004-03-11 Fujitsu Ltd 半導体装置及びその製造方法
US6654250B1 (en) * 2002-09-25 2003-11-25 International Business Machines Corporation Low-stress compressive heatsink structure
JP2004179232A (ja) 2002-11-25 2004-06-24 Seiko Epson Corp 半導体装置及びその製造方法並びに電子機器
US6750549B1 (en) * 2002-12-31 2004-06-15 Intel Corporation Variable pad diameter on the land side for improving the co-planarity of ball grid array packages
JP4475875B2 (ja) 2003-02-26 2010-06-09 イビデン株式会社 プリント配線板
JP3917946B2 (ja) 2003-03-11 2007-05-23 富士通株式会社 積層型半導体装置
JP4096774B2 (ja) 2003-03-24 2008-06-04 セイコーエプソン株式会社 半導体装置、電子デバイス、電子機器、半導体装置の製造方法及び電子デバイスの製造方法
US20040262368A1 (en) * 2003-06-26 2004-12-30 Haw Tan Tzyy Ball grid array solder joint reliability

Also Published As

Publication number Publication date
US20040222510A1 (en) 2004-11-11
JP2004289002A (ja) 2004-10-14
CN101241906A (zh) 2008-08-13
US7091619B2 (en) 2006-08-15
CN1532931A (zh) 2004-09-29
CN100380660C (zh) 2008-04-09

Similar Documents

Publication Publication Date Title
JP4096774B2 (ja) 半導体装置、電子デバイス、電子機器、半導体装置の製造方法及び電子デバイスの製造方法
US6479321B2 (en) One-step semiconductor stack packaging method
US6545366B2 (en) Multiple chip package semiconductor device
US20040222508A1 (en) Semiconductor device, electronic device, electronic apparatus, method of manufacturing semiconductor device, and method of manufacturing electronic device
JP2001217388A (ja) 電子装置およびその製造方法
JP2004349495A (ja) 半導体装置、電子デバイス、電子機器および半導体装置の製造方法
US20040227236A1 (en) Semiconductor device, electronic device, electronic apparatus, and methods for manufacturing carrier substrate, semiconductor device, and electronic device
US20090102049A1 (en) Semiconductor device, layered type semiconductor device using the same, base substrate and semiconductor device manufacturing method
JP4069771B2 (ja) 半導体装置、電子機器および半導体装置の製造方法
JP3891123B2 (ja) 半導体装置、電子デバイス、電子機器、及び半導体装置の製造方法
JP3786103B2 (ja) 半導体装置、電子デバイス、電子機器および半導体装置の製造方法
US20070020812A1 (en) Circuit board structure integrated with semiconductor chip and method of fabricating the same
JP2007042762A (ja) 半導体装置およびその実装体
US7276800B2 (en) Carrying structure of electronic components
JP2005340450A (ja) 半導体装置及びその製造方法、回路基板並びに電子機器
TW550717B (en) Improvement of flip-chip package
JP3710003B2 (ja) 実装基板及び実装基板の製造方法
JPH118474A (ja) 多層基板の製造方法
JP2768315B2 (ja) 半導体装置
CN100361301C (zh) 多芯片半导体封装件及其制法
JP3611463B2 (ja) 電子部品の製造方法
JP3623641B2 (ja) 半導体装置
CN114551256B (zh) 一种基于柔性基板的三维堆叠封装方法
KR102785840B1 (ko) 반도체 패키지
JP2007142124A (ja) 半導体装置およびその製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20040817

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20040817

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20060725

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060801

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060922

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20061017

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20061204

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20071204

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080129

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20080219

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20080303

R150 Certificate of patent or registration of utility model

Ref document number: 4096774

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110321

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120321

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120321

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130321

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140321

Year of fee payment: 6

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees