JP2009246370A - マイクロコンピュータ及びデータプロセッサ - Google Patents
マイクロコンピュータ及びデータプロセッサ Download PDFInfo
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- JP2009246370A JP2009246370A JP2009100471A JP2009100471A JP2009246370A JP 2009246370 A JP2009246370 A JP 2009246370A JP 2009100471 A JP2009100471 A JP 2009100471A JP 2009100471 A JP2009100471 A JP 2009100471A JP 2009246370 A JP2009246370 A JP 2009246370A
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- G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
Abstract
【解決手段】マイクロコンピュータは、内部バス68と、前記内部バスに結合されている中央演算部61と、前記内部バスに結合された不揮発性メモリ63とを含む。前記不揮発性メモリは、第1ゲートと第2ゲートとを含む複数の不揮発メモリセルと、前記複数の不揮発メモリセルの一つの前記第1ゲートに結合された第1回路21と、前記複数の不揮発メモリセルの一つの前記第2ゲートに結合された第2回路22と、前記第1回路に供給する第1電圧と前記第2回路に供給する第2電圧とを生成する電圧生成回路VS,77と、を含む。前記第1回路のゲート耐圧は前記第2回路のゲート耐圧より低い。
【選択図】図25
Description
Claims (14)
- 内部バスと、
前記内部バスに結合されている中央演算部と、
第1ゲートと第2ゲートとを含む複数の不揮発メモリセルと、前記複数の不揮発メモリセルの一つの前記第1ゲートに結合された第1回路と、前記複数の不揮発メモリセルの一つの前記第2ゲートに結合された第2回路と、前記第1回路に供給する第1電圧と前記第2回路に供給する第2電圧とを生成する電圧生成回路と、を含み前記内部バスに結合された不揮発メモリと、
を含み、
前記第1回路のゲート耐圧は前記第2回路のゲート耐圧より低いことを特徴とするマイクロコンピュータ。 - 前記複数の不揮発メモリセルは、チャネル領域と前記第2ゲートとの間に電荷蓄積領域を有することを特徴とした請求項1に記載のマイクロコンピュータ。
- 前記第1回路は、前記複数の不揮発メモリセルの一方側に配置されていることを特徴とする請求項1に記載のマイクロコンピュータ。
- 前記第2回路は、前記一方側に対向している前記複数の不揮発メモリセルの他方側に配置されることを特徴とする請求項3に記載のマイクロコンピュータ。
- 前記中央演算部はMOS型トランジスタを有し、
前記MOS型トランジスタのゲート耐圧は前記第2回路のゲート耐圧より低いことを特徴とする請求項1に記載のマイクロコンピュータ。 - 半導体チップ上に形成されたマイクロコンピュータであって、
内部バスと、
MOS型トランジスタを有し前記内部バスと結合された中央演算部と、
夫々に第1ゲートと第2ゲートとを含む複数の不揮発メモリセルと、前記複数の不揮発メモリセルの1つの前記第1ゲートに結合された第1ドライバと、前記複数の不揮発メモリセルの1つの前記第2ゲートに結合された第2ドライバと、前記第1ドライバに供給する第1電圧と前記第2ドライバに供給する第2電圧とを生成する電圧生成回路と、を含み前記内部バスに結合されたフラッシュメモリと、
を有し、
前記第1ドライバのゲート耐圧と前記中央演算部の前記MOSトランジスタのゲート耐圧とは前記第2回路のゲート耐圧より低いことを特徴とするマイクロコンピュータ。 - 前記複数の不揮発メモリセルは、チャネル領域と前記第2ゲートとの間に電荷蓄積領域を有することを特徴とした請求項6に記載のマイクロコンピュータ。
- 前記第1ドライバは、前記複数の不揮発メモリセルの一方側に配置されていることを特徴とする請求項6に記載のマイクロコンピュータ。
- 前記第2ドライバは、前記一方側に対向している前記複数の不揮発メモリセルの他方側に配置されることを特徴とする請求項8に記載のマイクロコンピュータ。
- 半導体チップ上に形成されたデータプロセッサであって、
内部バスと、
MOS型トランジスタを有し前記内部バスに結合された中央演算部と、
夫々に第1制御ゲートと第2制御ゲートを有する複数の不揮発メモリセルと、1つのワード線、1つの制御線、1つのソース線が1つの不揮発メモリセルに接続されるように前記複数の不揮発メモリセルに結合される複数のワード線と複数の制御線と複数のソース線と、前記ワード線を介して前記複数のメモリセルの前記第1制御ゲートに結合される第1ドライバと、前記制御線を介して前記複数のメモリセルの前記第2制御ゲートに結合される第2ドライバと、を含み前記内部バスに結合されたフラッシュメモリと、を有し、
前記第1ドライバのゲート耐圧は前記第2ドライバのゲート耐圧より低いことを特徴とするデータプロセッサ。 - 前記複数の不揮発メモリセルは、チャネル領域と前記第2制御ゲートとの間に電荷蓄積領域を有することを特徴とした請求項10に記載のデータプロセッサ。
- 前記中央演算部はMOS型トランジスタを有し、
前記MOS型トランジスタのゲート耐圧は前記第2ドライバのゲート耐圧より低いことを特徴とする請求項10に記載のデータプロセッサ。 - 前記第1ドライバは、前記複数の不揮発メモリセルの一方側に配置されていることを特徴とする請求項10に記載のデータプロセッサ。
- 前記第2ドライバは、前記一方側に対向している前記複数の不揮発メモリセルの他方側に配置されることを特徴とする請求項10に記載のデータプロセッサ。
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