JP2008288227A5 - - Google Patents

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JP2008288227A5
JP2008288227A5 JP2007128692A JP2007128692A JP2008288227A5 JP 2008288227 A5 JP2008288227 A5 JP 2008288227A5 JP 2007128692 A JP2007128692 A JP 2007128692A JP 2007128692 A JP2007128692 A JP 2007128692A JP 2008288227 A5 JP2008288227 A5 JP 2008288227A5
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Priority to US12/752,828 priority patent/US8168547B2/en
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Claims (19)

  1. 半導体基板上にMISトランジスタのゲート絶縁膜を形成し、前記ゲート絶縁膜上に前記MISトランジスタのゲート電極を形成する工程を含む半導体装置の製造方法であって、
    前記半導体基板上に前記ゲート絶縁膜を形成する工程は、
    (a)前記半導体基板の主面上に、酸化シリコンより高い比誘電率の酸化物から構成される第1層を形成する工程と、
    (b)前記工程(a)の後、前記半導体基板の主面を非酸化性雰囲気中で熱処理する工程と、
    (c)前記第1層上に、前記工程(b)直後の第1層中に占める酸素の割合より高い酸化物から構成される第2層を形成する工程と、
    (d)前記第2層上に、酸素が拡散するのを抑制する金属から構成されるキャップ層を形成する工程と、
    (e)前記工程(d)の後、前記半導体基板の主面を熱処理する工程と、
    を含むことを特徴とする半導体装置の製造方法。
  2. 前記工程(c)では、前記第2層を構成する酸化ハフニウム膜を、酸素原料として水を用いたALD法によって、前記第1層上に形成することを特徴とする請求項1記載の半導体装置の製造方法。
  3. 前記工程(c)では、前記第2層を構成する酸化アルミニウム膜を、酸素原料として水を用いたALD法によって、前記第1層上に形成することを特徴とする請求項1記載の半導体装置の製造方法。
  4. 前記工程(c)では、前記第2層を構成する酸化タンタル膜を、酸素原料として水を用いたALD法によって、前記第1層上に形成することを特徴とする請求項1記載の半導体装置の製造方法。
  5. (f)前記キャップ層をパターニングすることによって、前記キャップ層から構成される前記ゲート電極を形成する工程と、
    を含むことを特徴とする請求項1記載の半導体装置の製造方法。
  6. 前記工程(b)では、前記第1層を緻密化することを特徴とする請求項1記載の半導体装置の製造方法。
  7. 前記工程(e)では、前記第2層から前記第1層へ酸素を供給することを特徴とする請求項1記載の半導体装置の製造方法。
  8. (a)半導体基板上に第1層を形成する工程と、
    (b)前記第1層上に第2層を形成する工程と、
    (c)前記第2層上にキャップ層を形成する工程と、
    (d)前記工程(a)〜(c)後に、前記半導体基板の主面を熱処理する工程、
    を有し、
    前記第1及び第2層はMISトランジスタのゲート絶縁膜を構成しており、
    前記キャップ層は前記MISトランジスタのゲート電極を構成しており、
    前記第1層はハフニウムと酸素を含んで構成されており、
    前記第2層はアルミニウムと酸素、または、タンタルと酸素を含んで構成されており、
    前記第2層の膜厚は、前記第1層の膜厚よりも薄いことを特徴とする半導体装置の製造方法。
  9. 前記工程(d)によって、前記第2層から前記第1層に酸素が供給されることを特徴とする請求項8に記載の半導体装置の製造方法。
  10. 前記工程(a)と前記工程(b)との間に、(e)前記半導体基板の主面を非酸化性雰囲気中で熱処理する工程、を更に有することを特徴とする請求項8または9の何れか1項に記載の半導体装置の製造方法。
  11. 前記工程(e)によって、前記第1層が緻密化されることを特徴とする請求項10に記載の半導体装置の製造方法。
  12. 前記工程(b)で形成される前記第2層は、前記工程(a)直後の前記第1層中に占める酸素の割合より高い酸化物から構成されることを特徴とする請求項10または11の何れか1項に記載の半導体装置の製造方法。
  13. 前記工程(b)で、前記第2層はALD法によって形成されることを特徴とする請求項8〜12の何れか1項に記載の半導体装置の製造方法。
  14. 前記工程(a)で、前記第1層はALD法によって形成されることを特徴とする請求項8〜13の何れか1項に記載の半導体装置の製造方法。
  15. 前記工程(a)前に、(f)前記半導体基板上に酸化シリコン膜を形成する工程、を更に有し、
    前記酸化シリコン膜の膜厚は、前記第1層の膜厚よりも薄いことを特徴とする請求項8〜14の何れか1項に記載の半導体装置の製造方法。
  16. 前記第2層の膜厚は、前記酸化シリコン膜の膜厚よりも薄いことを特徴とする請求項15に記載の半導体装置の製造方法。
  17. 前記キャップ層は、金属から構成されていることを特徴とする請求項8〜16の何れか1項に記載の半導体装置の製造方法。
  18. 前記MISトランジスタはnチャネル型MISトランジスタであり、
    前記キャップ層は、窒化タンタル、アルミニウム、チタン、または、タンタルによって構成されていることを特徴とする請求項8〜16の何れか1項に記載の半導体装置の製造方法。
  19. 前記MISトランジスタはpチャネル型MISトランジスタであり、
    前記キャップ層は、ルテニウム、プラチナ、または、ニッケルによって構成されていることを特徴とする請求項8〜16の何れか1項に記載の半導体装置の製造方法。
JP2007128692A 2007-05-15 2007-05-15 半導体装置の製造方法 Active JP5103056B2 (ja)

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US12/116,940 US20090011608A1 (en) 2007-05-15 2008-05-07 Manufacturing method of semiconductor device
US12/752,828 US8168547B2 (en) 2007-05-15 2010-04-01 Manufacturing method of semiconductor device

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