CN1540757A - 具应变通道的互补式金氧半导体及其制作方法 - Google Patents
具应变通道的互补式金氧半导体及其制作方法 Download PDFInfo
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Abstract
本发明揭示一种具应变通道的互补式金氧半导体,主要是包括:一半导体基底、设置于上述半导体基底内的复数沟槽隔离区、一氮化物衬垫层、一离子布植氮化物衬垫层、一N型通道晶体管以及一P型通道晶体管。其中,相邻两沟槽隔离区之间各定义出一主动区,主动区包括一N型主动区与一P型主动区。另外,氮化物衬垫层,顺应性设置于上述N型主动区两侧的上述沟槽隔离区与上述半导体基底之间。再者,离子布植氮化物衬垫层,顺应性设置于上述P型主动区两侧的沟槽隔离区与半导体基底之间。并且,N型通道晶体管,设置于N型主动区上方。以及,P型通道晶体管,设置于P型主动区上方。
Description
技术领域
本发明是有关于一种场效晶体管,且特别是有关于一种包括具有拉伸应变的N型通道晶体管(NMOS)与具有压缩应力的P型通道晶体管(PMOS)的互补式金氧半场效晶体管(CMOS)组件及其制作方法。
背景技术
随着栅极组件尺寸的缩小化,要使金氧半场效晶体管(MOSFET)组件能在低操作电压下,具有高趋动电流和高速的效能是相当困难的。因此,许多人在努力寻求改善金氧半场效晶体管组件的效能的方法。
利用应变引发的能带结构变型来增加载子的迁移率,以增加场效晶体管的趋动电流,可改善场效晶体管组件的效能,且此种方法已被应用于各种组件中。这些组件的硅信道是处于双轴拉伸应变的情况。
已有研究指出利用硅通道处于双轴拉伸应变的情况中来增加电子的迁移率(K.Ismail et al.,“Electron transport properties in Si/SiGeheterostructures:Measurements and device applications”,Appl.Phys.Lett.63,pp.660,1993.),及利用硅锗通道处于双轴压缩应变的情况中来增加电洞的迁移率(D.K.Nayak et al.,“Enhancement-modequantum-well GeSi PMOS”,IEEE Elect.Dev.Lett.12,pp.154,1991.)。然而,结合具有双轴拉伸应变的硅通道的NMOSFETs(N型金氧半场效晶体管)及具有双轴压缩应变的硅锗通道的PMOSFETs(P型金氧半场效晶体管)的CMOS制程技术是难以达成的。在晶体管的制造上有利用厚的缓冲层或复杂多层结构等许多应变层制造方法(K.Ismail et al.,IBM,Jul.1996,Complementary metal-oxide semiconductor transistorlogic using strained Si/SiGe heterostructure layers,U.S.PatentNo.5534713.),此些方法并不易于整合到传统的CMOS制程中。
再者,更有研究提出以覆盖一层应力膜于整个晶体管上方的方式,以提供适当的应力予晶体管的通道区(A.Shimizu et al.,“Localmechanical stress control (LMC):A new technique for CMOSperformance enhancement”,pp.433-436 of the Digest of TechnicalPapers of the 2001 International Electron Device Meeting.)
然而,于通道区导入压缩应力有利于改善电动的迁移速率,却会对电子迁移率造成退化。因此,对N型通道晶体管(NMOS)而言,需要导入拉伸应力以提升电子迁移率,而对P型通道晶体管(PMOS)而言,需要导入压缩应力以提升电洞迁移率。但是在同一芯片上欲制作出同时具有拉伸应力信道区的N型信道晶体管(NMOS)与压缩应力信道区的P型信道晶体管(PMOS)的互补式金氧半导体(CMOS),却有相当的困难。
有鉴于此,本发明提出一种可同时具拉伸应力通道区与压缩应力通道区的半导体基底及其制作方法,可适用于制作互补式金氧半导体。
发明内容
本发明的目的在于一种具应变信道的互补式金氧半导体及其制作方法,使N型信道晶体管的信道区具有拉伸应力,而P型信道晶体管的信道区具有压缩应力,整合两者于同一芯片,以提升组件的操作速度。
本发明的主要特征之一是在于N型通道晶体管两侧的浅沟槽隔离区内顺应性形成一氮化物衬垫层,用以阻挡后续填充于浅沟槽隔离区的氧化物扩散,以避免隔离氧化物体积膨胀,并且氮化物衬垫层本身可提供N型晶体管的半导体基底通道区形成一拉伸应力。另外,将P型通道晶体管两侧的浅沟槽隔离区内的氮化物衬垫层施以离子布植,以造成氮化物衬垫层内的缺陷形成,有利于后续填充于浅沟槽隔离区的氧化物扩散,以于P型晶体管的半导体基底通道区形成一压缩应力。
为获致上述的目的,本发明提出一种具应变通道的互补式金氧半导体,主要是包括:一半导体基底、设置于上述半导体基底内的复数沟槽隔离区、一氮化物衬垫层、一离子布植氮化物衬垫层、一N型通道晶体管以及一P型通道晶体管。其中,相邻两上述沟槽隔离区之间各定义出一主动区,上述主动区包括一N型主动区与一P型主动区。另外,上述氮化物衬垫层,顺应性设置于上述N型主动区两侧的上述沟槽隔离区与上述半导体基底之间。再者,上述离子布植氮化物衬垫层,顺应性设置于上述P型主动区两侧的上述沟槽隔离区与上述半导体基底之间。并且,上述N型通道晶体管,设置于上述N型主动区上方。以及,上述P型通道晶体管,设置于上述P型主动区上方。
如前所述,上述半导体基底包括:一硅基底、堆栈的一硅层与一硅锗层或堆栈的一第一硅基底、一埋入绝缘层与一第二硅基底。
如前所述,上述沟槽隔离区的厚度大体为2000-6000。
如前所述,上述沟槽隔离区是由一氧化物所构成。
如前所述,本发明的结构更包括:一氧化物衬垫层,顺应性设置于上述氮化物衬垫层与上述半导体基底之间。
如前所述,本发明的结构更包括:一氧化物衬垫层,顺应性设置于上述离子布植氮化物衬垫层与上述半导体基底之间。
如前所述,上述氮化物衬垫层是由氮化硅所构成,而上述离子布植氮化物衬垫层是由被施以离子布植的氮化硅所构成。
如前所述,上述离子布植氮化物衬垫层所被施加的离子包括:硅(Si)离子、氮(N)离子、氦(He)离子、氖(Ne)离子、氩(Ar)、氙(Xe)或锗离子。
根据本发明,上述N型主动区的上述半导体基底表层具有一拉伸应变通道区。上述拉伸应变通道区的拉伸应变量大体为0.1%-2%。
根据本发明,上述P型主动区的上述半导体基底表层具有一压缩应变通道区。上述压缩应变通道区的拉伸应变量大体为0.1%-2%。
根据前述的具应变通道的互补式金氧半导体,本发明又提出。一种具应变通道的互补式金氧半导体的制作方法,包括:
首先,供一半导体基底。接着,形成复数沟槽于上述基底内,使得相邻两上述沟槽之间各定义出一主动区,其中上述主动区包括一N型主动区与一P型主动区。接着,顺应性形成一氮化物衬垫层,于各上述沟槽的侧壁与底部。接着,实施一离子布植于上述P型主动区两侧的上述氮化物衬垫层内。然后,形成复数沟槽隔离物,以填满各上述沟槽。接着,形成一N型通道晶体管于上述N型主动区上方。最后,形成一P型通道晶体管于上述P型主动区上方。
如前所述,形成上述N型通道晶体管与上述P型通道晶体管之后更包括:分别形成一应力膜,覆盖于上述N型通道晶体管与上述P型通道晶体管表面。上述应力膜是由化学气相沉积法(chemical vapor deposition;CVD)所形成。
本发明的主要特征的二是在于N型通道晶体管两侧的浅沟槽隔离区内顺应性形成一氮化物衬垫层,用以阻挡后续填充于浅沟槽隔离区的氧化物扩散,以避免隔离氧化物体积膨胀,并且氮化物衬垫层本身可提供N型晶体管的半导体基底通道区形成一拉伸应力。另外,P型通道晶体管两侧的浅沟槽隔离区内并无氮化物衬垫层,后续填充于浅沟槽隔离区的氧化物会体积膨胀,导致于P型晶体管的半导体基底通道区形成一压缩应力。
为获致上述的目的,本发明提出一种具应变通道的互补式金氧半导体,主要是包括:一半导体基底、复数沟槽隔离区、一氮化物衬垫层、一N型通道晶体管、一P型通道晶体管。其中,上述沟槽隔离区,设置于上述半导体基底内,使得相邻两上述沟槽隔离区之间各定义出一主动区,上述主动区包括一N型主动区与一P型主动区。并且,上述氮化物衬垫层,顺应性设置于上述N型主动区两侧的上述沟槽隔离区与上述半导体基底之间。再者,上述N型通道晶体管,设置于上述N型主动区上方。以及,上述P型通道晶体管,设置于上述P型主动区上方。
如前所述,上述半导体基底包括:一硅基底、堆栈的一硅层与一硅锗层或堆栈的一第一硅基底、一埋入绝缘层与一第二硅基底。
如前所述,上述沟槽隔离区的厚度大体为2000-6000。
如前所述,上述沟槽隔离区是由一氧化物所构成。
如前所述,本发明的结构更包括:一氧化物衬垫层,顺应性设置于上述氮化物衬垫层与上述半导体基底之间。
如前所述,上述氮化物衬垫层是由氮化硅所构成。
根据本发明,上述N型主动区的上述半导体基底表层具有一拉伸应变通道区,上述拉伸应变通道区的拉伸应变量大体为0.1%-2%。
根据本发明,上述P型主动区的上述半导体基底表层具有一压缩应变通道区,上述拉伸应变通道区的拉伸应变量大体为0.1%-2%。
根据前述的具应变通道的互补式金氧半导体,本发明更提出一种具应变通道的互补式金氧半导体的制作方法,包括:
首先,提供一半导体基底。接着,形成复数沟槽于上述基底内,使得相邻两上述沟槽之间各定义出一主动区,其中上述主动区包括一N型主动区与一P型主动区。接着,顺应性形成一氮化物衬垫层,于上述N型主动区两侧的各上述沟槽的侧壁与底部。接着,形成复数沟槽隔离物,以填满各上述沟槽。形成一N型通道晶体管于上述N型主动区上方。最后,形成一P型通道晶体管于上述P型主动区上方。
附图说明
图1A至图1H系显示根据本发明的具应变通道的互补式金氧半导体的一较佳实施例的制程剖面图;
图2A至图2H系显示根据本发明的具应变通道的互补式金氧半导体的另一较佳实施例的制程剖面图;
图3A至图3H系显示根据本发明的具应变通道的互补式金氧半导体的又一较佳实施例的制程剖面图。
符号说明:
100、200、300-半导体基底
102、202、302-图案化罩幕层
104a、104b、204a、204b、304a、304b-沟槽隔离区
106、206、306-氧化物衬垫层
108、208、308-氮化物衬垫层
108a-离子布植氮化物衬垫层
112、212、312-隔离氧化物
117、217、317-N型通道晶体管
116、216、316-P型通道晶体管
S100-离子布植程序
114、214、314-栅极介电层
115、215、315-栅极层
118、218、318-间隙壁
122、120、220、222、320、322-应力膜
210、311-罩幕层
S100-形成氮化物衬垫层程序
具体实施方式
实施例1:
以下请参照图1G,说明根据本发明的具应变通道的互补式金氧半导体的一较佳实施例。
其主要是包括:一半导体基底100、复数沟槽隔离区104a、104b、一氮化物衬垫层108、一离子布植氮化物衬垫层108a、一N型通道晶体管117以及一P型通道晶体管116。
其中,沟槽隔离区104a、104b设置于半导体基底100内,且相邻两沟槽隔离区104a、104b之间各定义出一主动区,而主动区包括一N型主动区(n-井)与一P型主动区(p-井)。沟槽隔离区104a、104b内填满隔离氧化物112。
另外,氮化物衬垫层108顺应性设置于N型主动区(n-井)两侧的沟槽隔离区104b与半导体基底100之间。氮化物衬垫层108的设置为本发明的特征之一。氮化物衬垫层108可用以阻挡后续填充于浅沟槽隔离区的氧化物112扩散,进而避免隔离氧化物112体积膨胀,并且氮化物衬垫层本身具有拉伸应力(intrinsic tensile stress),导致对沟槽104b的侧壁施加一垂直压缩应力(vertical compressive stress)以及可提供N型晶体管117的半导体基底100通道区形成一拉伸应力。
再者,离子布植氮化物衬垫层108a顺应性设置于P型主动区(p-井)两侧的沟槽隔离区104a与半导体基底100之间。离子布植氮化物衬垫层108a内具有缺陷,有利于后续填充于浅沟槽隔离区的氧化物扩散,造成体积膨胀,以于P型晶体管116的半导体基底100通道区形成一压缩应力。
并且,N型通道晶体管117设置于N型主动区(n-井)上方。以及,P型通道晶体管116,设置于P型主动区(p-井)上方。如此一来,N型信道晶体管117下方的信道区具有一拉伸应力,可提升电子迁移率。P型信道晶体管116下方的信道区具有一压缩应力,可提升电洞迁移率。
实施例2:
以下请配合参考图1A至图1H的制程剖面图,说明根据本发明的实施例1的具应变通道的互补式金氧半导体的制作方法。
首先,请参照图1A,提供一半导体基底100,其包括:一硅基底、堆栈的一硅层与一硅锗层或是堆栈的一第一硅基底、一埋入绝缘层与一第二硅基底,即所谓的绝缘层上覆硅(silicon-on-insulator;SOI),甚至可以是包含砷化镓或磷化铟的化合物。
接着,请参照图1B,形成复数沟槽104a、104b于半导体基底100内。例如先形成一图案化罩幕层102于半导体基底100表面,然后利用适当蚀刻法,例如:非等向性电浆蚀刻法(anisotropic plasma etching),该电浆可以为含氟化学物质,较佳为CF4,透过图案化罩幕层102以形成复数沟槽104a、104b,使得相邻两沟槽104a、104b之间各定义出一主动区。本发明是强调应用于CMOS组件,所以图式中主动区包括一N型主动区(n-井)与一P型主动区(p-井)。N型主动区(n-井)与P型主动区(p-井)是分别以掺杂不同导电型态的掺杂物于半导体基底100内所形成。沟槽隔离区104a、104b的厚度大体为2000-6000。图案化罩幕层102的材质可包括:氧化硅、氮化硅或是堆栈的氧化硅与氮化硅,其中以堆栈的氧化硅与氮化硅为较佳。
接着,请参照图1C,先例如以热氧化法(thermal oxidation)于温度约600-1000℃下通入水气与氧气,或是直接以化学气相沉积法(CVD),顺应性形成一氧化物衬垫层106于沟槽104a、104b的侧壁与底部表面。接着,在例如以适当的化学气相沉积法(chemical vapor deposition;CVD)顺应性形成一氮化物衬垫层108于氧化物衬垫层106表面,使得氧化物衬垫层106在沟槽104a、104b内夹设于氮化物衬垫层108与半导体基底100之间。氧化物衬垫层106不仅可以增加氮化物衬垫层108的附着力,更可以缓冲以化学气相沉积(CVD)形成氮化物衬垫层108时对半导体基底100所造成的损伤。其中,形成氮化物衬垫层108的反应性气体可包括氨(ammonia)与烷类(silane)。
接着,请再参照图1D,形成一离子布植罩幕110于整个N型主动区(n-井)上方,其材质例如为光阻(photoresist)。然后,以离子布植罩幕110为遮蔽,实施一离子布植程序S100于P型主动区(p-井)两侧的氮化物衬垫层108内,也就是沟槽104b中的氮化物衬垫层108内。离子布植程序S100可以为传统的束线离子布植程序(beam-line ion implantationprocess),也可以是电浆入浸离子布植(plasma immersion ionimplantation;PIII),或是任何其它习知的离子布植程序,离子布植S100可包括:硅(Si)离子、氮(N)离子、氦(He)离子、氖(Ne)离子、氩(Ar)、氙(Xe)或锗离子,其剂量约为每平方公分下1E13-1E16个离子量,施加能量约为10eV-100keV。氮化物衬垫层108被施加离子布植之后会增加其内部的缺陷,使得不仅其本身的应例会降低,更可使后续填充于沟槽的隔离物容易扩散,进而造成体积膨胀,以至于对P型主动区(p-井)的半导体基底100表层(即通道区)形成一压缩应力。
接着,请再参照图1E,先以适当腐蚀溶液将离子布植罩幕110移除,再形成隔离物112以填满沟槽104a、104b。隔离物112的材质可以包括氧化物,例如氧化硅,或是由氧化硅与多晶硅的组合所构成。然后再以化学机械研磨法(chemical mechanical polishing;CMP)使隔离物112表面平坦化,以完成浅沟槽隔离区(shallow trench isolation;STI)的制作。
接着,请参照图1F,再以适当腐蚀溶液移除图案化罩幕层102,当图案化罩幕层102的材质包括氧化硅与氮化硅时,较佳实施例为先以热磷酸溶液去除氮化硅,再以稀释氢氟酸去除氧化硅。
接着,请参照图1G,分别形成一N型通道晶体管117于N型主动区(n-井)上方以及形成一P型通道晶体管116于P型主动区(p-井)上方。先于N型主动区(n-井)与P型主动区(p-井)的半导体基底100表面形成栅极介电层114,栅极介电层114例如为氧化硅层,其形成方法例如是利用化学气相沉积法(CVD)、热氧化法(thermal oxidation)、氮化法(nitridation)、溅镀法(sputtering)或是任何习知形成栅极介电层的方法,其材质可包括氧化硅、氮化硅、氮氧化硅,其厚度约为3-100,或是其它高介电常数(high permittivity;high-k)材质,包括:氧化铝(Al2O3)、氧化铪(HfO2)、氮氧化铪(HfON)、硅烷化铪(HfSiO4)、硅烷化锆(ZrSiO4)、氧化镧(La2O3)等,其等效氧化物厚度(equivalent oxidethickness;EOT)约为3-100,其中栅极介电层114的材质以氮氧化硅为较佳。然后,再于栅极介电层114表面形成一栅极层115,栅极层115知材质包括:多晶硅、多晶硅锗、金属化合物包含:钼(Mo)、钨(W)或氮化钛(TiN),抑或者是其它导电材质,以多晶硅为较佳。栅极介电层114与栅极层115共同构成一栅极结构116、117。然后再利用一罩幕采用选择性蚀刻,图案化栅极介电层114与栅极层115,以定义出栅极结构116、117的图案。并分别于栅极结构116、117两侧的N型主动区(n-井)与P型主动区(p-井)进行n型和p型离子掺杂,以及于栅极结构116、117的侧壁形成间隙壁118,间隙壁118的材质例如为氮化硅或氧化硅。然后再例如利用离子布植法于间隙壁118外侧的半导体基底100内形成漏极/源极。这些晶体管的制成可以根据任何习知半导体晶体管制造技术加以被制,在此并不加限制与赘述。
如此,在半导体基底100上,便形成N型通道晶体管117于具有拉伸应力的通道区上方,拉伸应变通道区的拉伸应变量大体为0.1%-2%,且形成P型通道晶体管116于具有压缩应力的通道区上方,压缩应变通道区的拉伸应变量大体为0.1%-2%。如此一来,N型信道晶体管117下方的信道区具有一拉伸应力,可提升电子迁移率。P型信道晶体管116下方的信道区具有一压缩应力,可提升电洞迁移率。
请参照图1H,N型通道晶体管117与P型通道晶体管116表面更可以分别以化学气相沉积法(chemical vapor deposition;CVD)覆盖一应力膜122、120,加以提供适当的应力。
实施例3:
以下请参照图2G,说明根据本发明的具应变通道的互补式金氧半导体的一较佳实施例。
其主要是包括:一半导体基底200、复数沟槽隔离区204a、204b、一氮化物衬垫层208、一N型通道晶体管217以及一P型通道晶体管216。
其中,沟槽隔离区204a、204b设置于半导体基底200内,且相邻两沟槽隔离区204a、204b之间各定义出一主动区,而主动区包括一N型主动区(n-井)与一P型主动区(p-井)。沟槽隔离区204a、204b内填满隔离氧化物212。
另外,氮化物衬垫层208顺应性设置于N型主动区(n-井)两侧的沟槽隔离区204b与半导体基底200之间。氮化物衬垫层208的设置为本发明的特征之一。氮化物衬垫层208可用以阻挡后续填充于浅沟槽隔离区的氧化物212扩散,进而避免隔离氧化物212体积膨胀,并且氮化物衬垫层208本身具有拉伸应力(intrinsic tensile stress),导致对沟槽204b的侧壁施加一垂直压缩应力(vertical compressive stress)以及可提供N型晶体管217的半导体基底200通道区形成一拉伸应力。
然而,沟槽204a内并无氮化物衬垫层,后续填充于浅沟槽隔离区的氧化物会发生扩散,造成体积膨胀,以于P型晶体管216的半导体基底200通道区形成一压缩应力。
并且,N型通道晶体管217设置于N型主动区(n-井)上方。以及,P型通道晶体管216,设置于P型主动区(p-井)上方。如此一来,N型信道晶体管217下方的信道区具有一拉伸应力,可提升电子迁移率。P型信道晶体管216下方的信道区具有一压缩应力,可提升电洞迁移率。
实施例4:
以下请配合参考图2A至图2H的制程剖面图,说明根据本发明的实施例3的具应变通道的互补式金氧半导体的制作方法之一。
首先,请参照图2A,提供一半导体基底200,其包括:一硅基底、堆栈的一硅层与一硅锗层或是堆栈的一第一硅基底、一埋入绝缘层与一第二硅基底,即所谓的绝缘层上覆硅(silicon-on-insulator;SOI),甚至可以是包含砷化镓或磷化铟的化合物。
接着,请参照图2B,形成复数沟槽204a、204b于半导体基底200内。例如先形成一图案化罩幕层202于半导体基底200表面,然后利用适当蚀刻法,例如:非等向性电浆蚀刻法(anisotropic plasma etching),该电浆可以为含氟化学物质,较佳为CF4,透过图案化罩幕层202以形成复数沟槽204a、204b,使得相邻两沟槽204a、204b之间各定义出一主动区。本发明是强调应用于CMOS组件,所以图式中主动区包括一N型主动区(n-井)与一P型主动区(p-井)。N型主动区(n-井)与P型主动区(p-井)是分别以掺杂不同导电型态的掺杂物于半导体基底200内所形成。沟槽隔离区204a、204b的厚度大体为2000-6000。图案化罩幕层202的材质可包括:氧化硅、氮化硅或是堆栈的氧化硅与氮化硅,其中以堆栈的氧化硅与氮化硅为较佳。
接着,请参照图2C,先例如以热氧化法(thermal oxidation)于温度约600-1000℃下通入水气与氧气,或是直接以化学气相沉积法(CVD),顺应性形成一氧化物衬垫层206于沟槽204a、204b的侧壁与底部表面。接着,在例如以适当的化学气相沉积法(chemical vapor deposition;CVD)顺应性形成一氮化物衬垫层208于氧化物衬垫层206表面,使得氧化物衬垫层206在沟槽204a、204b内夹设于氮化物衬垫层208与半导体基底200之间。氧化物衬垫层206不仅可以增加氮化物衬垫层208的附着力,更可以缓冲以化学气相沉积(CVD)形成氮化物衬垫层208时对半导体基底200所造成的损伤。其中,形成氮化物衬垫层208的反应性气体可包括氨(ammonia)与烷类(silane)。
接着,请再参照图2D,形成一材质例如为光阻的罩幕层210于整个N型主动区(n-井),然后以适当溶液,例如:热磷酸溶液,去除位于P型主动区(p-井)两侧沟槽204a内的氮化物衬垫层208。
接着,请再参照图2E,先以适当腐蚀溶液将罩幕层210移除,再形成隔离物212以填满沟槽204a、204b。隔离物212的材质可以包括氧化物,例如氧化硅,或是由氧化硅与多晶硅的组合所构成。然后再以化学机械研磨法(chemical mechanical polishing;CMP)使隔离物212表面平坦化,以完成浅沟槽隔离区(shallow trench isolation;STI)的制作。
接着,请参照图2F,再以适当腐蚀溶液移除图案化罩幕层202,当图案化罩幕层202的材质包括氧化硅与氮化硅时,较佳实施例为先以热磷酸溶液去除氮化硅,再以稀释氢氟酸去除氧化硅。
接着,请参照图2G,分别形成一N型通道晶体管217于N型主动区(n-井)上方以及形成一P型通道晶体管216于P型主动区(p-井)上方。先于N型主动区(n-井)与P型主动区(p-井)的半导体基底200表面形成栅极介电层214,栅极介电层214例如为氧化硅层,其形成方法例如是利用化学气相沉积法(CVD)、热氧化法(thermal oxidation)、氮化法(nitridation)、溅镀法(sputtering)或是任何习知形成栅极介电层的方法,其材质可包括氧化硅、氮化硅、氮氧化硅,其厚度约为3-100,或是其它高介电常数(high permittivity;high-k)材质,包括:氧化铝(Al2O3)、氧化铪(HfO2)、氮氧化铪(HfON)、硅烷化铪(HfSiO4)、硅烷化锆(ZrSiO4)、氧化镧(La2O3)等,其等效氧化物厚度(equivalent oxidethickness;EOT)约为3-100,其中栅极介电层214的材质以氮氧化硅为较佳。然后,再于栅极介电层214表面形成一栅极层215,栅极层215知材质包括:多晶硅、多晶硅锗、金属化合物包含:钼(Mo)、钨(W)或氮化钛(TiN),抑或者是其它导电材质,以多晶硅为较佳。栅极介电层214与栅极层215共同构成一栅极结构216、217。然后再利用一罩幕采用选择性蚀刻,图案化栅极介电层214与栅极层215,以定义出栅极结构216、217的图案。并分别于栅极结构216、217两侧的N型主动区(n-井)与P型主动区(p-井)进行n型和p型离子掺杂,以及于栅极结构216、217的侧壁形成间隙壁218,间隙壁218的材质例如为氮化硅或氧化硅。然后再例如利用离子布植法于间隙壁218外侧的半导体基底200内形成漏极/源极。这些晶体管的制成可以根据任何习知半导体晶体管制造技术加以被制,在此并不加限制与赘述。
如此,在半导体基底200上,便形成N型通道晶体管217于具有拉伸应力的通道区上方,拉伸应变通道区的拉伸应变量大体为0.1%-2%,且形成P型通道晶体管216于具有压缩应力的通道区上方,压缩应变通道区的拉伸应变量大体为0.1%-2%。如此一来,N型信道晶体管217下方的信道区具有一拉伸应力,可提升电子迁移率。P型信道晶体管216下方的信道区具有一压缩应力,可提升电洞迁移率。
请参照图2H,N型通道晶体管217与P型通道晶体管216表面更可以分别以化学气相沉积法(chemical vapor deposition;CVD)覆盖一应力膜222、220,加以提供适当的应力。
实施例5:
以下请配合参考图3A至图3H的制程剖面图,说明根据本发明的实施例3的具应变通道的互补式金氧半导体的制作方法之二。
首先,请参照图3A,提供一半导体基底300,其包括:一硅基底、堆栈的一硅层与一硅锗层或是堆栈的一第一硅基底、一埋入绝缘层与一第二硅基底,即所谓的绝缘层上覆硅(silicon-on-insulator;SOI),甚至可以是包含砷化镓或磷化铟的化合物。
接着,请参照图3B,形成复数沟槽304a、304b于半导体基底300内。例如先形成一图案化罩幕层302于半导体基底300表面,然后利用适当蚀刻法,例如:非等向性电浆蚀刻法(anisotropic plasma etching),该电浆可以为含氟化学物质,较佳为CF4,透过图案化罩幕层302以形成复数沟槽304a、304b,使得相邻两沟槽304a、304b之间各定义出一主动区。本发明是强调应用于CMOS组件,所以图式中主动区包括一N型主动区(n-井)与一P型主动区(p-井)。N型主动区(n-井)与P型主动区(p-井)是分别以掺杂不同导电型态的掺杂物于半导体基底300内所形成。沟槽隔离区304a、304b的厚度大体为2000-6000。图案化罩幕层302的材质可包括:氧化硅、氮化硅或是堆栈的氧化硅与氮化硅,其中以堆栈的氧化硅与氮化硅为较佳。
接着,请参照图3C,先例如以热氧化法(thermal oxidation)于温度约600-1000℃下通入水气与氧气,或是直接以化学气相沉积法(CVD),顺应性形成一氧化物衬垫层306于沟槽304a、304b的侧壁与底部表面。
接着,请再参照图3D,进行形成氮化物衬垫层308步骤S300。此步骤是本发明的实施例3的结构的制作方法中与前述实施例4主要差异的步骤。先形成一罩幕311于整个P型主动区(p-井)上方,例如以适当的化学气相沉积法(chemical vapor deposition;CVD)、含氮离子布植法或是在含氮气氛下进行退火,抑或是施以含氮电浆处理,顺应性形成一氮化物衬垫层308于N型主动区(n-井)的两侧沟槽304b的氧化物衬垫层306表面,使得氧化物衬垫层306在沟槽304a内夹设于氮化物衬垫层308与半导体基底300之间。氧化物衬垫层306不仅可以增加氮化物衬垫层308的附着力,更可以缓冲以化学气相沉积(CVD)形成氮化物衬垫层308时对半导体基底300所造成的损伤。其中,形成氮化物衬垫层308的反应性气体可包括氨(ammonia)与烷类(silane)。
接着,请再参照图3E,先以适当腐蚀溶液将罩幕层311移除,再形成隔离物312以填满沟槽304a、304b。隔离物312的材质可以包括氧化物,例如氧化硅,或是由氧化硅与多晶硅的组合所构成。然后再以化学机械研磨法(chemical mechanical polishing;CMP)使隔离物312表面平坦化,以完成浅沟槽隔离区(shallow trench isolation;STI)的制作。
接着,请参照图3F,再以适当腐蚀溶液移除图案化罩幕层302,当图案化罩幕层302的材质包括氧化硅与氮化硅时,较佳实施例为先以热磷酸溶液去除氮化硅,再以稀释氢氟酸去除氧化硅。
接着,请参照图3G,分别形成一N型通道晶体管317于N型主动区(n-井)上方以及形成一P型通道晶体管216于P型主动区(p-井)上方。先于N型主动区(n-井)与P型主动区(p-井)的半导体基底300表面形成栅极介电层314,栅极介电层314例如为氧化硅层,其形成方法例如是利用化学气相沉积法(CVD)、热氧化法(thermal oxidation)、氮化法(nitridation)、溅镀法(sputtering)或是任何习知形成栅极介电层的方法,其材质可包括氧化硅、氮化硅、氮氧化硅,其厚度约为3-100,或是其它高介电常数(high permittivity;high-k)材质,包括:氧化铝(Al2O3)、氧化铪(HfO2)、氮氧化铪(HfON)、硅烷化铪(HfSiO4)、硅烷化锆(ZrSiO4)、氧化镧(La2O3)等,其等效氧化物厚度(equivalent oxidethickness;EOT)约为3-100,其中栅极介电层314的材质以氮氧化硅为较佳。然后,再于栅极介电层314表面形成一栅极层315,栅极层315知材质包括:多晶硅、多晶硅锗、金属化合物包含:钼(Mo)、钨(W)或氮化钛(TiN),抑或者是其它导电材质,以多晶硅为较佳。栅极介电层314与栅极层315共同构成一栅极结构316、317。然后再利用一罩幕采用选择性蚀刻,图案化栅极介电层314与栅极层315,以定义出栅极结构316、317的图案。并分别于栅极结构316、317两侧的N型主动区(n-井)与P型主动区(p-井)进行n型和p型离子掺杂,以及于栅极结构316、317的侧壁形成间隙壁318,间隙壁318的材质例如为氮化硅或氧化硅。然后再例如利用离子布植法于间隙壁318外侧的半导体基底300内形成漏极/源极。这些晶体管的制成可以根据任何习知半导体晶体管制造技术加以被制,在此并不加限制与赘述。
如此,在半导体基底300上,便形成N型通道晶体管317于具有拉伸应力的通道区上方,拉伸应变通道区的拉伸应变量大体为0.1%-2%,且形成P型通道晶体管316于具有压缩应力的通道区上方,压缩应变通道区的拉伸应变量大体为0.1%-2%。如此一来,N型信道晶体管317下方的信道区具有一拉伸应力,可提升电子迁移率。P型信道晶体管316下方的信道区具有一压缩应力,可提升电洞迁移率。
请参照图3H,N型通道晶体管317与P型通道晶体管316表面更可以分别以化学气相沉积法(chemical vapor deposition;CVD)覆盖一应力膜322、320,加以提供适当的应力。
发明优点:
1.根据本发明的N型通道晶体管具有拉伸应力而P型通道晶体管具有压缩应力,因此可同时提升N型信道的电子迁移率以及P型通道的电洞迁移率,有效提升组件操作速度。
2.根据本发明的互补式金氧半晶体管(CMOS),以简单的制成方式整合N型信道晶体管与P型信道晶体管于同一芯片,分别有适当可提升操作速度的应力。
Claims (48)
1.一种具应变通道的互补式金氧半导体,其特征在于所述互补式金氧半导体包括:
一半导体基底;
复数沟槽隔离区,设置于上述半导体基底内,使得相邻两上述沟槽隔离区之间各定义出一主动区,其中上述主动区包括一N型主动区与一P型主动区;
一氮化物衬垫层,顺应性设置于上述N型主动区两侧的上述沟槽隔离区与上述半导体基底之间;
一离子布植氮化物衬垫层,顺应性设置于上述P型主动区两侧的上述沟槽隔离区与上述半导体基底之间;
一N型通道晶体管,设置于上述N型主动区上方;以及
一P型通道晶体管,设置于上述P型主动区上方。
2.根据权利要求1所述的具应变通道的互补式金氧半导体,其特征在于:上述沟槽隔离区是由一氧化物所构成。
3.根据权利要求1所述的具应变通道的互补式金氧半导体,其特征在于更包括:一氧化物衬垫层,顺应性设置于上述氮化物衬垫层与上述半导体基底之间。
4.根据权利要求1所述的具应变通道的互补式金氧半导体,其特征在于更包括:一氧化物衬垫层,顺应性设置于上述离子布植氮化物衬垫层与上述半导体基底之间。
5.根据权利要求1所述的具应变通道的互补式金氧半导体,其特征在于:上述氮化物衬垫层是由氮化硅所构成。
6.根据权利要求1所述的具应变通道的互补式金氧半导体,其特征在于:上述离子布植氮化物衬垫层是由被施以离子布植的氮化硅所构成。
7.根据权利要求1所述的具应变通道的互补式金氧半导体,其特征在于上述离子布植氮化物衬垫层所被施加的离子包括:硅(Si)离子、氮(N)离子、氦(He)离子、氖(Ne)离子、氩(Ar)、氙(Xe)或锗离子。
8.根据权利要求1所述的具应变通道的互补式金氧半导体,其特征在于:上述N型主动区的上述半导体基底表层具有一拉伸应变通道区。
9.根据权利要求8所述的具应变通道的互补式金氧半导体,其特征在于:上述拉伸应变通道区的拉伸应变量为0.1%-2%。
10.根据权利要求1所述的具应变通道的互补式金氧半导体,其特征在于:上述P型主动区的上述半导体基底表层具有一压缩应变通道区。
11.根据权利要求10所述的具应变通道的互补式金氧半导体,其特征在于:上述压缩应变通道区的拉伸应变量为0.1%-2%。
12.根据权利要求1所述的具应变通道的互补式金氧半导体,其特征在于上述半导体基底包括:一硅基底、堆栈的一硅层与一硅锗层或堆栈的一第一硅基底、一埋入绝缘层与一第二硅基底。
13.根据权利要求1所述的具应变通道的互补式金氧半导体,其特征在于:上述沟槽隔离区的厚度为2000-6000。
14.一种具应变通道的互补式金氧半导体,其特征在于所述互补式金氧半导体包括:
一半导体基底;
复数沟槽隔离区,设置于上述半导体基底内,使得相邻两上述沟槽隔离区之间各定义出一主动区,其中上述主动区包括一N型主动区与一P型主动区;
一氮化物衬垫层,顺应性设置于上述N型主动区两侧的上述沟槽隔离区与上述半导体基底之间;
一N型通道晶体管,设置于上述N型主动区上方;以及
一P型通道晶体管,设置于上述P型主动区上方。
15.根据权利要求14所述的具应变通道的互补式金氧半导体,其特征在于:上述沟槽隔离区是由一氧化物所构成。
16.根据权利要求14项所述的具应变通道的互补式金氧半导体,其特征在于更包括:一氧化物衬垫层,顺应性设置于上述氮化物衬垫层与上述半导体基底之间。
17.根据权利要求14所述的具应变通道的互补式金氧半导体,其特征在于:上述氮化物衬垫层是由氮化硅所构成。
18.根据权利要求14所述的具应变通道的互补式金氧半导体,其特征在于:上述N型主动区的上述半导体基底表层具有一拉伸应变通道区。
19.根据权利要求18所述的具应变通道的互补式金氧半导体,其特征在于:上述拉伸应变通道区的拉伸应变量为0.1%-2%。
20.根据权利要求14所述的具应变通道的互补式金氧半导体,其特征在于:上述P型主动区的上述半导体基底表层具有一压缩应变通道区。
21.根据权利要求20所述的具应变通道的互补式金氧半导体,其特征在于:上述拉伸应变通道区的拉伸应变量为0.1%-2%。
22.根据权利要求14所述的具应变通道的互补式金氧半导体,其中上述半导体基底包括:一硅基底、堆栈的一硅层与一硅锗层或堆栈的一第一硅基底、一埋入绝缘层与一第二硅基底。
23.根据权利要求14所述的具应变通道的互补式金氧半导体,其特征在于:上述沟槽隔离区的厚度为2000-6000。
24.一种具应变通道的互补式金氧半导体的制作方法,包括:
提供一半导体基底;
形成复数沟槽于上述基底内,使得相邻两上述沟槽之间各定义出一主动区,其中上述主动区包括一N型主动区与一P型主动区;
顺应性形成一氮化物衬垫层,于各上述沟槽的侧壁与底部;
实施一离子布植于上述P型主动区两侧的上述氮化物衬垫层内;
形成复数沟槽隔离物,以填满各上述沟槽;
形成一N型通道晶体管于上述N型主动区上方;以及
形成一P型通道晶体管于上述P型主动区上方。
25.根据权利要求24所述的具应变通道的互补式金氧半导体的制作方法,其中上述沟槽隔离物是由一氧化物所构成。
26.根据权利要求24所述的具应变通道的互补式金氧半导体的制作方法,其中形成上述氮化物衬垫层之前更包括:顺应性形成一氧化物衬垫层于各上述氮化物衬垫层与上述半导体基底之间。
27.根据权利要求24所述的具应变通道的互补式金氧半导体的制作方法,其中上述氮化物衬垫层是由氮化硅所构成。
28.根据权利要求24所述的具应变通道的互补式金氧半导体的制作方法,其中上述离子布植所施加的离子包括:硅(Si)离子、氮(N)离子、氦(He)离子、氖(Ne)离子、氩(Ar)、氙(Xe)或锗离子。
29.根据权利要求24所述的具应变通道的互补式金氧半导体的制作方法,其中上述N型主动区的上述半导体基底表层具有一拉伸应变通道区。
30.根据权利要求29所述的具应变通道的互补式金氧半导体的制作方法,其中上述拉伸应变通道区的拉伸应变量为0.1%-2%。
31.根据权利要求24所述的具应变通道的互补式金氧半导体的制作方法,其中上述P型主动区的上述半导体基底表层具有一压缩应变通道区。
32.根据权利要求31所述的具应变通道的互补式金氧半导体的制作方法,其中上述压缩应变通道区的拉伸应变量为0.1%-2%。
33.根据权利要求24所述的具应变通道的互补式金氧半导体的制作方法,其中上述半导体基底包括:一硅基底、堆栈的一硅层与一硅锗层或堆栈的一第一硅基底、一埋入绝缘层与一第二硅基底。
34.根据权利要求24所述的具应变通道的互补式金氧半导体的制作方法,其中上述沟槽的厚度为2000-6000。
35.根据权利要求24所述的具应变通道的互补式金氧半导体的制作方法,其中形成上述N型通道晶体管与上述P型通道晶体管之后更包括:分别形成一应力膜,覆盖于上述N型通道晶体管与上述P型通道晶体管表面。
36.根据权利要求24所述的具应变通道的互补式金氧半导体的制作方法,其中上述应力膜是由化学气相沉积法(chemical vapordeposition;CVD)所形成。
37.一种具应变通道的互补式金氧半导体的制作方法,包括:
提供一半导体基底;
形成复数沟槽于上述基底内,使得相邻两上述沟槽之间各定义出一主动区,其中上述主动区包括一N型主动区与一P型主动区;
顺应性形成一氮化物衬垫层,于上述N型主动区两侧的各上述沟槽的侧壁与底部;
形成复数沟槽隔离物,以填满各上述沟槽;
形成一N型通道晶体管于上述N型主动区上方;以及
形成一P型通道晶体管于上述P型主动区上方。
38.根据权利要求37所述的具应变通道的互补式金氧半导体的制作方法,其中上述沟槽隔离物是由一氧化物所构成。
39.根据权利要求37所述的具应变通道的互补式金氧半导体的制作方法,其中形成上述氮化物衬垫层之前更包括:顺应性形成一氧化物衬垫层于各上述氮化物衬垫层与上述半导体基底之间。
40.根据权利要求37所述的具应变通道的互补式金氧半导体的制作方法,其中上述氮化物衬垫层是由氮化硅所构成。
41.根据权利要求37所述的具应变通道的互补式金氧半导体的制作方法,其中上述N型主动区的上述半导体基底表层具有一拉伸应变通道区。
42.根据权利要求41所述的具应变通道的互补式金氧半导体的制作方法,其中上述拉伸应变通道区的拉伸应变量为0.1%-2%。
43.根据权利要求37所述的具应变通道的互补式金氧半导体的制作方法,其中上述P型主动区的上述半导体基底表层具有一压缩应变通道区。
44.根据权利要求43所述的具应变通道的互补式金氧半导体的制作方法,其中上述压缩应变通道区的拉伸应变量为0.1%-2%。
45.根据权利要求37所述的具应变通道的互补式金氧半导体的制作方法,其中上述半导体基底包括:一硅基底、堆栈的一硅层与一硅锗层或堆栈的一第一硅基底、一埋入绝缘层与一第二硅基底。
46.根据权利要求37所述的具应变通道的互补式金氧半导体的制作方法,其中上述沟槽的厚度为2000-6000。
47.根据权利要求37所述的具应变通道的互补式金氧半导体的制作方法,其中形成上述N型通道晶体管与上述P型通道晶体管之后更包括:分别形成一应力膜,覆盖于上述N型通道晶体管与上述P型通道晶体管表面。
48.根据权利要求37所述的具应变通道的互补式金氧半导体的制作方法,其中上述应力膜是由化学气相沉积法(chemical vapordeposition;CVD)所形成。
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CN105321943A (zh) * | 2014-08-05 | 2016-02-10 | 台湾积体电路制造股份有限公司 | 非平面器件和应变产生沟道电介质 |
CN105321943B (zh) * | 2014-08-05 | 2019-04-05 | 台湾积体电路制造股份有限公司 | 非平面器件和应变产生沟道电介质 |
CN105914206A (zh) * | 2015-02-24 | 2016-08-31 | 三星电子株式会社 | 集成电路器件及其制造方法 |
CN105914206B (zh) * | 2015-02-24 | 2019-07-05 | 三星电子株式会社 | 集成电路器件及其制造方法 |
CN109616446A (zh) * | 2018-12-10 | 2019-04-12 | 德淮半导体有限公司 | 半导体装置的制造方法 |
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US6882025B2 (en) | 2005-04-19 |
TW200423306A (en) | 2004-11-01 |
US7052964B2 (en) | 2006-05-30 |
CN1293637C (zh) | 2007-01-03 |
US20050156274A1 (en) | 2005-07-21 |
TWI222715B (en) | 2004-10-21 |
US20040212035A1 (en) | 2004-10-28 |
SG115690A1 (en) | 2005-10-28 |
CN2751444Y (zh) | 2006-01-11 |
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