CN1670965A - 源极及漏极中聚含掺质金属的晶体管 - Google Patents
源极及漏极中聚含掺质金属的晶体管 Download PDFInfo
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Abstract
本发明关于一种晶体管及其制造方法。一栅极介电质与栅极系形成于一工作部件上,且一晶体管的源极与漏极区域是嵌壁式的,填充一含掺质金属于凹槽中,并利用一低温退火过程来形成掺杂区域于与该含掺质金属区域相邻的工作部件中,进而形成一种具有较小的有效氧化物厚度与良好控制的接合深度的晶体管。
Description
技术领域
本发明一般是关于半导体装置,且特别是关于一种晶体管的制造方法及其结构。
背景技术
半导体装置可应用于多种电子领域之应用中,例如个人计算机、行动电话、数字相机、以及其它的电子设备等;而在半导体装置中广泛使用的组件则为晶体管,举例而言,在一个单一集成电路上便具有百万个晶体管。在半导体装置制造中所使用之最常见的晶体管类型则为金属氧化物半导体场效晶体管(金氧半场效晶体管,MOSFET)。
在过去,MOSFET装置之栅极介电质一般包含二氧化硅,然而随着装置尺寸减小,二氧化硅则因栅极泄漏电流而成为导致装置性能降低的一个问题;因此,在工业应用上便朝向于使用具有高介电常数(k)之材料(例如介电常数高于3.9或更大者),来作为MOSFET装置中的栅极介电质。
在国际半导体技术蓝图(ITRS,International TechnologyRoadmap for Semiconductor)2003年发行版本中认定了高介电常数(k)之栅极介电质的发展是重大挑战之一;在此,该发行版本亦列为本发明之参考文献,其认定了技术挑战以及在未来15年中所需要面对的半导体工业。对于低功率逻辑(例如可携式电子产品)而言,为了延长电池的使用寿命而使用具有低泄漏电流的装置是很重要的,栅极泄漏电流与次要临界泄漏、接合泄漏以及价带-至-价带穿隧一样,都必须于低功率应用中加以控制。对于高性能(亦及高速)应用而言,具有一低片状电阻(sheet resistance)与最小有效栅极氧化物厚度则是非常重要的。
为了完全实现减小晶体管尺寸的效益,需将该栅极氧化物厚度减小至低于2nm;然而,在许多要求低备用功率消耗之装置应用中,其所导致的栅极泄漏电流使得如此薄的氧化物无法被使用;因此,无可避免地必须使用一个具有更高介电常数的替代介电质材料来取代原有的栅极氧化物介电质材料。然而,使用高介电常数(k)介电质材料之装置性能亦受到介电层中捕捉之电荷的影响,其降低了电荷移动率,并使得其驱动电流较具有二氧化硅栅极氧化物者为低,因而降低了具有高介电常数(k)栅极介电质材料之晶体管的速度与性能。
图1为一习知之半导体装置的截面图,该半导体装置100包含了一具有高介电常数(k)栅极介电质材料之晶体管。该半导体装置100具有形成于一工作部件102中之场效氧化物区域104;该晶体管包含了由一信道区域C隔开之一源极S与一漏极D,该晶体管包含一栅极介电质108,其含有一高介电常数(k)绝缘材料;一栅极110则形成于该栅极介电质108上,如图中所示。
在形成该栅极110后,便对该源极区域S与该漏极区域D进行轻微掺杂,例如利用一轻微掺杂之漏极(LDD)布植,以形成该源极S与漏极D之延伸区域128。接着,沿着该栅极110与该栅极介电质108之侧壁形成绝缘间隙物112,并于该工作部件102的暴露表面上施行一源极/漏极布植,并接着执行一高温热退火(执行之一般温度约为1000至1015℃),以形成该源极S与该漏极D。
图1所示之习知半导体装置100的问题在于该工作部件102与该高介电常数(k)介电质108间所形成的一接口氧化物114,以及在该介电常数(k)介电质108与该栅极110间所形成的一接口氧化物116。该等接口氧化物114与116之形成原因在于,举例而言,在沉积该高介电常数(k)介电质108期间,该工作部件102中所含的硅一般会在氧存在时具有形成二氧化硅的高度趋势,因而形成了该介电氧化物114。同样的,该栅极110通常包含了多晶硅,其亦趋向于形成二氧化硅116于该高介电常数(k)介电质108之顶部表面上。
该半导体装置100的该源极S与该漏极D区域之形成是藉由布植一掺杂物种之离子以及对该工作部件102退火以使掺杂物扩散于该工作部件102内之深处,而形成该源极S与该漏极D区域。此习知之结构100的问题在于用以形成该源极S与该漏极D之高温退火过程会降低该高介电常数(k)栅极介电质108之介电常数,特别是,当暴露于一高温处理时,该等接口氧化物114与116会变得更厚,其增加了从该半导体装置100之整体栅极堆栈(该接口氧化物114、该高介电常数(k)介电质108与该接口氧化物116)所电性评估之有效氧化物厚度(EOT)118;因此,使用一高介电常数(k)介电质作为该栅极介电质108,在减小该装置100之尺寸时,便难以将该栅极介电质108厚度降低至该晶体管设计所需之厚度。
图1所示之习知半导体装置100所具有的另一问题为,由于该源极S与该漏极D是利用离子布植而形成,因此难以符合先进技术所需之较小的接合深度Xj与片状电阻Rs;该接合深度Xj越厚,便会产生更多的短信道效应,例如热载子效应会变得严重并降低晶体管的可靠度,导致源极S与漏极D泄漏及/或击穿(punch-through)现象。此外,该装置100具有高片状电阻Rs,其降低了驱动电流与电路速度,因而使得该半导体装置100必须降低可靠度以使用于高性能及/或高速度之应用。
因此,在此领域中需要一种晶体管设计与制造方法,其降低了栅极介电质厚度、接合深度与片状电阻。
发明内容
上述之各种问题以及其它可能的问题皆可藉由本发明之较佳实施例而解决或加以避免,且藉由本发明亦实现了技术上的优势;本发明包含了一种晶体管,其具有的源极与漏极区域包含一含掺质金属,且利用一低温退火过程来使得该含掺质金属中的掺杂物扩散至与该含掺质金属相邻的工作部件中,而形成掺杂区域。该等掺杂区域与该含掺质金属包含了晶体管之源极与漏极。由于该掺杂区域是利用低温退火过程而形成,因而在低温退火过程中,栅极介电质的有效氧化物厚度并不会增加,因而可形成较薄的有效栅极介电质(或氧化物)厚度;此外,低温退火过程亦可产生一较低的接合深度。
根据本发明之一较佳实施例,一晶体管包含了一源极与一漏极,其位于一工作部件中;该工作部件具有一顶部表面,该源极与该漏极是由一信道区域所分隔。该源极与漏极各包含一含掺质金属区域与一掺杂区域,该含掺质金属区域是位于该工作部件的该顶部表面内,而该掺杂区域是位于与各含掺质金属区域相邻之该工作部件中。一栅极介电质是位于该信道区域与该源极与该漏极的一部份上。一栅极是位于该栅极介电质上。
根据本发明之另一较佳实施例,一晶体管包含了一源极,其位于一工作部件中,该工作部件具有一顶部表面。该源极包含一第一含掺质金属区域与一第一掺杂区域,该第一含掺质金属区域是位于该工作部件的该顶部表面内,而该第一掺杂区域是位于与该第一含掺质金属区域相邻之该工作部件中。一漏极是位于该工作部件中,该漏极是藉由一信道区域而自该源极分隔,其中该漏极包含一第二含掺质金属区域与一第二掺杂区域,该第二含掺质金属区域是位于该工作部件的该顶部表面内,而该第二掺杂区域是位于与该第二含掺质金属区域相邻之该工作部件中。一栅极介电质是位于该信道区域与该源极与该漏极的一部份上。一栅极是位于该栅极介电质上。
根据本发明之又一较佳实施例,一种用以制造一晶体管之方法包含了提供一工作部件;沉积一栅极介电质材料于该工作部件上;以及沉积一栅极材料于该栅极介电质材料上;对该栅极材料与栅极介电质材料加以图样化,以形成一栅极与一栅极介电质于该工作部件之一信道区域上;一第一凹槽是形成于该工作部件之一源极区域中,而一第二凹槽是形成于该工作部件之一漏极区域中,该源极区域与该漏极区域是彼此近似且由该信道区域分隔。该方法包含了填充一含掺质金属于该第一凹槽与该第二凹槽中;以及退火该工作部件以使该含掺质金属之一掺杂物扩散至该工作部件中,并于该源极区域与该漏极区域中与该含掺质金属相邻之该工作部件中形成一掺杂区域。
本发明之较佳实施例的优势包含了其提供一种晶体管设计及其制造方法,其降低了在该晶体管制造过程中所需之整体退火温度,减少了热预算(thermal budget)并提升了该栅极介电质的性能。在该源极与漏极延伸区域中的片状电阻非常低,且由于凹槽的形成,使得接合深度能够被良好控制;在该源极与漏极区域中,亦可形成具有陡峭边缘之接合。由于在该含掺质金属区域下方的掺杂区域是形成于一低温条件,因而掺杂物较不会扩散至该工作部件中,可产生一较薄的接合深度、较低的片状电阻以及较小的有效氧化物厚度。
以上已列明本发明之特征以及其实施例的技术优势,以使下述之本发明详细说明得以被了解;本发明实施例的其它特征与优势将说明如下,其形成了本发明之权利要求标的。本发明得由熟悉技艺之人任施匠思而为诸般修饰,然不脱如附申请范围所欲保护者。
附图说明
为使本发明以及其优势能够完全被了解,本发明将参考下列描述并配合伴随之图式加以说明,其中:
图1为一习知晶体管之截面图;
图2至图8为根据本发明之一较佳实施例中各个不同制造阶段的晶体管之截面图,其中源极与漏极区域是位于凹槽中且以一含掺质金属加以填充,并接着执行一低温退火过程;
图9为根据本发明之一较佳实施例之截面图,其中深源极与漏极区域是在形成该含掺质金属源极与漏极区域后,藉由离子布植与热退火而形成;
图10与图11为根据本发明之另一较佳实施例之截面图,其中一侧壁间隙物是在形成该含掺质金属之凹槽前,即形成于该栅极介电质与该栅极上;
图12为根据本发明之一实施例之截面图,其中一侧壁间隙物是形成于该源极与漏极区域中的凹槽形成之前,且同样形成深源极与漏极区域,如图9所示之实施例所示。
除非另外说明,在不同的图式中对应的组件符号一般皆指相同的对应部分。该等图式是基于清楚表达本发明之实施例而绘制,并不代表其实际尺寸。
具体实施方式
以下将详细说明本发明之各较佳实施例,然而,此处之实施例仅为说明本发明之概念可实施于多种应用中而提出,该等特定实施例仅用以说明如何利用并制造本发明,而非用以限制本发明之范畴。
本发明将以一特定背景(亦即一半导体装置上之一晶体管)来说明其较佳实施例;然而,本发明亦可应用于MOSFETs或是其它的晶体管装置,包含了例如p型信道金属氧化物半导体晶体管(PMOS)、n型信道金属氧化物半导体晶体管(NMOS)、及/或补偿型金属氧化物半导体晶体管(CMOS)装置。在该等图式中仅说明一种晶体管,然而在所示之半导体装置的制造过程中亦可形成多种其它的晶体管或装置。
图2至图8为根据本发明之一较佳实施例中各个不同制造阶段的晶体管之截面图。首先参考图2,一半导体装置200包含一工作部件202,该工作部件202可包含一半导体基板,举例而言,该半导体基板含有以一绝缘层覆盖之硅或其它的半导体材料;举例而言,该工作部件202可包含二氧化硅于单晶硅上。该工作部件202包含了其它的传导层或其它的半导体组件,例如:晶体管、二极管等等;亦可使用化合物半导体(例如:GaAs、InP、Si/Ge或SiC)来取代硅;举例而言,该工作部件202亦可包含一绝缘层上覆硅(SOI)基板。
该工作部件202可经轻微掺杂(图中未示);一般而言,该工作部件系以N型或P型掺杂物加以掺杂,其端视于该晶体管之接合分别是P型接合或是N型接合。举例而言,若该等晶体管欲被制造为PMOS晶体管,则该工作部件202可轻微掺杂一N型掺杂物;而若欲形成NMOS晶体管,则该工作部件202可轻微掺杂一P型掺杂物。
如图中所示,在该工作部件202上的多个位置中形成有隔离区域204,该等隔离区域204可包含浅沟渠绝缘区域(STI)或场效氧化物区域,举例而言,其位于一晶体管230之一信道区域C(未示于图2,见图8)的任一侧。该等隔离区域204可藉由沉积一光阻质于该工作部件202上而形成(图中未示),利用一光微影技术图样化(pattern)该光阻质,且利用该光阻质作为一罩幕(mask),以供对该工作部件202蚀刻以形成孔洞或是在该工作部件202之一顶部表面中图样化该等隔离区域204时之用。举例而言,一绝缘层(例如一氧化物)则沉积于该工作部件202上以填充该等图形而形成隔离区域204;另外,亦可利用其它的替代方法来形成该等隔离区域204。
须注意的是,若要在同一工作部件202上形成PMOS与NMOS(图中未示),则可对该工作部件202轻微掺杂一P型掺杂物,且遮蔽该工作部件202的NMOS部分,则可接着形成井掺杂以产生该PMOS装置之N型井;接着则布植P型掺杂物至该NMOS部份中。
一栅极介电质材料208则沉积于该工作部件202上,如图2所示。该栅极介电质208可包含传统作为栅极介电质的绝缘材料,例如二氧化硅(SiO2)、氮化硅(SixNy)、或氮氧化硅(SiON);然而,本发明之实施例之特别优势在于使用一高介电常数(k)材料来作为该栅极介电质材料208,因此在一实施例中,该栅极介电质材料208最好是包含一高介电常数材料,例如:HfO2、HfSiOx、Al2O3、ZrO2、ZrSiOx、Ta2O5、La2O3等,此外,该栅极介电质材料208亦可包含其它的低介电常数(k)或高介电常数(k)绝缘材料。
该栅极介电质材料208可包含一单一层之材料,或是亦可包含两层或多层之材料;在一实施例中,在不同组合或堆栈层中的该栅极介电质材料208可包含该等材料中的一或多种,举例而言,该栅极介电质材料208可藉化学气相沉积(CVD,chemical vapor deposition)、原子层沉积(ALD,atomic layer deposition)、金属有机化学气相沉积(MOCVD,metal organic chemical vapor deposition)、物理气相沉积(PVD,physical vapor deposition)、喷射气相沉积(JVD,jetvapor deposition)等方式沉积而成,且亦可使用其它合适的沉积技术来沉积该栅极介电质材料208。在一实施例中,该栅极介电质材料208最好是具有一约为10至70的厚度,亦可具有其它尺寸之厚度,例如80或低于80;在沉积该栅极介电质材料208之前,该工作部件202可随意暴露于一预栅极处理(图中未示)中,例如:HF、HCl或基于臭氧之清洁处理。
一栅极材料210则沉积于该栅极介电质材料208上,该栅极材料210最好是包含一导体,例如金属或多晶硅,或是亦可使用其它的传导性与半导性材料作为该栅极材料210;举例而言,该栅极材料210可包含TiN、HfN、TaN、硅化物栅极材料(FUSI)、或其它金属。该栅极材料210可包含复数之堆栈栅极材料,例如一金属底层与位于该金属底层上方之一多晶硅盖层,或是由复数之金属层的组合所形成的一栅极电极堆栈;另外,在另一实施例中,该栅极材料210可包含多晶硅或其它的半导体材料。举例而言,该栅极材料210可藉由CVD、PVD、ALD、或是其嘎得沉积技术沉积而成。
该栅极材料210与该栅极介电材料208是利用光微影技术而图样化,以形成一晶体管之栅极210与栅极介电植208,如图3所示。举例而言,沉积一光阻质(图中未示)于该工作部件202上,并以该栅极与该栅极介电质所需之一图形来图样化该光阻质,以供对该栅极材料210与该栅极介电质材料208进行蚀刻以形成该栅极210与该栅极介电质208于一所须图形时之用;接着便使该光阻质成为条状或加以移除。
须注意的是,在该栅极介电质材料208之沉积期间,或是在沉积该栅极介电质材料208之前的清洁处理(例如一湿式预清洁)期间,亦可形成一薄接口层220,该薄接口层220是藉由该工作部件202中的硅或其它半导体材料与该栅极介电质材料208或预清洁过程中的氧化物反应而形成。
接着,根据本发明之一较佳实施例,在该工作部件202上形成凹槽于该源极S与该漏极D区域中,如图4所示。举例而言,该源极S区域与该漏极D区域可藉由一含氩之干式蚀刻过程而形成凹槽,亦可使用其它的蚀刻化学物来形成凹槽。举例而言,在一实施例中,该蚀刻过程最好是异向性蚀刻,以避免减少了该栅极210与该栅极介电层208之水平尺寸(例如侧向蚀刻)。此外,用以形成凹槽之蚀刻过程亦可包含一等向性蚀刻,例如所谓之“化学下游蚀刻(chemical downstreametching)”,该技术应用微波等离子体源、低偏压RF功率、或其组合,以等向地对该工作部件202中的硅形成凹槽而选择性成为该隔离氧化物204;另外,亦可使用替代之其它等向蚀刻过程。举例而言,在该源极S与该漏极D区域中的该等凹槽之深度h1最好是位于该工作部件202的顶部表面222下方约200或低于200;较佳为,该源极S区域与漏极D区域是在一单一处理步骤中形成凹槽,换言之,即两者同时形成凹槽;举例而言,该源极S区域与该漏极D区域亦可藉由一额外的独立蚀刻过程而形成凹槽,或是在该栅极210与该栅极介电质208图样化过程中对该源极S区域与该漏极D区域形成凹槽。
如图5所示,一含掺质金属224系沉积于该工作部件202的暴露部分、该栅极210的顶部表面以及隔离区域204上;该含掺质金属224最好是包含一金属,其含有例如硼(B)、磷(P)、砷(As)、或锑(Sb)等掺杂物,此外该掺杂物亦可包含其它的掺杂材料;举例而言,该含掺质金属224可包含TiB2、ZrB2、HfB2、ZrP、TiP、ZrSb2、TiSb2、HfSb2、或是含Zr或Hf之砷化物;此外,该含掺质金属224亦包括含有掺杂物之其它金属。
该含掺质金属224的金属部分(例如Ti、Zr、Hf)可使该源极S与该漏极D具有一较低的片状电阻Rs,且其掺杂部分(例如B、P、Sb、As)可产生该源极S与漏极D之接合。较佳为,根据本发明之实施例,可选择该含掺质金属224以提供该半导体装置200一较低片状电阻Rs。
该源极S与该漏极D区域中的凹槽最好是以该含掺质金属224加以回填,举例而言,该含掺质金属224可藉由电子束蒸镀(electronbeam evaporation)、CVD、或物理气相沉积方式沉积而成,此外,亦可使用其它的沉积方法来沉积该含掺质金属224。
如图5所示,在沉积该含掺质金属224时,其本质上为共形之均匀覆盖。自该隔离部分204、栅极210顶部表面与侧壁、以及该栅极介电质208的侧壁上移除该含掺质金属224的过剩部分,而残留下如图6所示之结构。该含掺质金属224的过剩部分是藉由一异向性蚀刻过程或是一等向性蚀刻过程加以移除,举例而言,可利用湿式、干式、电化学或化学蚀刻过程来移除该等过剩部分,亦可使用其它的蚀刻方法。在该源极S与漏极D区域中所形成之该含掺质金属224的顶部表面本质上与该工作部件202的顶部表面222系为一平面;此外,该含掺质金属224亦可稍微凹陷或是在该工作部件202的凹槽中呈现轻微凹面(图中未示)。
在一实施例中,可在此一制造阶段中,利用离子布植方式来对该等含掺质金属区域加以掺杂,其为一可随意加入的步骤且并非本发明之实施例所必须,然却适用于某些晶体管之设计。在此一随意之步骤中,利用离子布植方式而将掺杂物离子225注入至该含掺质金属224中,其可增加该含掺质金属区域224中的掺杂物浓度,而于后续处理步骤中,该含掺质金属224之掺杂物在扩散至下方的基板202中期间,可增加下方之掺杂区域(未示于图6,见图7中226处)的掺杂物浓度。当本制造过程包含此一随意之离子布植步骤时,较佳为,此布植是执行于约1KeV的能量级或更低之能量级,且其布植剂量约为1×1015ions/cm2或更低。
接着,对该工作部件202施行一低温退火过程以产生该含掺质金属区域224中掺杂物之外扩散,并于相邻于该含掺质金属区域224之该工作部件202内的各源极S区域与漏极D区域中形成一掺杂区域226,如图7所示。该掺杂区域226延伸于该含掺质金属区域224下方,并侧向(至该含掺质金属区域之侧边)延伸于该栅极210与栅极介电质208下方处约(或少于)70,如228处所示。举例而言,该低温退火过程较佳为包含以约为900℃或更低之温度退火1小时或少于1小时,且最好是包含以约为900℃之温度退火20分钟或少于20分钟;该掺杂区域226之厚度较佳为(或少于)100。
因此,该源极S与该漏极D各包含一含掺质金属224以及与该含掺质金属224相邻(亦即低于且自其侧向延伸)之一掺杂区域226,如图中所示。该源极S与该漏极D较佳为包含位于该工作部件202之该顶部表面222下方300之总厚度。
须注意的式该掺杂区域226包含一延伸区域228,其系自该栅极介电质208下方向该信道区域C延伸;根据本发明之较佳实施例所形成的晶体管230的一项优势为,相较于传统的晶体管设计,可制作较小的该延伸区域228。举例而言,该延伸区域228可以一距离d1而延伸于该栅极210任一侧下方,该距离d1约为70或低于70(亦即约20至50),由于较小的重叠部分d1可降低该晶体管230的热载子效应,因而可产生较低的该延伸区域228电阻之优势。
在一实施例中,该含掺质金属224之掺杂物的原子百分率比该含掺质金属224之中性状态者为高,且在经低温退火后,由于掺杂物离子会扩散至该工作部件202中以形成该掺杂区域206,因而该含掺质金属224之掺杂物百分率会降低。举例而言,若该含掺质金属224为含钛(Ti)之硼(B)掺杂,则该含掺质金属224便包含TiBx,其中x>2,亦即x为3、4等等;在此一实施例中,在低温退火以形成该掺杂区域226后,该含掺质金属224便包含一较小的掺杂物原子百分率,亦可包含例如TiB2。须注意的是,在低温退火后,遗留在该含掺质金属224中的掺杂物物种会减少,这是因为部分掺杂物原子已迁移至该掺杂区域226,然仍有部分的掺杂物物种遗留在该含掺质金属224中。
接着继续执行该装置200之制造过程以完成该装置200,较佳为,不须对该半导体装置200施行高温处理,例如不须将该半导体装置200暴露于一高于900℃之温度中。举例而言,可将包含一介电质材料(如SiO2、SiN或SiON)之一间隙物材料212,或是可使用其它的绝缘材料,沉积于该工作部件202的暴露部分上,该侧壁间隙物212材料可暴露至一蚀刻过程(例如一异向性蚀刻)中以形成侧壁间隙物212,如图8所示。
因此,根据本发明之一实施例,所形成之一晶体管230包含了一栅极210、一源极S与一漏极D,其中该源极S与该漏极D包含了该含掺质金属224与该掺杂区域226。该晶体管装置230具有一薄有效氧化物厚度238,其包含了该接口层220与该栅极介电质208。有利地,由于该晶体管230并不暴露于一高温退火过程(亦即1000℃之温度或更高)中,可避免该接口层220之厚度因此而增加,因此,其有助于减少该有效氧化物厚度238;举例而言,该接口层220之厚度较佳约为2至7,且最好是7或少于7。此外,由于该源极S与该漏极D之该掺杂区域226是利用低温退火过程所形成,其可使该晶体管装置230之接合深度231较浅,该晶体管230则特别有利于强调高驱动电流与最小有效氧化物厚度之应用,例如高性能(亦即高速)应用,如用于内存与其它装置中。
图9说明了本发明之一较佳实施例,其使用与图2至图8所示者相似的处理流程。与图2至图8中的组件符号相同者在图9中亦代表对应的组件,而不在此重复赘述;此外,与图2至图8所示之材料与厚度相同的组件则以x02、x04...等组件符号表示,其中在图2至图8中,x=2,而在图9中,x=3;举例而言,在图2至图8中所列出之该含掺质金属224的较佳与替代材料,在图9中则表示为该含掺质金属324。
在图9所示之实施例中,在该等侧壁间隙物312形成于该栅极310与该栅极介电质308的侧壁上后,便使用一离子布植过程与接续之一高温退火处理,其温度约为1000℃或更高,以于该源极S与漏极D区域中形成深源极与漏极区域336,如图中所示。在一实施例中,此一随意之离子布植过程的目标深度最好是大于该含掺质金属324以及该掺杂区域326的深度。举例而言,该深源极与漏极区域336可于该工作部件顶部表面322下方包含一约为(或大于)500之深度。若该晶体管332包含一PMOS晶体管(BF2),且若该晶体管332包含一NMOS晶体管(As),则其布植之能量级约为10KeV,且其布植剂量为1×1015ions/cm2。
在图9所示之一实施例中,所产生的晶体管332具有的接口氧化物320比图8中所示之接口氧化物220更厚,且亦具有一额外的接口氧化物形成于该栅极介电质308与该栅极310(图中未示)间,然此晶体管322由于其源极S与漏极D中具有该含掺质金属324,因而有助于降低其片状电阻Rs。此一晶体管322有益于需要一较深源极S与漏极D布植之晶体管322应用,以避免该源极S和漏极D与该工作部件302间的接合泄漏电流,例如在低功率应用中;而在该等应用中,较高的有效氧化物厚度并不会将低该晶体管322之性能。
图10至图11、与图12说明了本发明另一实施例,其中,在沿侧壁方向且邻近该栅极介电质与该栅极处使用了一双重间隙物。图10至图11、与图12所示之实施例是使用与图2至图8、与图9所示者相似的处理流程以及结构。与图2至图8、与图9中的组件符号相同者在图10至图11、与图12中亦代表对应的组件,而不在此重复赘述;此外,与图2至图8、与图9所示之材料与厚度相同的组件则以x02、x04...等组件符号表示,其中在图2至图8中,x=2,在图9中,x=3,在图10至图11中x=4,而在图12中x=5。
图10至图11为根据本发明之另一较佳实施例之截面图,其中一第一间隙物440是在形成该源极S与漏极D区域之凹槽前,即形成于该栅极介电质408与该栅极410上。该等第一间隙物440具有之厚度约为(或少于)50,且可包含一绝缘材料,如SiO2、SiN或SiON。在此使用与图4至图8所示者相同的制造过程,而产生如图11所示之晶体管444之截面图。在形成此处所述之该源极S与漏极D区域后,一第二间隙物442则紧邻该第一间隙物444而形成,如图中所示。同样地,该晶体管444的该栅极介电质408具有一较小的有效氧化物厚度438,且其具有之接合深度431可良好控制至非常浅。此一实施例有助于进一步减少该源极S与漏极D的延伸区域428,其自该栅极410与该栅极介电质408下方延伸一约为50之d2距离,如图中所示。
图12说明本发明之一实施例,其使用了如图11所示之一第一间隙物540与第二间隙物542。此外,接着对该工作部件502施行一离子布植过程以于该源极S与漏极D中形成深源极与漏极区域536,可参考如图9所示之实施例;如图中所示,其使得所形成之晶体管546具有深源即与漏极区域536并包含位于该栅极510与该栅极介电质508任一侧上之一第一间隙物540与一第二间隙物542。如图9所示,其需要相对较高的退火温度来形成该深源极与漏极区域536,其导致一较大的EOT,但于部分应用中其并不会造成不利影响;该晶体管546具有较小的片状电阻Rs与接合深度531。
本发明之较佳实施例的优势为,其提供了晶体管设计230、332、444与546,以及其制造方法,该等晶体管之源极S与漏极D区域包含一含掺质金属224、324、424、524,其掺杂物是在一低温退火过程中扩散至该含掺质金属224、324、424、524下方的一区域,而形成掺杂区域226、326、426、526。该等掺杂区域226、326、426、526与该等含掺质金属224、324、424、524包含了该等晶体管230、332、444与546之源极S与漏极D。一般而言,在半导体制造中,金属具有的片状电阻较其它材料更低,因此,于该源极S与漏极D中使用金属可降低此处所述之该等晶体管230、332、444与546之延伸区域228、328、428、528的片状电阻Rs。
由于使用一低温退火过程来形成该等掺杂区域226、326、426、526,因此在用于形成该等掺杂区域226、326、426、526之低温退火过程中,并不会增加该栅极介电质的有效氧化物厚度,因而可产生较薄的有效栅极介电质厚度(或有效氧化物厚度(EOT)),其包含了该薄接口氧化物与该栅极介电质220/208或420/408的整体厚度。此外,由于为产生含掺质金属224、324、424与524的凹槽所使用之蚀刻过程可被良好控制,因而藉由本发明之实施例,亦可减少接合深度231、331、431、531,亦可降低热载子效应,这是因为该源极S与漏极D的延伸区域228、328、428、528延伸至该栅极210、310、410、510下方的距离减少之故。此处所述之晶体管有利于降低热预算并提升栅极性能。
再次说明,在各图式中仅显示一晶体管,然而,根据本发明之实施例,亦可同时形成复数之晶体管(图中未示);此外,亦可于单一工作部件上形成PMOS与NMOS晶体管,仅须于处理其它部分时,遮蔽该工作部件的某些部分。
虽然本发明之实施例与其优势详细加以说明,然其亦可具有不同的变化例,且得由熟悉技艺之人任施匠思而为诸般修饰,然不脱如附申请范围所欲保护者。举例而言,熟悉该项技艺之人士将了解到此处所述之特征、功能、处理过程、与材料种类而于本发明之范畴中加以变化;此外,本发明之范畴并不限于该等特定实施例所提及之制程、设备、制造、与物质组成。熟悉该项技艺之人士亦可藉由本发明所揭露之制程、设备、制造、物质组成、目前存在或后续发展的方法或步骤来达成本发明之实施例中所产生的结果;因此,下述之权利要求尝试于其范畴中包含该等制程、设备、制造、物质组成、方法、或步骤。
附图标记列表
100 半导体装置
102 工作部件
104 场效氧化物区域
108 栅极介电质
110 栅极
112 绝缘间隙物
114 接口氧化物
116 接口氧化物
118 有效氧化物厚度(EOT)
128 延伸区域
S 源极
D 漏极
C 信道区域
xj 接合深度
200、300、400、500半导体装置
202、302、402、502工作部件
204、304、404、504隔离区域
208、308、408、508栅极介电质
210、310、410、510栅极
212、312、412、512间隙物
220、320、420、520接口层
222、322、422、522顶部表面
224、324、424、524含掺质金属
225、325、425、525掺杂物离子
226、326、426、526掺杂区域
228、328、428、528延伸区域
230、332、444、546晶体管
231、331、431、531接合深度
238、338、438、538有效氧化物厚度
d1距离
h1 深度
S 源极
D 漏极
C 信道区域
Claims (31)
1.一种晶体管,其包含:
一源极与一漏极,其位于一工作部件中,该工作部件具有一顶部表面,该源极与该漏极是由一信道区域所分隔,其中该源极与漏极各包含一含掺质金属区域与一掺杂区域,该含掺质金属区域是位于该工作部件的该顶部表面内,而该掺杂区域是与各含掺质金属区域相邻而位于该工作部件中;
一栅极介电质,其位于该信道区域与该源极与该漏极的一部份上;以及
一栅极,其位于该栅极介电质上。
2.如权利要求1所述的晶体管,其中该含掺质金属区域具有的厚度约为200或小于200。
3.如权利要求2所述的晶体管,其中该含掺质金属区域包含TiB2、ZrB2、HfB2、ZrP、TiP、ZrSb2、TiSb2、HfSb2、或是含Zr或Hf砷化物。
4.如权利要求1所述的晶体管,其中该掺杂区域具有的厚度约为100或小于100。
5.如权利要求1所述的晶体管,其中该含掺质金属区域与该掺杂区域中的一掺杂物包含B、P、As或Sb。
6.如权利要求1所述的晶体管,其中该源极与该漏极具有的厚度约300或低于该工作部件的该顶部表面厚度。
7.如权利要求1所述的晶体管,其中该栅极介电质包含一高介电常数材料、二氧化硅(SiO2)、氮化硅(SixNx)、或氮氧化硅(SiON)。
8.如权利要求7所述的晶体管,其中该栅极介电质包含HfO2、HfSiOx、Al2O3、ZrO2、ZrSiOx、Ta2O5、La2O3、SiO2、SixNy、SiON、或是其组合。
9.如权利要求1所述的晶体管,更包含一接口介电质,其位于该栅极介电质与该工作部件的该信道区域间。
10.如权利要求9所述的晶体管,其中该接口介电质具有的厚度约为7或小于7。
11.如权利要求1所述的晶体管,其中该栅极与该栅极介电质包含侧壁,更包含位于该栅极与该栅极介电质的该侧壁上的一第一间隙物。
12.如权利要求11所述的晶体管,其中该第一间隙物具有的厚度约为20至70。
13.如权利要求11所述的晶体管,其中该第一间隙物包含侧壁,更包含邻接于该第一间隙物侧壁的一第二间隙物。
14.如权利要求1所述的晶体管,其中该源极与该漏极各包含一深布植区域,其位于各掺杂区域下方。
15.一种半导体装置,其包含至少一如权利要求1所述的晶体管。
16.如权利要求15所述的半导体装置,其中该至少一晶体管包含一P型金属氧化半导体晶体管、一N型金属氧化半导体晶体管或两者。
17.一种晶体管,包含:
一源极,其位于一工作部件中,该工作部件具有一顶部表面,其中该源极包含一第一含掺质金属区域与一第一掺杂区域,该第一含掺质金属区域是位于该工作部件的该顶部表面内,而该第一掺杂区域是位于与该第一含掺质金属区域相邻的该工作部件中;
一漏极,其位于该工作部件中,该漏极是藉由一信道区域而与该源极分隔,其中该漏极包含一第二含掺质金属区域与一第二掺杂区域,该第二含掺质金属区域是位于该工作部件的该顶部表面内,而该第二掺杂区域是位于与该第二含掺质金属区域相邻之该工作部件中;
一栅极介电质,其位于该信道区域与该源极与该漏极的一部份上;以及
一栅极,其位于该栅极介电质上。
18.如权利要求17所述的晶体管,其中该含掺质金属区域包含一厚度约为200或小于200的TiB2、ZrB2、HfB2、ZrP、TiP、ZrSb2、TiSb2、HfSb2、或是含Zr或Hf的砷化物。
19.如权利要求17所述的晶体管,其中该栅极介电质包含HfO2、HfSiOx、Al2O3、ZrO2、ZrSiOx、Ta2O5、La2O3、SiO2、SixNy、SiON、或是其组合。
20.一种用以制造一晶体管的方法,该方法包含:
提供一工作部件;
沉积一栅极介电质材料于该工作部件上;
沉积一栅极材料于该栅极介电质材料上;
图样化该栅极材料与栅极介电质材料,以形成一栅极与一栅极介电质于该工作部件的一信道区域上;
形成一第一凹槽于该工作部件的一源极区域中以及形成一第二凹槽于该工作部件的一漏极区域中,该源极区域与该漏极区域是彼此近似且由该信道区域分隔;
填充一含掺质金属至该第一凹槽与该第二凹槽中;以及
退火该工作部件以使该含掺质金属的一掺杂物扩散至该工作部件中,并于该源极区域与该漏极区域中与该含掺质金属相邻的该工作部件中形成一掺杂区域。
21.如权利要求20所述的方法,其中退火该工作部件包含以约为900℃或更低之温度退火1小时或少于1小时。
22.如权利要求20所述的方法,其中该栅极介电质包含侧壁,其中填充一含掺质金属至该第一凹槽与该第二凹槽中包含:
沉积该含掺植金属至该第一凹槽、该第二凹槽、该栅极与该栅极介电质的侧壁上;以及
移除在该栅极与该栅极介电质的侧壁上方的该含掺质金属,而留下在该第一凹槽与该第二凹槽中的该含掺质金属。
23.如权利要求20所述的方法,其中该栅极与该栅极介电质包含侧壁,该方法更包含在形成该第一凹槽与该第二凹槽前,形成一第一间隙物于该栅极与该栅极介电质的侧壁。
24.如权利要求23所述的方法,其中形成该第一间隙物包含形成一宽度约为20至70的一间隙物。
25.如权利要求23所述的方法,更包含在形成至少该第一间隙物后,布植一掺杂物的离子至该源极区域与该漏极区域中,并退火该工作部件以形成深布植区域于该掺杂区域下方的该源极区域与该漏极区域中。
26.如权利要求23所述的方法,其中该第一间隙物包含侧壁,该方法更包含在退火该工作部件后,形成一第二间隙物于该第一间隙物的侧壁上方。
27.如权利要求26所述的方法,其更包含在形成该第二间隙物后,布植一掺杂物的离子至该源极区域与该漏极区域中,并退火该工作部件以形成深布植区域于该掺杂区域下方之该源极区域与该漏极区域中。
28.如权利要求20所述的方法,其中形成该第一凹槽与该第二凹槽包含形成深度为200或少于200的凹槽。
29.如权利要求28所述的方法,其中填充一含掺质金属至该第一凹槽与该第二凹槽中包含填充TiB2、ZrB2、HfB2、ZrP、TiP、ZrSb2、TiSb2、HfSb2、或是含Zr或Hf的砷化物于该第一凹槽与该第二凹槽中。
30.如权利要求20所述的方法,其中形成该第一凹槽与该第二凹槽包含一单独图样化步骤。
31.如权利要求20所述的方法,其中沉积该栅极介电质材料包含沉积HfO2、HfSiOx、Al2O3、ZrO2、ZrSiOx、Ta2O5、La2O3、SiO2、SixNy、SiON、或是其组合。
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- 2005-03-04 DE DE102005009976A patent/DE102005009976B4/de not_active Expired - Fee Related
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CN102214608A (zh) * | 2010-04-09 | 2011-10-12 | 中国科学院微电子研究所 | 一种半导体器件及其制造方法 |
WO2011124061A1 (zh) * | 2010-04-09 | 2011-10-13 | 中国科学院微电子研究所 | 一种半导体器件及其制造方法 |
CN102466806A (zh) * | 2010-11-03 | 2012-05-23 | 中国科学院微电子研究所 | 一种基于绝缘体上硅的pmos辐射剂量计 |
CN102997944A (zh) * | 2011-09-08 | 2013-03-27 | 飞思卡尔半导体公司 | 入射电容式传感器 |
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CN105247682A (zh) * | 2013-06-27 | 2016-01-13 | 英特尔公司 | 具有未掺杂的漏极未覆盖环绕区的隧穿场效应晶体管(tfet) |
CN105247682B (zh) * | 2013-06-27 | 2019-01-22 | 英特尔公司 | 具有未掺杂的漏极未覆盖环绕区的隧穿场效应晶体管(tfet) |
CN111463285A (zh) * | 2020-04-10 | 2020-07-28 | 上海华力集成电路制造有限公司 | P型fet及其制造方法 |
CN111463285B (zh) * | 2020-04-10 | 2023-06-09 | 上海华力集成电路制造有限公司 | P型fet及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
US8390080B2 (en) | 2013-03-05 |
US6921691B1 (en) | 2005-07-26 |
DE102005009976A1 (de) | 2005-12-01 |
US20090026555A1 (en) | 2009-01-29 |
US7446379B2 (en) | 2008-11-04 |
DE102005009976B4 (de) | 2012-12-06 |
CN1670965B (zh) | 2011-01-12 |
US20050205896A1 (en) | 2005-09-22 |
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