TWI388003B - 半導體元件及其製造方法 - Google Patents
半導體元件及其製造方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims description 79
- 229910052751 metal Inorganic materials 0.000 title claims description 46
- 239000002184 metal Substances 0.000 title claims description 46
- 238000002513 implantation Methods 0.000 title claims description 20
- 239000004065 semiconductor Substances 0.000 claims description 78
- 230000008569 process Effects 0.000 claims description 50
- 239000000758 substrate Substances 0.000 claims description 26
- 238000004519 manufacturing process Methods 0.000 claims description 17
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 16
- 229910052731 fluorine Inorganic materials 0.000 claims description 16
- 239000011737 fluorine Substances 0.000 claims description 16
- 238000000137 annealing Methods 0.000 claims description 15
- 229910015900 BF3 Inorganic materials 0.000 claims description 12
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 claims description 12
- 238000005229 chemical vapour deposition Methods 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 12
- 239000002019 doping agent Substances 0.000 claims description 11
- 238000000231 atomic layer deposition Methods 0.000 claims description 10
- 238000000059 patterning Methods 0.000 claims description 8
- 238000005240 physical vapour deposition Methods 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 7
- 239000007943 implant Substances 0.000 claims description 6
- 230000004913 activation Effects 0.000 claims description 5
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 claims description 4
- 238000007654 immersion Methods 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 4
- 238000005516 engineering process Methods 0.000 claims description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 3
- 238000007740 vapor deposition Methods 0.000 claims description 3
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 claims description 2
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 238000004151 rapid thermal annealing Methods 0.000 claims 4
- 229910000449 hafnium oxide Inorganic materials 0.000 claims 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 138
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 238000000151 deposition Methods 0.000 description 6
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 6
- 229910052732 germanium Inorganic materials 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 125000006850 spacer group Chemical group 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 2
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium dioxide Chemical compound O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- -1 TiN Chemical class 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 229940119177 germanium dioxide Drugs 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 125000002524 organometallic group Chemical group 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 150000003304 ruthenium compounds Chemical class 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- XSOKHXFFCGXDJZ-UHFFFAOYSA-N telluride(2-) Chemical compound [Te-2] XSOKHXFFCGXDJZ-UHFFFAOYSA-N 0.000 description 1
- SITVSCPRJNYAGV-UHFFFAOYSA-L tellurite Chemical compound [O-][Te]([O-])=O SITVSCPRJNYAGV-UHFFFAOYSA-L 0.000 description 1
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
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- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3215—Doping the layers
- H01L21/32155—Doping polycristalline - or amorphous silicon layers
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
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Description
本發明係有關於半導體裝置，且特別是以佈植方法降低半導體裝置中金屬閘極元件之臨界電壓的方法。
半導體積體電路(IC)產業已經歷過快速的成長。IC材料和設計的技術進步使得IC的生產世代不停地推新，每個世代都較前個世代有更小及更複雜的電路。然而，這些進步也增加了製造IC製程的複雜性，因此IC製程也需要有同樣的進展才能實現更先進的積體電路IC製程。
在積體電路的革新過程中，功能密度(亦即每個晶片區域上互連裝置的數量)已普遍的增加且幾何尺圖案尺寸(亦即在製程中所能創造的最小元件或線)越來越小。這些尺度下降的製程通常能增加產品效能和提供較低的相關成本。但某些尺度的下降也產生一相對較高的功率消耗(power dissipation)值，其可用低功率消耗的元件例如互補型金氧半導體(CMOS)元件來處理。
依照元件縮小化的趨勢，各種材料被應用在CMOS的閘極電極(gate electrode)和閘介電層(gate dielectric)。例如，可使用一金屬材料當閘極電極和一高介電常數介電質當閘介電層。然而，n型MOS(NMOS)元件和p型MOS(PMOS)元件需要不同的功函數(work function)來對應它們的閘電極。目前已有許多同時達成金屬閘極的n和p的功函數。然而可以觀察到，由於有效功函數(effective work function)不足及p型金屬熱穩定性不佳，在PMOS元件的半導體製程中，臨界電壓(threshold voltage)可能會增大且載子(carrier)移動率變差。
因此，業界需要的是運用佈植的方法來降低一高介電常數金屬閘極元件的臨界電壓。
本發明提供一種半導體元件的製造方法，包含：在一半導體基材上形成一高介電常數介電層；在該高介電常數介電層上形成一蓋層(capping layer)；在該蓋層上形成一金屬層；在該金屬層上形成一半導體層；在該半導體層上進行一佈植製程，該佈植製程使用包含氟的雜質；及圖案化該高介電常數介電層、該蓋層、該金屬層和該半導體層以形成一閘極結構。
本發明也提供一種半導體元件的製造方法，包含：在一半導體基材上形成一界面層；在該界面層上形成一蓋層；在該蓋層上形成一高介電常數介電層；在該高介電常數介電層上形成一金屬層；在該金屬層上形成一多晶矽層；在該多晶矽層上進行一佈植製程，該佈植製程使用一含氟的摻質(dopant)；及圖案化該界面層、該蓋層、該高介電常數介電層、該金屬層及該多晶矽層，以形成一閘極結構。
另外，本發明提供一種半導體元件，包含一半導體基材和一電晶體於該基材中，該電晶體具有一閘極堆疊，包含：一界面層，形成於該半導體基材上；一高介電常數介電層，形成於該界面層上；一金屬層，形成於該高介電常數介電層上；一蓋層，形成於該界面層和高介電常數介電層之間或該高介電常數介電層和該金屬層之間；一摻雜層(doped layer)，形成於該金屬層上，該摻雜層至少包含氟。
本發明提供一含高介電常數介電層和金屬閘極的半導體元件之製造方法100，其流程如第1圖所示。第2圖為依第1圖方法100製造該半導體元件之剖面示意圖。第1圖和第2圖已經過簡化來強調PMOS元件的閘極結構，以更清楚的說明本實施例之發明概念。本方法100可藉由通過複晶層(poly layer)的佈植製程使PMOS元件的平帶電壓(flat band voltage)移向一p型功函數金屬(p-metal)來改善效能。
本方法100首先為提供一半導體基材(步驟110)。該半導體元件200可包含一半導體基材202例如矽基材。該基材202可替換為矽化鍺(silicon germanium)、鎵化砷(gallium arsenic)或其他合適的半導體材料。該基材202可進一步包含其他特徵像是各種摻雜區域，例如p井(p-well)或n井(n-well)、深埋層(buried layer)及/或磊晶層(epitaxy layer)。更進一步的，該基材202可為一在絕緣體上的半導體，例如絕緣層上覆矽(Silicon on Insulator；SOI)。在其他實施例中，該半導體基材202可包含一摻雜的磊晶層(epi layer)、一梯度半導體層(gradient semiconductor)及/或更可包含一半導體層疊在另一不同型態的半導體層上，例如一矽層疊在矽化鍺層上。在其他例子中，一化合物半導體基材可包含多層矽結構或一矽基材可包含多層化合物半導體結構。
該半導體元件200可進一步包含一隔離結構(圖中未顯示)像是在該基材202中形成淺溝槽隔離(STI)以隔離主動區。該隔離結構可由習知的二氧化矽、氮化矽(silicon nitride)、氟摻雜矽酸鹽(FSG)及/或一高介電常數介電層形成。主動區可形成像是NMOS元件和PMOS元件，雖然第2圖只顯示PMOS元件204。
該半導體元件200可進一步包含一界面層210，形於在該基材202上。界面層210可包含厚度約為6-8埃()的二氧化矽層。界面層210可由原子層沈積(ALD)、化學氣相沉積(CVD)或其他適合的製程形成。接著，在基材上形成一高介電常數介電層(步驟120)。半導體元件200可進一步包含一高介電常數介電層，形成於界面層210上。高介電常數介電層212可由原子層沈積(ALD)、化學氣相沉積(CVD)、有機金屬氣相沉積(MOCVD)、物理氣相沉積(PVD)或前述之組合或其他各種適合的沉積技術形成。高介電常數介電層212之厚度範圍約從5到25埃()。高介電常數介電層可包含例如二氧化鉿(HfO2
)的鉿化合物材料。或者，高介電常數介電層可選擇性的包含其他高介電常數介電材料像是HfSiO、HfSiON、HfTaO、HfTaTiO、HfTiO、HfZrO、HfAlON或前述之組合。
接著，在高介電常數介電層上形成一蓋層(步驟130)。半導體元件200可進一步包含一蓋層以調控功函數(對閘電極)使NMOS元件(圖中未顯示)或PMOS元件204有適當的效能。例如，一蓋層216像是氧化鋁可形成在PMOS元件204中的高介電常數介電層212上。或者，蓋層216可選擇性的包含氮化鋁(AlN)、鋁、鋁氧化物或前述之組合。蓋層216厚度約為2-10埃()。蓋層216可由原子層沈積(ALD)、化學氣相沉積(CVD)、有機金屬氣相沉積(MOCVD)、物理氣相沉積(PVD)或前述之組合或其他各種適合的沉積技術形成。
接著，在蓋層上形成一金屬層(步驟140)。半導體元件100可進一步包含一金屬層220，形成於蓋層216上。金屬層220可包含各種金屬例如TiN、TiAlN、TaN、WN或其他適合的金屬。金屬層220的厚度約從20到200埃()。金屬層220可由各種沉積技術例如原子層沈積(ALD)、化學氣相沉積(CVD)或濺鍍(sputtering)、電鍍(plating)或其他適合的沉積技術形成。
接著，用一適當的製程使多晶矽(或複晶)層(polysilicon or poly layer)222形成在金屬層220上(步驟150)。多晶矽層的厚度約為200-1000埃()。
接著，在多晶矽層上進行含氟雜質(species)的佈植製程(implantation process)(步驟160)。佈植製程230含一氟摻質，可在多晶矽(或複晶)層222上進行。例如，該摻質可包含氟、二氟化硼(BF2
)、氟化硼(BF)、含氟的雜質或前述之組合。佈植製程230可包含下列製程參數：能量範圍為約從2到20Kev(在複晶層厚度為800埃時，能量為15KeV較佳)和劑量範圍約從1E14到1E16atoms/cm2
(1E15atoms/cm2
較佳)。再者，佈植製程230可包含一電漿技術或浸入式離子佈植技術。值得注意的是在PMOS元件204中的複晶層222上進行佈植製程230的期間，可藉由一圖案化的光阻層保護NMOS元件(圖中未顯示)中的複晶層。該圖案化的光阻層可由微影技術(photolithography)、浸入式微影技術(immersion photolithography)或其他合適的製程形成。
接著，使用一退火製程(annealing process)來進行活化(步驟170)。在進行完佈植製程230後，使用一退火製程來進行活化。在退火期間，該含氟雜質(species)的摻質可擴散進入金屬閘極層和高介電常數介電層。該退火製程之溫度範圍從約從600到1100℃(1000℃較佳)。
接著，在各層形成閘極堆疊(步驟180)。使閘極結構圖案化的示範方法描述如下。藉由一合適的製程例如旋轉塗佈使光阻層形成在多晶矽層上，接著利用一適當的微影成形(lithography patterning)方法來形成一圖案化的光阻。經過一連串的製程步驟及各種適當程序，該光阻層的圖案可藉由乾式或濕式蝕刻製程轉移到底下的複晶層222、金屬層220、高介電常數介電層212和界面層210。之後，使用習知適當的製程來剝除該光阻層。在其他實施例中，可在複晶層222上形成並使用一硬罩幕層(hard mask)。圖案化的光阻層係形成在硬罩幕層上。先將光阻層的圖案轉移到硬罩幕層再轉移到底下的材料層以形成閘極結構。硬罩幕層可包含氮化矽(silicon nitride)、氮氧化矽(silicon oxynitride)、碳化矽(silicon carbide)及/或其他適合的介電材料。硬罩幕層可利用化學氣相沉積(CVD)或物理氣相沉積(PVD)的方法來形成。在PMOS元件204中的閘極堆積可包含界面層、高介電常數介電層、蓋層、金屬閘極層和多晶矽層。
之後，半導體元件200可繼續進行CMOS的製程流程來形成各種結構，像是輕摻雜汲極(lightly doped drain regions;LDD)、閘極堆積上的側壁間隔物(sidewall spacers)、源/汲極區域(包含矽化鍺)、金屬矽化物(silicide)、接觸點(contacts)/通孔(vias)、內連線層(interconnect layers)、金屬層、內層介電質(interlayer dielectric)、鈍化層(passivation layer)等等。例如，在該基材上可用離子佈植製程和可用(自我對準)閘極堆積形成輕摻雜源/汲極區域(light doped source/drain regions)。在PMOS元件的閘極堆積之兩側形成p型的輕摻雜汲極區域(使用p型摻質例如硼)。在NMOS元件的閘極堆積之兩側形成n型的輕摻雜汲極區域(使用n型摻質例如磷或砷)也為已習知的。在另一個例子中，側壁或閘極間隔物皆可在該PMOS和NOMOS元件中閘極堆積的兩側形成。側壁間隔物可選擇性的包含氮化矽(silicon nitride)、碳化矽(silicon carbide)、氮氧化矽(silicon oxynitride)或前述之組合，在某些實施例中，該側壁間隔物可包含一多層結構。該側壁間隔物可用沉積與蝕刻(非等向性蝕刻技術；anisotropic etching technique)的方式來形成。
值得注意的是藉由佈植一含氟雜質的摻質到複晶層222中，該閘極結構的平帶電壓(flat band)可移向一p功函數金屬(p型金屬)。也就是說PMOS元件的有效功函數可由佈植製程來做調整。因此，可降低PMOS的臨界電壓Vt
和增加載子(carrier)移動率並增加元件的效能和可靠度。雖然上述的例子中描述佈植製程230是在複晶層222沉積之後、閘極圖案化或蝕刻之前進行，但也可在閘極圖案化或蝕刻之後進行。
本發明另一實施例之含高介電常數和金屬閘極之半導體元件300的剖面圖如第3圖所示。半導體元件300除了蓋層外，其餘的配置皆近似於第2圖的半導體元件200。為了簡化起見，第2圖和第3圖會有許多相同的元件使用同樣的符號。半導體元件300可包含在界面層210和高介電常數介電層212之間形成一蓋層314，而非如第2圖中所示，在高介電常數介電層212和金屬層220之間。半導體元件300的製造方法類似於第1圖中的方法100，除了在界面層210上形成蓋層314，然後再於高介電常數介電層210上形成金屬層220，之後進行的製程皆與第1圖中步驟150-180相同。
在眾多實施例中，本發明達到了不同的優點。例如，本發明的方法提供了一簡單且節省的方法來減少PMOS元件的臨界電壓並且增進了載子(carrier)的移動率。因此，可增強同時擁有NMOS和PMOS的半導體元件的效能和可靠度。再者，本發明的方法和元件可輕易的和現有的CMOS技術製程和半導體設備做整合，使用該含氟雜質摻質的佈植製程和進行活化的退火製程對於現有的半導體製程來說合適且容易。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
200．．．半導體元件
202．．．半導體基材
204．．．PMOS元件
210．．．界面層
212．．．高介電常數介電層
216．．．蓋層
220．．．金屬層
222．．．半導體層
230．．．佈植製程
314．．．介於界面層和高介電常數介電層之間的蓋層
第1圖為本發明製造一半導體元件的流程示意圖，用來說明本發明的高介電常數金屬閘極的製程。
第2圖為依照第1圖的方法製造一半導體元件之剖面圖。
第3圖為本發明一實施例之一半導體元件的剖面圖。
200．．．半導體元件
202．．．半導體基材
204．．．PMOS元件
210．．．界面層
212．．．高介電常數介電層
216．．．蓋層
220．．．金屬層
222．．．半導體層
230．．．佈植製程
Claims (20)
- 一種半導體元件的製造方法，包含：在一半導體基材上形成一高介電常數介電層；在形成該高介電常數介電層之後，於其上形成一蓋層(capping layer)；在該蓋層上形成一金屬層；在該金屬層上形成一半導體層；在該半導體層上進行一佈植製程，該佈植製程使用包含氟的雜質；及圖案化該高介電常數介電層、該蓋層、該金屬層和該半導體層以形成一閘極結構。
- 如申請專利範圍第1項所述之半導體元件的製造方法，其中該半導體層包含一多晶矽層。
- 如申請專利範圍第1項所述之半導體元件的製造方法，其中該雜質包含氟、二氟化硼(BF2 )、氟化硼(BF)或前述之組合。
- 如申請專利範圍第1項所述之半導體元件的製造方法，其中該佈植製程之能量範圍為約2到20 KeV及劑量範圍約從1E14到1E16 atoms/cm2 。
- 如申請專利範圍第1項所述之半導體元件的製造方法，佈植製程包含電漿技術和浸入式離子佈植技術其中之一。
- 如申請專利範圍第1項所述之半導體元件的製造方法，更包含在進行佈植製程之後，使用一快速熱退火(rapid thermal annealing；RTA)、爐管退火(furnace annealing)、閃燈退火(flash lamp annealing；FLA)、雷射瞬間退火(laser spike annealing；LSA)或前述之組合來進行活化；及其中該退火製程之溫度範圍約從600到1100℃。
- 如申請專利範圍第1項所述之半導體元件的製造方法，更包含在該基材和該高介電常數介電層之間形成一界面層。
- 一種半導體元件的製造方法，包含：在一半導體基材上形成一界面層；在該界面層上形成一蓋層；在該蓋層上形成一高介電常數介電層；在該高介電常數介電層上形成一金屬層；在該金屬層上形成一多晶矽層；在該多晶矽層上進行一佈植製程，該佈植製程使用一含氟的摻質(dopant)；及圖案化該界面層、該蓋層、該高介電常數介電層、該金屬層及該多晶矽層，以形成一閘極結構。
- 如申請專利範圍第8項所述之半導體元件的製造方法，其中該摻質包含氟、二氟化硼(BF2 )、氟化硼(BF)或前述之組合。
- 如申請專利範圍第8項所述之半導體元件的製造方法，其中該佈植製程之能量範圍約從2到20 KeV及劑量範圍約從1E14到1E16 atoms/cm2 。
- 如申請專利範圍第8項所述之半導體元件的製造方法，佈植製程包含電漿技術和浸入式離子佈植技術其 中之一。
- 如申請專利範圍第8項所述之半導體元件的製造方法，更包含在進行佈植製程之後，使用一快速熱退火(rapid thermal annealing；RTA)、爐管退火(furnace annealing)、閃燈退火(flash lamp annealing；FLA)、雷射瞬間退火(laser spike annealing；LSA)或前述之組合來進行活化；及其中該退火製程之溫度範圍約從600到1100℃。
- 如申請專利範圍第8項所述之半導體元件的製造方法，其中形成該蓋層和形成該高介電常數介電層的方法包含原子層沈積(ALD)、化學氣相沉積(CVD)、有機金屬氣相沉積(MOCVD)、物理氣相沉積(PVD)其中之一或前述之組合。
- 一種半導體元件，包含一半導體基材和一電晶體於該基材中，該電晶體具有一閘極堆疊，包含：一界面層，形成於該半導體基材上；一高介電常數介電層，形成於該界面層上；一金屬層，形成於該高介電常數介電層上；一蓋層，形成於該界面層和高介電常數介電層之間；及一摻雜層(doped layer)，形成於該金屬層上，該摻雜層至少包含氟。
- 如申請專利範圍第14項所述之半導體元件，其中該電晶體包含一PMOS元件。
- 如申請專利範圍第14項所述之半導體元件，其中 該高介電常數介電質包含HfO2 、HfSiON、HfTaO、HfTaTiO、HfZrO、HfAlON其中一種或前述之組合。
- 如申請專利範圍第14項所述之半導體元件，其中該蓋層包含氮化鋁(AlN)、鋁、鋁氧化物其中之一或前述之組合。
- 如申請專利範圍第14項所述之半導體元件，其中該摻雜層包含摻雜的多晶矽層。
- 如申請專利範圍第18項所述之半導體元件，其中該摻雜層的摻質包含氟、二氟化硼(BF2 )、氟化硼(BF)或前述之組合。
- 如申請專利範圍第14項所述之半導體元件，其中該界面層包含二氧化矽。
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| US20110095379A1 (en) * | 2009-10-28 | 2011-04-28 | International Business Machines Corporation | Scaling of metal gate with aluminum containing metal layer for threshold voltage shift |
| CN101950757A (zh) * | 2010-07-13 | 2011-01-19 | 中国科学院上海微系统与信息技术研究所 | 基于soi衬底的高介电常数材料栅结构及其制备方法 |
| CN102468237B (zh) * | 2010-10-29 | 2014-03-12 | 中芯国际集成电路制造(北京)有限公司 | 半导体器件的制造方法 |
| US8530294B2 (en) | 2011-10-21 | 2013-09-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stress modulation for metal gate semiconductor device |
| CN103390559B (zh) * | 2012-05-09 | 2016-08-31 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件的制造方法 |
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| CN104752202B (zh) * | 2013-12-26 | 2018-01-02 | 中国科学院微电子研究所 | 一种半导体器件的制造方法 |
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| US5440168A (en) * | 1993-02-22 | 1995-08-08 | Ryoden Semiconductor System Engineering Corporation | Thin-film transistor with suppressed off-current and Vth |
| US5767004A (en) * | 1996-04-22 | 1998-06-16 | Chartered Semiconductor Manufacturing, Ltd. | Method for forming a low impurity diffusion polysilicon layer |
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| US6720630B2 (en) * | 2001-05-30 | 2004-04-13 | International Business Machines Corporation | Structure and method for MOSFET with metallic gate electrode |
| JP4236992B2 (ja) * | 2002-06-24 | 2009-03-11 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置の製造方法 |
| US7018880B2 (en) | 2003-12-22 | 2006-03-28 | Texas Instruments Incorporated | Method for manufacturing a MOS transistor having reduced 1/f noise |
| US7279413B2 (en) * | 2004-06-16 | 2007-10-09 | International Business Machines Corporation | High-temperature stable gate structure with metallic electrode |
| US8178902B2 (en) | 2004-06-17 | 2012-05-15 | Infineon Technologies Ag | CMOS transistor with dual high-k gate dielectric and method of manufacture thereof |
| KR100639679B1 (ko) * | 2004-11-26 | 2006-10-30 | 삼성전자주식회사 | 매립 절연막을 구비하는 트랜지스터의 제조방법 및 그에의하여 제조된 트랜지스터 |
| KR100629357B1 (ko) * | 2004-11-29 | 2006-09-29 | 삼성전자주식회사 | 퓨즈 및 부하저항을 갖는 낸드 플래시메모리소자 형성방법 |
| US7514310B2 (en) * | 2004-12-01 | 2009-04-07 | Samsung Electronics Co., Ltd. | Dual work function metal gate structure and related method of manufacture |
| US20060211259A1 (en) * | 2005-03-21 | 2006-09-21 | Maes Jan W | Silicon oxide cap over high dielectric constant films |
| KR100653714B1 (ko) * | 2005-04-12 | 2006-12-05 | 삼성전자주식회사 | 반도체소자의 제조방법 및 그에 의해 제조된 반도체소자 |
| KR100724563B1 (ko) | 2005-04-29 | 2007-06-04 | 삼성전자주식회사 | 다중 일함수 금속 질화물 게이트 전극을 갖는 모스트랜지스터들, 이를 채택하는 씨모스 집적회로 소자들 및그 제조방법들 |
| KR100780661B1 (ko) * | 2005-06-29 | 2007-11-29 | 주식회사 하이닉스반도체 | 비휘발성 메모리 소자의 유전체막 및 그 형성방법 |
| US7947549B2 (en) * | 2008-02-26 | 2011-05-24 | International Business Machines Corporation | Gate effective-workfunction modification for CMOS |
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| CN101728273A (zh) | 2010-06-09 |
| US7994051B2 (en) | 2011-08-09 |
| US8258546B2 (en) | 2012-09-04 |
| CN101728273B (zh) | 2012-07-04 |
| TW201017730A (en) | 2010-05-01 |
| US20100096705A1 (en) | 2010-04-22 |
| US20110272766A1 (en) | 2011-11-10 |
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