TWI420652B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI420652B
TWI420652B TW098129863A TW98129863A TWI420652B TW I420652 B TWI420652 B TW I420652B TW 098129863 A TW098129863 A TW 098129863A TW 98129863 A TW98129863 A TW 98129863A TW I420652 B TWI420652 B TW I420652B
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metal layer
semiconductor device
metal
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TW201013900A (en
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Su Horng Lin
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Taiwan Semiconductor Mfg
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Description

半導體裝置及其製造方法
本發明係有關於半導體裝置，且特別是有關於一種在高介電常數/金屬閘極製程中，具有N型功函數及P型功函數效能的單一金屬之形成方法。
半導體積體電路(IC)產業已經歷過快速的成長。IC材料和設計的技術進步使得IC的生產世代不停地推新，每個世代都較前個世代有更小及更複雜的電路。然而，這些進步也增加了製造IC製程的複雜性，因此IC製程也需要有同樣的進展才能實現更先進的積體電路IC製程。
在積體電路的革新過程中，功能密度(亦即每個晶片區域上互連裝置的數量)已普遍的增加然而幾何尺寸(亦即在製程中所能創造的最小元件或線)也越來越小。這些縮小尺寸的製程通常能增加產品效能和提供較低的相關成本。但某些尺寸的下降也產生相對較高的功率消耗(power dissipation)值，其可用低功率消耗的元件例如互補型金氧半導體(CMOS)元件來因應。
為配合元件縮小化的趨勢，各種材料被應用在CMOS裝置的閘極電極(gate electrode)和閘極介電層(gate dielectric)。其所需要的是使用金屬材料來作為閘極電極及使用高介電常數介電質作為閘極介電層來製造裝置。然而，N型MOS裝置(NMOS)及P型MOS裝置(PMOS)各自的閘極電極需要不同的功函數。目前許多方法已嘗試用以同時滿足金屬閘極之N型及P型的功函數，其中一種為使用多種金屬及/或蓋層作為閘極堆疊以滿足N型及P型功函數。雖然此種方法可滿足其原本之設計目的，然而卻不能廣泛地應用於各種情況。例如，此方法會增加NMOS及PMOS裝置中的閘極堆疊的複雜性，而增加了圖案化閘極堆疊的困難。
因此，業界需要的是在高介電常數/金屬閘極製程中形成一種具有N型功函數及P型功函數效能的單一金屬之方法。
本發明提供一種一種半導體裝置之製造方法，包括：提供具有一第一區域及一第二區域之一半導體基材；形成一高介電常數介電層於該半導體基材上；形成一金屬層於該高介電常數介電層上，該金屬層具有一第一功函數；保護位於該第一區域的該金屬層；對位於該第二區域之該金屬層進行一包含碳及氮之去耦合電漿(de-coupled plasma)處理；以及於該第一區域形成一第一閘極結構及於該第二區域形成一第二閘極結構，該第一閘極結構包含該高介電常數介電層及該金屬層，該第二閘極結構包含該高介電常數層及該經處理的金屬層。
本發明也提供一種半導體裝置之製造方法，包括：提供具有一第一區域及一第二區域之一半導體基材；形成一高介電常數介電層於該半導體基材上；形成一N型功函數金屬層(N型金屬)於該半導體基材上；對位於該第二區域上的N型金屬層進行一去耦合電漿處理，使至少兩種元素進入位於該第二區域上的N型金屬層中，該至少兩種元素至少距離位於該高介電常數介電層及該N型金屬層之間之界面5以上；進行一退火製程；形成一多晶矽層於該第一區域之N型金屬層上及該第二區域之經處理過之N型金屬層上；以及形成一第一閘極結構於該第一區域中及形成一第二閘極結構於該第二區域中，該第一閘極結構包含該高介電常數介電層、該N型金屬層及該多晶矽層，該第二閘極結構包含該高介電常數介電層、該經處理過之N型金屬層及該多晶矽層。
本發明更提供一種半導體裝置，包含：一具有一第一區域及一第二區域之半導體裝置；一形成在該半導體基材中之隔離結構，用以隔離該第一區域及該第二區域；一形成在該第一區域中之第一電晶體，該第一電晶體具有一第一閘極結構，該第一閘極結構包含一界面層、一高介電常數介電層及一金屬層；一形成在該第二區域中的第二電晶體；該第二電晶體具有一第二閘極結構，該第二閘極結構包含該界面層、該高介電常數介電層及該金屬層，該金屬層包含至少被混入兩種元素，該至少兩種元素距離該位於該高介電常數介電層及該金屬層之間的界面至少5以上，該至少兩種元素使該金屬層由一第一型功函數金屬轉變為一第二型功函數金屬。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：
在本說明書的各種例子中可能會出現重複的元件符號以便簡化描述，但這不代表在各個實施例及/或圖示之間有何特定的關連。再者，當提到某一層在另一層“之上”或“上方”，可代表兩層之間直接接觸或中間更插有其他元件或膜層。各種元件可能以任意不同比例顯示以使圖示清晰簡潔。
第1圖繪示在高介電常數/金屬閘極製程中，半導體裝置之製造方法100之流程圖。第2A至2F圖繪示以第1圖方法100製造半導體裝置200之一實施例於各個階段相對應之製程剖面示意圖。並且，第1圖方法100中的部分步驟可應用於CMOS的製造流程中。因此，於方法100之前、之中或之後可提供額外的製程，且其中某些製程在此會作些簡單的描述。此外，第2A至2F圖僅為簡化之圖示以使本發明提供之概念能易於明瞭。
依據第1圖，方法100起始於方塊110，其為在半導體基材上形成高介電常數材料。請參見第2A圖，半導體裝置200包含例如為矽基材的半導體裝置202。基材202可依照習知技術的需要包含各種摻雜形態。基材202也可包含其他元素半導體，例如鍺或鑽石。或者，基材202可包含化合物半導體及/或合金半導體。再者，基材202也可選擇性地包含磊晶層(epi layer)、應變以增進效能(strained for performance enhancement)及絕緣層上覆矽(SOI)結構。
此半導體裝置200可進一步包含隔離結構204，例如用以隔離基材202中的主動區206及208而形成於基材中的淺溝槽隔離(STI)元件。隔離結構204可由氧化矽、氮化矽、氮氧化矽、氟摻雜玻璃(FSG)及/或已習知的低介電常數材料形成。N型金氧半電晶體裝置(NMOS)為配置在主動區206上及P型金氧半電晶體裝置(PMOS)為配置在主動區208上。可以瞭解的是，半導體裝置200的部分可由互補型金氧半導體裝置(CMOS)之製程製造，故在此不多作贅述。
半導體裝置200可進一步包含形成於基材202上之界面層210。界面層210可包含成長的氧化矽層，其厚度約為5至10。半導體裝置200更可包含形成於界面層210上的高介電常數介電層212。高介電常數介電層212可包含HfO2 。或者，高介電常數介電層212可選擇性地包含其他高介電常數材料，例如HfSiO、HfSiON、HfTaO、HfTiO、HfZrO或前述之組合。高介電常數介電層212可由原子層沉積(ALD)、化學氣相沉積(CVD)或其他合適技術形成。高介電常數介電層212的厚度約為10至30。
接著，進行方塊120之步驟，其為在高介電常數介電層上形成金屬層，且該金屬層具有第一功函數。半導體裝置200更可包含在高介電常數介電層212上形成金屬層214。此金屬層214可包含N型功函數金屬(N型金屬)。例如，此金屬層214可包含各種功函數小於4.33eV的各種金屬。在一實施例中，此金屬層包含鉭或也可包含其他的N型金屬(但不僅限於)鋅、鈦、鈮、鋁、銀、錳、鋯、鉿及鑭。金屬層214可藉由各種沉積技術像是物理氣相沉積(PVD或濺鍍)、化學氣相沉積(CVD)、原子層沉積(ALD)、電鍍或其他合適技術形成。此金屬層214的厚度大於約25。在一實施例中，此金屬層的厚度約在40至60之間，較佳為約50。
接著，進行方塊130之步驟，其為形成用以保護於該第一區域中之金屬層的圖案化罩幕層。在本發明實施例中，可形成圖案化光阻層218於NMOS裝置206中的金屬層214n上。此圖案化光阻層218可藉由光學微影(photolithography)、浸潤式微影(immersion lithography)、離子束寫入(ion-beam writing)或其他合適製程形成。例如，光學微影製程可包含旋轉塗佈(spin-coating)、軟烘烤(soft-baking)、曝光、後烘烤(post-baking)、顯影(developing)、潤洗(rinsing)、乾燥及其他合適製程。或者，可形成圖案化硬罩幕層來取代光阻層以保護於NMOS裝置206中之金屬層214n。硬罩幕層可由氧化矽、氮氧化矽、氮化矽或其他合適材料形成。首先可先形成圖案化的光阻層於該硬罩幕層上，然後再進行乾或濕蝕刻以移除該硬罩幕層位於PMOS區域中的部分。
接著，進行方塊140之步驟，其為對在第二區域中未受保護之金屬層進行去耦合電漿製程處理，如第2B圖所示。在本發明實施例中，對受到保護之金屬層214p進行去耦合電漿製程處理225，此去耦合電漿處理可使元素227混雜(incorporate)進入金屬層214p的頂部，以使金屬層214p之功函數由N型金屬轉變(或調整)為P型功函數金屬(P型金屬)。各種可作混雜之元素227包含碳、氮、矽、氧或前述任何可達到欲調整之功函數之組合。在一實施例中，可藉由去耦合電漿製程225對鉭(Ta)層進行碳化及氮化而轉變為氮碳化鉭(TaCN)層，而具有P型金屬之效能。在各種實施例中，P型金屬之功函數可約大於4.8eV。並且，可調整耦合式電漿製程225，以使元素227混雜進入之區域至少能距離位於金屬層214p及高介電常數介電212之間的界面至少5以上。如此，可降低或避免對高介電常數介電層212造成損傷的風險。並且，在NMOS裝置206中的受保護之金屬層214p也可繼續維持為N型金屬不變。如此，一單一金屬層即可同時作為N型金屬及P型金屬。
去耦合電漿製程225可包含下列製程參數在去耦合電漿機台中進行：流量大於約100sccm之氮氣(或其他包含氮之氣體)、流量大於約100sccm之乙炔(或甲烷或其他含碳之氣體)、大於約500W之射頻功率(RF power)(連續或脈衝式射頻)、大於約10mTorr之壓力及約在15至120秒之間的週期時間。值得注意的是，去耦合電漿製程225可提供高離子密度但低能量的電漿，以使元素227僅混雜進入金屬層214p的頂部界面，而不會穿透太深及降解(degrading)底下的高介電常數介電層212，這對於厚度僅有約為50金屬層214p是相當重要的。本發明在此僅揭示如上述少許實施例的各種參數，這些參數可用來調整達到所欲之功函數，而不會脫離本發明之精神及範圍。例如，增加去耦合電漿機台之射頻功率及壓力可創造出高離子密度但低離子能量的電漿，以對金屬輪廓在頂部表面作更多的修飾。
接著，進行方塊150之步驟，其為進行退火製程。進行退火製程之溫度範圍約在800至1000℃之間。退火製程可包含快速退火(RTA)、雷射退火或其他合適之製程。此退火製程可確保PMOS裝置208中之金屬層214p中碳及氮元素的濃度，以穩定P型金屬的功函數。如此，此退火製程會促進金屬層214p中碳及氮元素的鍵結。此退火製程為在與已混雜元素(incorporated elements)相容之環境下進行，例如在氮氣之環境下。
接著，進行方塊160之步驟，其為在第一區域及第二區域中的金屬層上形成多晶矽層，如第2C圖所示。圖案化光阻層118可藉由剝離(stripping)製程或其他合適製程移除，並可藉由化學氣相沉積(CVD)或其他合適沉積製程來在N型金屬214n及P型金屬214p上形成多晶矽層240。此多晶矽層的厚度範圍約在200至2000之間。
第2D圖顯示為可在多晶矽層240上形成硬罩幕層250。硬罩幕層250可包含SiN、SiON、SiC、SiOC/PEOX、TEOS或其他合適材料。此外，可在硬罩幕層250上形成抗反射塗佈(anti-reflective coating；ARC)或底部抗反射塗佈(bottom anti-reflective coating；BARC)，其皆為習知之技術。
第2E圖顯示為可在硬罩幕層250上形成為圖案化之光阻層。此光阻層可包含用於NMOS裝置206之閘極圖案261及用於PMOS裝置208之閘極圖案262。閘極圖案261、262可由光學微影、浸潤式微影或其他合適製程來形成。
接著，進行方塊170之步驟，其為在第一區域中形成第一閘極結構及在第二區域中形成第二閘極結構。第2F圖顯示為以閘極圖案261、262作為罩幕，進行乾蝕刻或濕蝕刻製程來圖案化罩幕層250，並使用硬罩幕層來圖案化NMOS裝置206中的閘極結構281及PMOS裝置中的閘極結構282。閘極結構281、282可由乾蝕刻或濕蝕刻製程形成(閘極蝕刻或圖案化)。隨後可使用習知之技術將閘極圖案261、262移除。
NMOS裝置206中的閘極結構281可包含多晶矽層240n、金屬層214n、高介電常數介電層212n及界面層210n。PMOS裝置208中的閘極結構282可包含多晶矽層240p、P型金屬214p、高介電常數介電層212p。值得注意的是，為了對閘極進行圖案化，N型金屬214n及P型金屬214p可具有相似的厚度，且因此對NMOS裝置206及PMOS裝置208中的閘極進行圖案化相較於後閘極製程中NMOS裝置206及PMOS裝置208具有各種不同閘極厚度時會較為簡單。
可瞭解的是，方法100可更進一步進行CMOS技術製程之流程以形成各種已習知之元件。例如，在兩邊之閘極結構281、282旁形成輕摻雜源極/汲極區(LDD區)。並且，可由沉積及蝕刻製程在閘極結構之兩側形成側壁或閘極間隔物。此極間隔物可包含合適的介電材料，像是氮化矽、氧化矽、碳化矽、氮氧化矽或前述之組合。並且，可使用合適的N型或P型摻質(依據裝置之結構，例如NMOS及PMOS)進行離子佈植或擴散以形成源極/汲極區(S/D區)。
此外，可在基材上形成各種接觸點(contacts)/通孔(vias)、金屬結構及多層內連線元件(例如金屬層及層間介電層)，以連接半導體裝置200的各種結構及元件。例如，可由自我對準矽化(self-aligned silicide；salicide)形成矽化物元件，其步驟為在矽結構上形成金屬層，然後升溫作退火製程並造成金屬與其底下的矽進行反應而形成矽化物，接著再以蝕刻移除未反應之金屬。可在各種元件像是源極、汲極及/或閘極電極上以自我對準矽化形成矽化物材料，減少接觸電阻。並且，在基材上形成複數個圖案化的介電層及導電層，以形成多層內連線來連接各種P型及N型摻雜區域，像是源極、汲極、接觸區域及閘極區域。在一實施例中，形成多層內連線(MLI)結構，並以層間介電層(ILD)相互隔離。在較佳的例子中，此內連線結構包含在基材上形成接觸點(contacts)、通孔、金屬線。
本發明提供一種半導體裝置，包含半導體、用以隔離第一區域及第二區域而形成在基材中之隔離結構，形成於第一區域中的第一電晶體，此第一電晶體具有第一閘極結構，其包含界面層、高介電常數介電層及混雜至少有兩種元素之金屬層，且此第一閘極結構中之金屬層中的至少兩種元素距離位於金屬層及高介常數介電層之間的界面至少5以上，此至少兩種元素可使金屬層由第一型功函數金屬轉變為第二型功函數金屬，且此第二型功函數金屬包含P型功函數金屬。在其他實施例中，此金屬層包含鉭。在其他實施例中，此至少兩種元素包含碳及氮。在一些其他實施例中，此金屬層的厚度約為40至60。
此外，雖然本發明在實施例中舉例為可將N型金屬轉變為P型金屬，然而，本發明也可應用於將P型金屬轉變成N型金屬。並且，本發明所述之半導體裝置並不僅限於電晶體，也可包含其他主動及被動裝置，例如鰭式場效電晶體(FinFET)、高功率電晶體(high voltage transistor)、雙載子電晶體(bipolar transistor)、電容、電阻、二極體、熔絲(fuse)或前述之組合。
本發明在各種實施例中達到了許多不同的優點。例如，本方法提供了簡單且具有經濟效益的單一金屬層，其對NMOS裝置及PMOS裝置各自具有N型功函數金屬及P型功函數金屬。如此一來，欲對NMOS及PMOS裝置中因相對應的閘極堆疊具有相似之厚度，使閘極結構的圖案化變得相對較為簡單。如此，NMOS裝置及PMOS裝置的性能變得更加可靠及可預測。並且，本方法適用於現有的CMOS技術製程流程，因此可輕易地與現有的製造設備及裝置技術作整合。另外，在本發明中於各個實施例會有不同的優點，且無須在每個實施例中都需要有特定之優點。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
200．．．半導體裝置
202．．．基材
204．．．隔離結構
206．．．NMOS裝置
208．．．PMOS裝置
210、210n、210p．．．界面層
212、212n、212p．．．高介電常數介電層
214．．．金屬層
212n．．．n型金屬
214p．．．p型金屬
218．．．光阻層
225．．．去耦合電漿處理
227．．．摻雜元素
240．．．多晶矽層
250．．．硬罩幕層
261．．．NMOS裝置之閘極圖案
262．．．PMOS裝置之閘極圖案
281．．．NMOS裝置之閘極結構
282．．．PMOS裝置之閘極結構
第1圖為在高介電常數/金屬閘極製程中製造半導體裝置之一實施例之流程圖。
第2A~2F圖為一系列依據第1圖所述方法製造半導體裝置之剖面圖。
200‧‧‧半導體裝置
202‧‧‧基材
204‧‧‧隔離結構
206‧‧‧NMOS裝置
208‧‧‧PMOS裝置
210‧‧‧界面層
212‧‧‧高介電常數介電層
214n‧‧‧n型金屬
214p‧‧‧p型金屬
218‧‧‧光阻層
225‧‧‧去耦合電漿處理
227‧‧‧摻雜元素

Claims (20)

  1. 一種半導體裝置之製造方法，包括：提供具有一第一區域及一第二區域之一半導體基材；形成一高介電常數介電層於該半導體基材上；形成一金屬層於該高介電常數介電層上，該金屬層具有一第一功函數；保護位於該第一區域之該金屬層；對該位於第二區域之該金屬層進行一包含碳及氮之去耦合電漿(de-coupled plasma)處理；以及於該第一區域形成一第一閘極結構及於該第二區域形成一第二閘極結構，該第一閘極結構包含該高介電常數介電層及該金屬層，該第二閘極結構包含該高介電常數層及該經處理的金屬層。
  2. 如申請專利範圍第1項所述之半導體裝置的製造方法，其中該去耦合電漿處理包含大於500W之射頻功率、大於10mTorr之壓力、流速大於100sccm的一含氮氣體、流速大於100sccm的含碳氣體及介於15-120秒的時間週期。
  3. 如申請專利範圍第2項所述之半導體裝置的製造方法，其中該含氮氣體包含氮氣。
  4. 如申請專利範圍第2項所述之半導體裝置的製造方法，其中該含碳氣體包含乙烯或甲烷。
  5. 如申請專利範圍第1項所述之半導體裝置的製造方法，其中該第一功函數包含一N型功函數金屬。
  6. 如申請專利範圍第1項所述之半導體裝置的製造方法，其中該第一金屬層包含鉭。
  7. 如申請專利範圍第1項所述之半導體裝置的製造方法，更包含在處理過程之後進行一退火製程，該退火製程的溫度介於約800到1000℃之間。
  8. 如申請專利範圍第1項所述之半導體裝置的製造方法，更包含：形成一界面層於該半導體基材及該高介電常數之間；以及形成一多晶矽層位於該第一區域之該未經處理之金屬層及位於該第二區域之該處理過之金屬層上；其中該第一及該第二閘極結構皆包含該界面層及該多晶矽層。
  9. 如申請專利範圍第1項所述之半導體裝置的製造方法，其中該第一閘極結構為部分的一NMOS裝置及該第二閘極結構為部分的一PMOS裝置。
  10. 如申請專利範圍第1項所述之半導體裝置的製造方法，其中該高介電常數介電層包含HfO、HfSiO、HfSiNO、HfTaO、HfTiO、HfZrO或前述之組合。
  11. 一種半導體裝置之製造方法，包括：提供具有一第一區域及一第二區域之一半導體基材；形成一高介電常數介電層於該半導體基材上；形成一N型功函數金屬層(N型金屬)於該半導體基材上；對位於該第二區域上的N型金屬層進行一去耦合電漿處理，使至少兩種元素進入位於該第二區域上的N型金屬層中，該至少兩種元素至少距離位於該高介電常數介電層及該N型金屬層之間之界面5以上；進行一退火製程；形成一多晶矽層於該第一區域之N型金屬層上及該第二區域之經處理過之N型金屬層上；以及形成一第一閘極結構於該第一區域中及形成一第二閘極結構於該第二區域中，該第一閘極結構包含該高介電常數介電層、該N型金屬層及該多晶矽層，該第二閘極結構包含該高介電常數介電層、該經處理過之N型金屬層及該多晶矽層。
  12. 如申請專利範圍第11項所述之半導體裝置的製造方法，其中該至少兩種元素包含碳、氮、矽或氧之組合。
  13. 如申請專利範圍第11項所述之半導體裝置的製造方法，其中該N型金屬層包含鉭。
  14. 如申請專利範圍第11項所述之半導體裝置的製造方法，其中該去耦合電漿處理過程包含大於500W之射頻功率、大於10mTorr之壓力、流速大於100sccm之含氮氣體、流速大於100sccm之含碳氣體及介於15-120秒之週期時間。
  15. 如申請專利範圍第11項所述之半導體裝置的製造方法，其中該N型金屬層包含鑭、鉿、鋯、鋁或鈦。
  16. 一種半導體裝置，包含：一具有一第一區域及一第二區域之半導體裝置；一形成在該半導體基材中之隔離結構，用以隔離該第一區域及該第二區域；一形成在該第一區域中之第一電晶體，該第一電晶體具有一第一閘極結構，該第一閘極結構包含一界面層、一高介電常數介電層及一金屬層；以及一形成在該第二區域中的第二電晶體；該第二電晶體具有一第二閘極結構，該第二閘極結構包含該界面層、該高介電常數介電層及該金屬層，該金屬層包含至少被混入兩種元素，該至少兩種元素距離該位於該高介電常數介電層及該金屬層之間的界面至少5以上，該至少兩種元素使該金屬層由一第一型功函數金屬轉變為一第二型功函數金屬。
  17. 如申請專利範圍第16項所述之半導體裝置，其中該第一型功函數金屬包含一N型功函數金屬及該第二型功函數金屬包含一P型功函數金屬。
  18. 如申請專利範圍第16項所述之半導體裝置，其中該金屬層包含鉭。
  19. 如申請專利範圍第16項所述之半導體裝置，其中該至少兩種元素包含碳及氮。
  20. 如申請專利範圍第16項所述之半導體裝置，其中該金屬層的厚度約為40-60。
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