CN101685799A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN101685799A
CN101685799A CN200910173523A CN200910173523A CN101685799A CN 101685799 A CN101685799 A CN 101685799A CN 200910173523 A CN200910173523 A CN 200910173523A CN 200910173523 A CN200910173523 A CN 200910173523A CN 101685799 A CN101685799 A CN 101685799A
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林思宏
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种半导体装置的制造方法，包含：提供一具有一第一区域及一第二区域的半导体基材；形成一高介电常数介电层于该基材上；形成一金属层于该高介电常数介电层上，该金属层具有一第一功函数；保护该第一区域中的金属层，对该第二区域中的金属层进行一包含碳及氮的去耦合等离子体处理，以及形成一第一栅极结构于该第一区域中及形成一第二栅极结构于该第二区域中。该第一栅极结构包含高介电常数介电层及未经处理的金属层。该第二栅极结构包含高介电常数介电层及经处理过的金属层。本方法提供了简单且具有经济效益的单一金属层，适用于现有的CMOS技术工艺流程，因此可轻易地与现有的制造设备及装置技术作整合。

Description

半导体装置及其制造方法
技术领域
本发明涉及半导体装置，且特别涉及一种在高介电常数/金属栅极工艺中，具有N型功函数及P型功函数效能的单一金属的形成方法。
背景技术
半导体集成电路(IC)产业已经历过快速的成长。IC材料和设计的技术进步使得IC的生产世代不停地推新，每个世代都较前个世代有更小及更复杂的电路。然而，这些进步也增加了制造IC工艺的复杂性，因此IC工艺也需要有同样的进展才能实现更先进的集成电路IC工艺。
在集成电路的革新过程中，功能密度(亦即每个晶片区域上互连装置的数量)已普遍增加然而几何尺寸(亦即在工艺中所能创造的最小元件或线)也越来越小。这些缩小尺寸的工艺通常能增加产品效能和提供较低的相关成本。但某些尺寸的下降也产生相对较高的功率消耗(power dissipation)值，其可用低功率消耗的元件例如互补型金属氧化物半导体(CMOS)元件来因应。
为配合元件缩小化的趋势，各种材料被应用在CMOS装置的栅极电极(gate electrode)和栅极介电层(gate dielectric)。其所需要的是使用金属材料来作为栅极电极及使用高介电常数介电质作为栅极介电层来制造装置。然而，N型MOS装置(NMOS)及P型MOS装置(PMOS)各自的栅极电极需要不同的功函数。目前许多方法已尝试用以同时满足金属栅极的N型及P型的功函数，其中一种为使用多种金属及/或盖层作为栅极堆叠以满足N型及P型功函数。虽然此种方法可满足其原本的设计目的，然而却不能广泛地应用于各种情况。例如，此方法会增加NMOS及PMOS装置中的栅极堆叠的复杂性，而增加了图案化栅极堆叠的困难。
因此，业界需要的是在高介电常数/金属栅极工艺中形成一种具有N型功函数及P型功函数效能的单一金属的方法。
发明内容
本发明提供一种一种半导体装置的制造方法，包括：提供具有一第一区域及一第二区域之一半导体基材；形成一高介电常数介电层于该半导体基材上；形成一金属层于该高介电常数介电层上，该金属层具有一第一功函数；保护位于该第一区域的该金属层；对位于该第二区域的该金属层进行一包含碳及氮的去耦合等离子体(de-coupled plasma)处理；以及于该第一区域形成一第一栅极结构及于该第二区域形成一第二栅极结构，该第一栅极结构包含该高介电常数介电层及该金属层，该第二栅极结构包含该高介电常数层及该经处理的金属层。
本发明也提供一种半导体装置的制造方法，包括：提供具有一第一区域及一第二区域之一半导体基材；形成一高介电常数介电层于该半导体基材上；形成一N型功函数金属层(N型金属)于该半导体基材上；对位于该第二区域上的N型金属层进行一去耦合等离子体处理，使至少两种元素进入位于该第二区域上的N型金属层中，该至少两种元素至少距离位于该高介电常数介电层及该N型金属层之间之界面
Figure G2009101735235D00021
以上；进行一退火工艺；形成一多晶硅层于该第一区域的N型金属层上及该第二区域的经处理过的N型金属层上；以及形成一第一栅极结构于该第一区域中及形成一第二栅极结构于该第二区域中，该第一栅极结构包含该高介电常数介电层、该N型金属层及该多晶硅层，该第二栅极结构包含该高介电常数介电层、该经处理过的N型金属层及该多晶硅层。
本发明还提供一种半导体装置，包含：一具有一第一区域及一第二区域的半导体装置；一形成在该半导体基材中的隔离结构，用以隔离该第一区域及该第二区域；一形成在该第一区域中的第一晶体管，该第一晶体管具有一第一栅极结构，该第一栅极结构包含一界面层、一高介电常数介电层及一金属层；一形成在该第二区域中的第二晶体管；该第二晶体管具有一第二栅极结构，该第二栅极结构包含该界面层、该高介电常数介电层及该金属层，该金属层包含至少被混入两种元素，该至少两种元素距离该位于该高介电常数介电层及该金属层之间的界面至少
Figure G2009101735235D00022
以上，该至少两种元素使该金属层由一第一型功函数金属转变为一第二型功函数金属。
为让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举出优选实施例，并配合所附附图，作详细说明如下：
附图说明
图1为在高介电常数/金属栅极工艺中制造半导体装置的一实施例的流程图。
图2A～图2F为一系列依据图1所述方法制造半导体装置的剖面图。
【附图标记说明】
200～半导体装置202～基材
204～隔离结构206～NMOS装置
208～PMOS装置
210、210n、210p～界面层
212、212n、212p～高介电常数介电层
214～金属层
212n～N型金属
214p～P型金属
218～光致抗蚀剂层
225～去耦合等离子体处理
227～掺杂元素
240～多晶硅层
250～硬掩模层
261～NMOS装置的栅极图案
262～PMOS装置的栅极图案
281～NMOS装置的栅极结构
282～PMOS装置的栅极结构
具体实施方式
在本说明书的各种例子中可能会出现重复的元件符号以便简化描述，但这不代表在各个实施例及/或图示之间有何特定的关连。再者，当提到某一层在另一层“之上”或“上方”，可代表两层之间直接接触或中间还插有其他元件或膜层。各种元件可能以任意不同比例显示以使图示清晰简洁。
图1绘示在高介电常数/金属栅极工艺中，半导体装置的制造方法100的流程图。图2A至图2F绘示以图1方法100制造半导体装置200的一实施例于各个阶段相对应的工艺剖面示意图。并且，图1方法100中的部分步骤可应用于CMOS的制造流程中。因此，于方法100之前、之中或之后可提供额外的工艺，且其中某些工艺在此会作些简单的描述。此外，图2A至图2F仅为简化的图示以使本发明提供的概念能易于明了。
依据图1，方法100起始于方块110，其为在半导体基材上形成高介电常数材料。请参见图2A，半导体装置200包含例如为砖基材的半导体装置202。基材202可依照公知技术的需要包含各种掺杂形态。基材202也可包含其他元素半导体，例如锗或钻石。或者，基材202可包含化合物半导体及/或合金半导体。再者，基材202也可选择性地包含外延层(epi layer)、应变以增进效能(strained for performance enhancement)及绝缘层上覆硅(SOI)结构。
此半导体装置200可进一步包含隔离结构204，例如用以隔离基材202中的有源区206及208而形成于基材中的浅沟槽隔离(STI)元件。隔离结构204可由氧化硅、氮化硅、氮氧化硅、氟掺杂玻璃(FSG)及/或已公知的低介电常数材料形成。N型金属氧化物半导体晶体管装置(NMOS)为配置在有源区206上及P型金属氧化物半导体晶体管装置(PMOS)为配置在有源区208上。可以了解的是，半导体装置200的部分可由互补型金属氧化物半导体装置(CMOS)的工艺制造，故在此不多作赘述。
半导体装置200可进一步包含形成于基材202上的界面层210。界面层210可包含成长的氧化硅层，其厚度约为5至
Figure G2009101735235D00041
半导体装置200还可包含形成于界面层210上的高介电常数介电层212。高介电常数介电层212可包含HfO2。或者，高介电常数介电层212可选择性地包含其他高介电常数材料，例如HfSiO、HfSiON、HfTaO、HfTiO、HfZrO或前述的组合。高介电常数介电层212可由原子层沉积(ALD)、化学气相沉积(CVD)或其他合适技术形成。高介电常数介电层212的厚度约为10至
Figure G2009101735235D00042
接着，进行方块120的步骤，其为在高介电常数介电层上形成金属层，且该金属层具有第一功函数。半导体装置200还可包含在高介电常数介电层212上形成金属层214。此金属层214可包含N型功函数金属(N型金属)。例如，此金属层214可包含各种功函数小于4-33eV的各种金属。在一实施例中，此金属层包含钽或也可包含其他的N型金属(但不仅限于)锌、钛、铌、铝、银、锰、锆、铪及镧。金属层214可通过各种沉积技术像是物理气相沉积(PVD或溅镀)、化学气相沉积(CVD)、原子层沉积(ALD)、电镀或其他合适技术形成。此金属层214的厚度大于约
Figure G2009101735235D00051
在一实施例中，此金属层的厚度约在40至
Figure G2009101735235D00052
之间，优选为约
Figure G2009101735235D00053
接着，进行方块130的步骤，其为形成用以保护于该第一区域中的金属层的图案化掩模层。在本发明实施例中，可形成图案化光致抗蚀剂层218于NMOS装置206中的金属层214n上。此图案化光致抗蚀剂层218可通过光学微影(photolithography)、浸润式微影(immersion lithography)、离子束写入(ion-beam writing)或其他合适工艺形成。例如，光学微影工艺可包含旋转涂布(spin-coating)、软烘烤(soft-baking)、曝光、后烘烤(post-baking)、显影(developing)、润洗(rinsing)、干燥及其他合适工艺。或者，可形成图案化硬掩模层来取代光致抗蚀剂层以保护于NMOS装置206中的金属层214n。硬掩模层可由氧化硅、氮氧化硅、氮化硅或其他合适材料形成。首先可先形成图案化的光致抗蚀剂层于该硬掩模层上，然后再进行干或湿蚀刻以移除该硬掩模层位于PMOS区域中的部分。
接着，进行方块140的步骤，其为对在第二区域中未受保护的金属层进行去耦合等离子体工艺处理，如图2B所示。在本发明实施例中，对受到保护的金属层214p进行去耦合等离子体工艺处理225，此去耦合等离子体处理可使元素227混杂(incorporate)进入金属层214p的顶部，以使金属层214p的功函数由N型金属转变(或调整)为P型功函数金属(P型金属)。各种可作混杂的元素227包含碳、氮、硅、氧或前述任何可达到欲调整之功函数的组合。在一实施例中，可通过去耦合等离子体工艺225对钽(Ta)层进行碳化及氮化而转变为氮碳化钽(TaCN)层，而具有P型金属的效能。在各种实施例中，P型金属的功函数可约大于4.8eV。并且，可调整耦合式等离子体工艺225，以使元素227混杂进入的区域至少能距离位于金属层214p及高介电常数介电212之间的界面至少
Figure G2009101735235D00054
以上。如此，可降低或避免对高介电常数介电层212造成损伤的风险。并且，在NMOS装置206中的受保护的金属层214p也可继续维持为N型金属不变。如此，一单一金属层即可同时作为N型金属及P型金属。
去耦合等离子体工艺225可包含下列工艺参数在去耦合等离子体机台中进行：流量大于约100sccm的氮气(或其他包含氮的气体)、流量大于约100sccm的乙炔(或甲烷或其他含碳的气体)、大于约500W的射频功率(RFpower)(连续或脉冲式射频)、大于约10mTorr的压力及约在15至120秒之间的周期时间。值得注意的是，去耦合等离子体工艺225可提供高离子密度但低能量的等离子体，以使元素227仅混杂进入金属层214p的顶部界面，而不会穿透太深及降解(degrading)底下的高介电常数介电层212，这对于厚度仅有约为
Figure G2009101735235D00061
金属层214p是相当重要的。本发明在此仅揭示如上述少许实施例的各种参数，这些参数可用来调整达到所欲之功函数，而不会脱离本发明的精神及范围。例如，增加去耦合等离子体机台的射频功率及压力可创造出高离子密度但低离子能量的等离子体，以对金属轮廓在顶部表面作更多的修饰。
接着，进行方块150的步骤，其为进行退火工艺。进行退火工艺的温度范围约在800至1000℃之间。退火工艺可包含快速退火(RTA)、激光退火或其他合适的工艺。此退火工艺可确保PMOS装置208中的金属层214p中碳及氮元素的浓度，以稳定P型金属的功函数。如此，此退火工艺会促进金属层214p中碳及氮元素的键结。此退火工艺为在与已混杂元素(incorporated elements)相容的环境下进行，例如在氮气的环境下。
接着，进行方块160的步骤，其为在第一区域及第二区域中的金属层上形成多晶硅层，如图2C所示。图案化光致抗蚀剂层118可通过剥离(stripping)工艺或其他合适工艺移除，并可通过化学气相沉积(CVD)或其他合适沉积工艺来在N型金属214n及P型金属214p上形成多晶硅层240。此多晶硅层的厚度范围约在200至
Figure G2009101735235D00062
之间。
图2D显示为可在多晶硅层240上形成硬掩模层250。硬掩模层250可包含SiN、SiON、SiC、SiOC/PEOX、TEOS或其他合适材料。此外，可在硬掩模层250上形成抗反射涂布(anti-reflective coating；ARC)或底部抗反射涂布(bottom anti-reflective coating；BARC)，其都为公知的技术。
图2E显示为可在硬掩模层250上形成为图案化的光致抗蚀剂层。此光致抗蚀剂层可包含用于NMOS装置206的栅极图案261及用于PMOS装置208的栅极图案262。栅极图案261、262可由光学微影、浸润式微影或其他合适工艺来形成。
接着，进行方块170的步骤，其为在第一区域中形成第一栅极结构及在第二区域中形成第二栅极结构。图2F显示为以栅极图案261、262作为掩模，进行干蚀刻或湿蚀刻工艺来图案化掩模层250，并使用硬掩模层来图案化NMOS装置206中的栅极结构281及PMOS装置中的栅极结构282。栅极结构281、282可由干蚀刻或湿蚀刻工艺形成(栅极蚀刻或图案化)。随后可使用公知的技术将栅极图案261、262移除。
NMOS装置206中的栅极结构281可包含多晶硅层240n、金属层214n、高介电常数介电层212n及界面层210n。PMOS装置208中的栅极结构282可包含多晶硅层240p、P型金属214p、高介电常数介电层212p。值得注意的是，为了对栅极进行图案化，N型金属214n及P型金属214p可具有相似的厚度，且因此对NMOS装置206及PMOS装置208中的栅极进行图案化相较于后栅极工艺中NMOS装置206及PMOS装置208具有各种不同栅极厚度时会较为简单。
可了解的是，方法100可更进一步进行CMOS技术工艺的流程以形成各种已公知的元件。例如，在两边的栅极结构281、282旁形成轻掺杂源极/漏极区(LDD区)。并且，可由沉积及蚀刻工艺在栅极结构的两侧形成侧壁或栅极间隔物。此极间隔物可包含合适的介电材料，像是氮化硅、氧化硅、碳化硅、氮氧化硅或前述的组合。并且，可使用合适的N型或P型掺质(依据装置的结构，例如NMOS及PMOS)进行离子注入或扩散以形成源极/漏极区(S/D区)。
此外，可在基材上形成各种接触点(contacts)/通孔(vias)、金属结构及多层内连线元件(例如金属层及层间介电层)，以连接半导体装置200的各种结构及元件。例如，可由自我对准硅化(self-aligned silicide；salicide)形成硅化物元件，其步骤为在硅结构上形成金属层，然后升温作退火工艺并造成金属与其底下的硅进行反应而形成硅化物，接着再以蚀刻移除未反应的金属。可在各种元件像是源极、漏极及/或栅极电极上以自我对准硅化形成硅化物材料，减少接触电阻。并且，在基材上形成多个图案化的介电层及导电层，以形成多层内连线来连接各种P型及N型掺杂区域，像是源极、漏极、接触区域及栅极区域。在一实施例中，形成多层内连线(MLI)结构，并以层间介电层(ILD)相互隔离。在优选的例子中，此内连线结构包含在基材上形成接触点(contacts)、通孔、金属线。
本发明提供一种半导体装置，包含半导体、用以隔离第一区域及第二区域而形成在基材中的隔离结构，形成于第一区域中的第一晶体管，此第一晶体管具有第一栅极结构，其包含界面层、高介电常数介电层及混杂至少有两种元素的金属层，且此第一栅极结构中的金属层中的至少两种元素距离位于金属层及高介常数介电层之间的界面至少
Figure G2009101735235D00081
以上，此至少两种元素可使金属层由第一型功函数金属转变为第二型功函数金属，且此第二型功函数金属包含P型功函数金属。在其他实施例中，此金属层包含钽。在其他实施例中，此至少两种元素包含碳及氮。在一些其他实施例中，此金属层的厚度约为40至
Figure G2009101735235D00082
此外，虽然本发明在实施例中举例为可将N型金属转变为P型金属，然而，本发明也可应用于将P型金属转变成N型金属。并且，本发明所述的半导体装置并不仅限于晶体管，也可包含其他有源及无源装置，例如鳍式场效晶体管(FinFET)、高功率晶体管(high voltage transistor)、双载子晶体管(bipolar transistor)、电容、电阻、二极管、熔丝(fuse)或前述的组合。
本发明在各种实施例中达到了许多不同的优点。例如，本方法提供了简单且具有经济效益的单一金属层，其对NMOS装置及PMOS装置各自具有N型功函数金属及P型功函数金属。如此一来，欲对NMOS及PMOS装置中因相对应的栅极堆叠具有相似的厚度，使栅极结构的图案化变得相对较为简单。如此，NMOS装置及PMOS装置的性能变得更加可靠及可预测。并且，本方法适用于现有的CMOS技术工艺流程，因此可轻易地与现有的制造设备及装置技术作整合。另外，在本发明中于各个实施例会有不同的优点，且无须在每个实施例中都需要有特定的优点。
虽然本发明已以数个优选实施例揭示如上，然其并非用以限定本发明，任何所属技术领域中的技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与润饰，因此本发明的保护范围当视后附的权利要求所界定的范围为准。

Claims (15)

1.一种半导体装置的制造方法，包括：
提供具有一第一区域及一第二区域的一半导体基材；
形成一高介电常数介电层于该半导体基材上；
形成一金属层于该高介电常数介电层上，该金属层具有一第一功函数；
保护位于该第一区域的该金属层；
对该位于第二区域的该金属层进行一包含碳及氮的去耦合等离子体处理；以及
于该第一区域形成一第一栅极结构及于该第二区域形成一第二栅极结构，该第一栅极结构包含该高介电常数介电层及该金属层，该第二栅极结构包含该高介电常数层及该经处理的金属层。
2.如权利要求1所述的半导体装置的制造方法，其中该去耦合等离子体处理包含大于500W的射频功率、大于10mTorr的压力、流速大于100sccm的一含氮气体、流速大于100sccm的含碳气体及介于15-120秒的时间周期。
3.如权利要求2所述的半导体装置的制造方法，其中该含氮气体包含氮气。
4.如权利要求2所述的半导体装置的制造方法，其中该含碳气体包含乙烯或甲烷。
5.如权利要求1所述的半导体装置的制造方法，其中该第一功函数包含一N型功函数金属。
6.如权利要求1所述的半导体装置的制造方法，其中该第一金属层包含钽。
7.如权利要求1所述的半导体装置的制造方法，还包含在处理过程之后进行一退火工艺，该退火工艺的温度介于约800到1000℃之间。
8.如权利要求1所述的半导体装置的制造方法，还包含：
形成一界面层于该半导体基材及该高介电常数之间；以及
形成一多晶硅层位于该第一区域的该未经处理的金属层及位于该第二区域的该处理过的金属层上；
其中该第一及该工艺第二栅极结构都包含该界面层及该多晶硅层。
9.一种半导体装置的制造方法，包括：
提供具有一第一区域及一第二区域的一半导体基材；
形成一高介电常数介电层于该半导体基材上；
形成一N型功函数金属层(N型金属)于该半导体基材上；
对位于该第二区域上的N型金属层进行一去耦合等离子体处理，使至少两种元素进入位于该第二区域上的N型金属层中，该至少两种元素至少距离位于该高介电常数介电层及该N型金属层之间的界面
Figure A2009101735230003C1
以上；
进行一退火工艺；
形成一多晶硅层于该第一区域的N型金属层上及该第二区域的经处理过的N型金属层上；以及
形成一第一栅极结构于该第一区域中及形成一第二栅极结构于该第二区域中，该第一栅极结构包含该高介电常数介电层、该N型金属层及该多晶硅层，该第二栅极结构包含该高介电常数介电层、该经处理过的N型金属层及该多晶硅层。
10.如权利要求9所述的半导体装置的制造方法，其中该至少两种元素包含碳、氮、硅或氧的组合。
11.如权利要求9所述的半导体装置的制造方法，其中该N型金属层包含钽、镧、铪、锆、铝或钛。
12.如权利要求9所述的半导体装置的制造方法，其中该去耦合等离子体处理过程包含大于500W的射频功率、大于10mTorr的压力、流速大于100sccm的含氮气体、流速大于100sccm的含碳气体及介于15-120秒的周期时间。
13.一种半导体装置，包含：
一具有一第一区域及一第二区域的半导体装置；
一形成在该半导体基材中的隔离结构，用以隔离该第一区域及该第二区域；
一形成在该第一区域中的第一晶体管，该第一晶体管具有一第一栅极结构，该第一栅极结构包含一界面层、一高介电常数介电层及一金属层；
一形成在该第二区域中的第二晶体管；该第二晶体管具有一第二栅极结构，该第二栅极结构包含该界面层、该高介电常数介电层及该金属层，该金属层包含至少被混入两种元素，该至少两种元素距离该位于该高介电常数介电层及该金属层之间的界面至少以上，该至少两种元素使该金属层由一第一型功函数金属转变为一第二型功函数金属。
14.如权利要求13所述的半导体装置，其中该金属层包含钽。
15.如权利要求13所述的半导体装置，其中该至少两种元素包含碳及氮。
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