WO2011153845A1 - 一种用于cmos器件的双金属栅双高介质的集成方法 - Google Patents

一种用于cmos器件的双金属栅双高介质的集成方法 Download PDF

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WO2011153845A1
WO2011153845A1 PCT/CN2011/071129 CN2011071129W WO2011153845A1 WO 2011153845 A1 WO2011153845 A1 WO 2011153845A1 CN 2011071129 W CN2011071129 W CN 2011071129W WO 2011153845 A1 WO2011153845 A1 WO 2011153845A1
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gate
metal
metal gate
interface
etching
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PCT/CN2011/071129
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French (fr)
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徐秋霞
许高博
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中国科学院微电子研究所
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Priority to US13/129,743 priority Critical patent/US8748250B2/en
Publication of WO2011153845A1 publication Critical patent/WO2011153845A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures

Definitions

  • the invention belongs to the field of semiconductor technology, and particularly relates to a method for integrating a dual metal gate double high K gate dielectric for a CMOS device, which is suitable for a high performance nano complementary metal oxide semiconductor (CMOS) of 32/22 nm and below.
  • CMOS complementary metal oxide semiconductor
  • CMOS devices As the feature size of CMOS devices continues to shrink, the application of high dielectric constant (K) gate dielectrics and metal gate electrodes is imperative. With high-k gate dielectrics, the gate tunneling leakage current can be greatly reduced due to its thicker physical thickness at the same equivalent oxide thickness (EOT).
  • EOT equivalent oxide thickness
  • the conventional polysilicon gate is incompatible with the high ⁇ gate dielectric, and there is a serious Fermi pinning effect, so a new metal gate electrode must be used instead.
  • the metal gate not only eliminates the depletion effect of the polysilicon gate, reduces the gate resistance, but also eliminates boron penetration and improves device reliability.
  • the present invention provides an integrated method for a dual metal gate double high k dielectric for a CMOS device.
  • the main steps are as follows:
  • Step 1) After the conventional L0C0S or STI isolation is completed, the formation of the interface layer SiOx or SiON: rapid thermal annealing at 600 800 ° C for 20-120 seconds;
  • Step 2) forming a high dielectric constant gate dielectric film and thermally annealing at 600-1050 D C for 4-120 seconds;
  • Step 5) depositing a polysilicon film and a hard mask by a low pressure chemical vapor phase, and then performing photolithography and hard mask etching; step 6) removing the glue, masking with a hard mask, sequentially etching the polysilicon film/metal gate/ a high dielectric constant gate dielectric film forms a metal gate stacked structure;
  • Step 7) forming side wall 1 and source/drain extension regions with low energy ion implantation and large angle implantation;
  • Step 8) forming sidewall 2 and source/drain ion implantation
  • Step 9) Thermal annealing at 600-105CTC for 2 to 30 seconds; while the source/drain impurity is activated, metal ions are driven to the interface between the metal gate and the high dielectric constant gate dielectric film and the high dielectric constant gate At the interface between the dielectric film and the interface oxide layer, a stack is formed or a dipole is generated by an interface reaction, and the effective work function of the metal gate of the ⁇ OS device and the PMOS device is respectively realized;
  • Step 11) Contact and metallization: The alloy is annealed in the alloy furnace at N 2 or (N2+H2) for 30-60 minutes at a temperature of 380-450 °C.
  • the conventional L0C0S or STI isolated device is cleaned, firstly washed by a conventional method, and then immersed in a hydrofluoric acid/isopropanol/water mixed solution for 2-10 minutes at room temperature. , 1-2. 5% : 0. 01-0. 10 % : 1%.
  • the water is immersed in deionized water and simmered immediately after the drying.
  • the weight ratio of hydrofluoric acid: isopropyl alcohol: water is 0. 2-1. 5% : 0. 01-0. 10 % : 1%.
  • the interface layer in step 1 is formed by first injecting nitrogen and then rapidly annealing, or rapidly forming a SiOx by rapid thermal annealing, and then nitriding to form SiON; SiOx may also be formed by chemical treatment of 0 3 and then plasma nitriding.
  • the high dielectric constant gate dielectric film in step 2 is Hf0 2 , HfA10, HfAlON, HfSi0, HfSi0N, HfLaO or HfLaON, and the high dielectric constant gate dielectric film is subjected to physical vapor deposition, metal organic chemical vapor phase A deposition or atomic layer deposition process is formed.
  • the TiN metal gate in step 3 has a thickness of 5-100 nm.
  • the P-type or N-type metal ion implantation element in step 4 is Yb or Er or Tb for the NM0S device, and A1 or Ga or Pt for the PM0S device.
  • the hard mask in step 5 is Si0 2 , Si or its stack 0/N or 0/N/0.
  • step 6 the hard mask is fluorinated, the polysilicon is etched with F-based C1 or HBr plus C1, and the TiN, TaN or MoN metal gate is etched with C1-based reactive ions.
  • the NiSi in the step 10 is completed by sputtering an 8- 20 ran Ni film by two-step annealing and selective etching therebetween, and the NiSi film is 15-40 nm thick.
  • the method provided by the invention is characterized in that only one metal gate material and one high-k gate dielectric are used to dope the metal gate of the NM0S and PMOS devices by different ion implantation doping, and the metal ions are doped by high-temperature thermal annealing.
  • the adjustment of the effective work function of the corresponding metal gate achieves low threshold voltage control.
  • the present invention utilizes a physical vapor deposition (PVD) method to deposit a metal nitride film or a metal film on a high-k dielectric such as HfLaOH, HfSiON or the like as a metal gate electrode, and then into a metal gate electrode for an NM0S device.
  • PVD physical vapor deposition
  • Injecting elements such as Yb or Er or Tb
  • injecting elements such as A1 or Ga or Pt into the metal gate electrode
  • driving the doped metal ions into the interface between the metal gate and the high-k gate dielectric by high-temperature thermal annealing and
  • a stack is formed or a dipole is generated through an interface reaction, which results in a change in the effective work function of the gate, and the effective work function of the metal gate of the NM0S device and the PM0S device is respectively adjusted.
  • the amount of change is related to the type of metal gate material and the type of dopant ions, the profile of the concentration, and the reaction with the interface.
  • the invention greatly simplifies the complicated process of preparing the double metal gate and the double high K medium by the usual "deposition-lithography-corrosion-re-deposition-re-lithography and re-etching", and the operation is simple and controllable, and the cost is reduced. , fully compatible with conventional CMOS technology, facilitating the industrialization of integrated circuits.
  • Figure 1 compares the high-frequency C-V characteristics of TiTbN/HfLa (Tb) ON gate structures with different Tb contents in the metal gate TiTbN.
  • Figure 2 is a comparison of high-frequency C-V characteristics of TiGaN/HfLa(Ga) ON gate structures with different Ga contents in metal gate TiGaN. detailed description
  • the method for integrating a dual metal gate double high K medium for a CMOS device provided by the present invention has the following main steps:
  • Step 1) Cleaning After the device isolation is formed, the cleaning before the formation of the interface oxide layer is performed.
  • the method is cleaned, then immersed in a hydrofluoric acid/isopropanol/water mixed solution at room temperature, rinsed with deionized water, and then placed in a furnace immediately after drying; the weight ratio of hydrofluoric acid: isopropanol: water is 0. 2- 1. 5% : 0. 01-0. 10% : 1%;
  • Step 2) Interfacial layer Formation of SiOx or SiON: at 600-800. C, 20-120 seconds rapid thermal annealing; Step 3) high dielectric constant (K) formation of gate dielectric film;
  • Step 4) rapid thermal annealing after deposition of ft K medium thermal annealing at 600-1050 ° C for 4-120 seconds; step 5) formation of metal gate electrode: physical vapor deposition of TiN gate;
  • Step 6 using a photoresist as a mask, respectively performing P-type (or N-type) metal ion implantation on the PM0S (or NM0S) metal nitride gate for ion implantation doping;
  • Step 7) depositing a polysilicon film and a hard mask by a low-pressure chemical vapor deposition, and then performing photolithography and hard mask etching; Step 8) After de-glue, using a hard mask as a mask, sequentially etching the polysilicon film/metal gate / high K dielectric forming a metal gate laminated structure electrode;
  • Step 9) forming side wall -1 and source/drain extension regions with low energy ion implantation and large angle implantation;
  • Step 10 forming sidewall spacers 2 and source/drain ion implantation
  • Step 11 rapid thermal annealing at high temperature, thermal annealing at 600-1050 ° C for 2 to 30 seconds;
  • Step 12 NiSi silicide formation
  • the invention is characterized in that only one metal gate material and one high-k gate dielectric are used for different ion implantation doping of the metal gates of the NM0S and PMOS devices, and the metal ions are driven into the metal by high temperature thermal annealing.
  • a double metal gate and a double high-k dielectric are formed by the interface reaction, which leads to the adjustment of the effective work function of the respective gates.
  • the present invention greatly simplifies the complicated process flow of the conventional "deposition-lithography etching-re-deposition-re-lithography-re-etching" preparation of the double metal gate and the double high K medium, and the operation of the invention is simple and controllable. Improve product yield, and significantly reduce manufacturing costs, fully compatible with conventional CMOS processes, and facilitate the industrialization of integrated circuits.
  • Step 4) ultrasonic cleaning; ultrasonic cleaning with acetone and absolute ethanol for 5-10 minutes, rinsed with deionized water, dried in N 2 ;
  • Step 5 Rapid thermal annealing after deposition of high-k medium: the sheet is immediately dried and then fed into the furnace at a temperature of 600-100 CTC for 10-120 seconds.
  • Step 6) Metal nitride gate film deposition A TiN metal gate film is formed by sputtering a Ti target in a N 2 /Ar atmosphere by a magnetron reactive sputtering process, working pressure 5X1CT 13 3 ⁇ 4, ⁇ 2 flow 2-8 sccm, splashing The emission power is 600-100OOw, and the TiN film thickness is 5-100 nm.
  • Step 7) For the circle 0S, ion implantation of Tb into the TiN film: energy lOKev-120 Kev, dose 3X10 14 -5X10 cm 2 ;
  • Step 8) For PM0S, ion implantation into the TiN film: energy: 5 Kev-80 Kev, dose 3X10 I4 -4X10 ! 'Vcm 2 ;
  • Step 9) depositing a polysilicon film and a hard mask by a low-pressure chemical vapor phase, and then performing photolithography and hard mask etching; step 10) removing the glue, masking with a hard mask, sequentially etching the polysilicon film/metal gate/ High-k dielectric forms metal gate stacked structure electrodes: hard mask ⁇ CVD, polysilicon using HBr plus C1 based gas etching, TiTbN, TiGaN metal gate electrode using C1 based reactive ion etching to form metal gate electrode, RF Power 100-400W; Step 11) Forming sidewall 1 and source/drain extension low energy injection and large angle injection;
  • Step 12 forming sidewall spacers 2 and source/drain implants
  • Step 13 Rapid thermal annealing at high temperature, rapid thermal annealing at 800 to 1050 ° C for 2 to 30 seconds under nitrogen protection; driving metal ions to metal gate and high K gate while completing source/drain impurity activation
  • a stack is formed or a dipole is generated through the interface reaction, and the effective work function of the metal gate of the NM0S device and the PM0S device is respectively adjusted.
  • NiSi silicide Formation of NiSi silicide: NiSi is formed by sputtering 11-31 Ni thin films by two-step annealing and selective etching therebetween, and the NiSi film is 20-24 nm thick.
  • Fig. 1 it can be seen from Fig. 1 that as the implantation dose of Tb in the metal gate TiN increases, the CV characteristic curve moves largely in the negative direction, that is, the flat-band voltage of the metal gate largely moves in the negative direction, indicating that the effective work function of the NM0S device is large. The amplitude is reduced.
  • the Tb injection dose is 5.5E14cnf 2 compared with undoped Tb.
  • the voltage of the band is greatly shifted by 0.38V in the negative direction, which satisfies the needs of the NM0S device. It can be seen from Fig.
  • the C-V characteristic curve moves greatly in the positive direction, that is, the flat band voltage shifts to a large direction in the positive direction, indicating that the effective work function of the PM0S device is greatly increased.
  • the flat band voltage shifts significantly in the positive direction compared to undoped Ga, which is quite impressive.
  • the thickness of the equivalent oxide layer is greatly reduced. This is because Ga diffuses to the interface between the metal gate and the high-k gate dielectric and the interface between the high-k gate dielectric and the SiO2, and reacts with oxygen and nitrogen therein to further increase the K value of the medium.
  • the thickness of the interface SiO 2 layer is reduced, thereby causing the thickness of the equivalent oxide layer to be greatly reduced.

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Description

一种用于 CMOS器件的双金属栅双髙介质的集成方法 技术领域
本发明属于半导体技术领域， 特别指一种用于 CMOS器件的双金属栅双高 K栅介 质的集成方法，适合于 32/22纳米及以下技术代高性能纳米互补型金属氧化物半导体 (CMOS ) 器件的应用。 背景技术
随着 CMOS器件特征尺寸的不断缩小， 高介电常数（K)栅介质和金属栅电极的应 用势在必行。 釆用高 K栅介质， 由于其在同样等效氧化物厚度 （EOT) 下有较厚的物 理厚度， 所以可以大幅度降低栅隧穿漏电流。但是传统的多晶硅栅与高 κ栅介质不兼 容， 存在严重的费米钉扎效应， 所以必须釆用新型金属栅电极代替之。 金属栅不仅能 消除多晶硅栅的耗尽效应， 减小栅电阻， 还能消除硼穿透， 提高器件可靠性。 但是金 属栅集成到高 κ栅介质上仍有许多问题急待解决， 如热稳定性问题， 界面态问题， 特 别是费米钉扎效应使纳米 CMOS器件需要的适当低的阈值电压的获得面临很大挑战。 为了得到纳米 CMOS器件合适的阈值电压 ， 其 N管和 P管的有效功函数分别应在 Si 的导带底附近 （NM0S 4. leV左右） 和价带顶附近 （PM0S 5. 2eV左右）。 这样对丽 OS 和 PM0S往往需要各自合适的金属栅和高 K栅介质， 即需要双金属栅双高 K栅介质的 集成。通常制备双金属栅和双高 K介质的工艺流程非常繁杂，一般需要 "淀积 -光亥 IJ - 腐蚀-再淀积 -再光刻 再腐蚀" 的复杂工艺流程， 工艺很难控制， 成本高， 不便于大 规模生产。 发明内容
本发明的目的在于提供一种用于 CMOS器件的双金属栅双高 K栅介质的集成方法， 以改进公知技术中存在的缺陷。
为实现上述目的， 本发明提供的用于 CMOS器件的双金属栅双高 k介质的集成方 法， 主要步骤如下：
步骤 1 ) 在完成常规的 L0C0S或 STI隔离后， 界面层 SiOx或 SiON的形成： 于 600 800°C下， 20- 120秒快速热退火；
步骤 2 ) 高介电常数栅介质薄膜的形成， 并于 600- 1050DC下， 4- 120秒热退火； 步骤 3) 金属栅电极形成： 采用物理汽相淀积 TiN栅；
步骤 4)用光刻胶作掩模，先后分别采用 P型或 N型金属离子注入对 PM0S或 NM0S 金属氮化物栅分别进行离子注入掺杂；
步骤 5) 低压化学汽相淀积多晶硅膜和硬掩模， 然后进行光刻和硬掩膜的刻蚀； 步骤 6) 去胶， 以硬掩膜为掩蔽， 依次刻蚀多晶硅膜 /金属栅 /高介电常数栅介质 薄膜形成金属栅叠层结构；
步骤 7) 形成侧墙 1和源 /漏延伸区低能离子注入和大角度注入；
步骤 8) 形成侧墙 2和源 /漏离子注入；
步骤 9) 于 600- 105CTC下， 2- 30秒热退火； 在完成源 /漏杂质激活的同时， 将金 属离子驱动到金属栅与高介电常数栅介质薄膜的界面上和高介电常数栅介质薄膜与 界面氧化层界面上， 形成堆积或者通过界面反应生成偶极子， 分别实现对匪 OS 器件 和 PM0S器件金属栅有效功函数的调节；
步骤 10) NiSi硅化物形成；
步骤 11 ) 接触和金属化： 380- 450°C温度下， 在合金炉内 N2中或 （N2+H2) 中合 金退火 30-60分。
所述的方法中， 步骤 1之前对完成常规的 L0C0S或 STI隔离后的器件进行清洗， 先采用常规方法清洗， 然后用氢氟酸 /异丙醇 /水混合溶液在室温下浸泡 2-10分钟， 去离子水冲洗，甩干后立即进炉；氢氟酸：异丙醇:水的重量比为 0. 2-1. 5% : 0. 01-0. 10 % : 1%。
所述的方法中， 步骤 1中界面层是采用先注入氮再快速热退火形成， 或先快速热 退火形成 SiOx, 再氮化形成 SiON; SiOx也可用 03化学处理形成， 然后等离子氮化。
所述的方法中， 步骤 2 中高介电常数栅介质膜是 Hf02、 HfA10、 HfAlON, HfSi0、 HfSi0N、 HfLaO或 HfLaON, 所述高介电常数栅介质膜通过物理气相淀积、 金属有机化 学气相沉积或原子层淀积工艺形成。
所述的方法中， 步骤 3中的 TiN金属栅厚度为 5- 100nm。
所述的方法中，步骤 4中 P型或 N型金属离子注入元素，对 NM0S器件为 Yb或 Er 或 Tb; 对 PM0S器件为 A1或 Ga或 Pt。
所述的方法中， 步骤 5中的硬掩膜是 Si02、 Si具或其叠层 0/N或 0/N/0。
所述的方法中， 步骤 6中硬掩膜采用氟基刻蚀， 多晶硅釆用 F基加 C1基或 HBr 加 C1基刻蚀， TiN、 TaN或 MoN金属栅电极釆用 C1基反应离子刻蚀形成， 或采用化学 湿法腐蚀形成。
所述的方法中， 步骤 10中的 NiSi由溅射 8- 20ran Ni薄膜后， 通过两步退火和其 间的选择腐蚀完成， NiSi膜厚 15- 40nm。
本发明提供的方法， 其特点是只用一种金属栅材料和一种高 K 栅介质， 通过对 NM0S和 PM0S器件的金属栅进行不同的离子注入掺杂， 经过高温热退火将掺杂金属离 子驱进到金属栅与高 K栅介质的界面上和高 K栅介质与界面氧化层界面上，形成堆积 或者通过界面反应达到了实现双金属栅和双高 K介质的目的， 导致 N/PM0S各自相应 的金属栅有效功函数的调节， 实现了低的阈值电压的控制。本发明利用物理汽相淀积 (PVD)方法，在高 K介质如 HfLaOH、 HfSiON等上面淀积一层金属氮化物膜或金属膜， 作为金属栅电极， 然后对 NM0S器件， 往金属栅电极中注入 Yb或 Er或 Tb等元素， 对 PM0S器件， 往金属栅电极中注入 A1或 Ga或 Pt等元素， 通过高温热退火将掺杂金属 离子驱进到金属栅与高 K栅介质的界面上和高 K栅介质与界面氧化层界面上，形成堆 积或者通过界面反应生成偶极子， 导致栅有效功函数的改变， 分别实现对 NM0S 器件 和 PM0S器件金属栅有效功函数的调节。 改变量与金属栅材料及掺杂离子的种类、 浓 度的剖面分布及其与界面的反应情况有关。优化离子注入的能量、剂量和热处理条件， 可以获得合适的栅功函数， 以期获得合适的阈值电压。 可见， 本发明大大简化了通常 的 "淀积 -光刻 -腐蚀 -再淀积-再光刻 再腐蚀"制备双金属栅和双高 K介质的复杂工 艺流程， 操作简便可控， 减低了成本， 与常规 CMOS工艺完全兼容， 便于集成电路产 业化。 附图说明
图 1 为金属栅 TiTbN中 Tb含量不同的 TiTbN/HfLa (Tb) ON栅结构高频 C- V特性 的比较。
图 2为金属栅 TiGaN中 Ga含量不同的 TiGaN/HfLa(Ga) ON栅结构高频 C- V特性的 比较。 具体实施方式
本发明提供的用于 CMOS器件的双金属栅双高 K介质的集成方法， 其主要步骤如 下：
步骤 1 ) 清洗： 在器件隔离形成后， 进行界面氧化层形成前的清洗， 先采用常规 方法清洗， 然后用氢氟酸 /异丙醇 /水混合溶液在室温下浸泡， 去离子水冲洗， 甩干后 立即进炉； 氢氟酸：异丙醇：水的重量比为 0. 2-1. 5% : 0. 01-0. 10% : 1%；
步骤 2) 界面层 SiOx或 SiON的形成： 于 600- 800。C下， 20- 120秒快速热退火； 步骤 3) 高介电常数 （K) 栅介质薄膜的形成；
步骤 4) 淀积 ft K介质后快速热退火： 于 600- 1050°C下， 4- 120秒热退火； 步骤 5) 金属栅电极形成： 采用物理汽相淀积 TiN栅；
步骤 6)用光刻胶作掩模，先后分别釆用 P型（或 N型）金属离子注入对 PM0S (或 NM0S) 金属氮化物栅分别进行离子注入掺杂；
步骤 7) 低压化学汽相淀积多晶硅膜和硬掩模， 然后进行光刻和硬掩膜的刻蚀； 步骤 8) 去胶后， 以硬掩膜为掩蔽， 依次刻蚀多晶硅膜 /金属栅 /高 K介质形成金 属栅叠层结构电极；
步骤 9 ) 形成侧墙 -1和源 /漏延伸区低能离子注入和大角度注入；
步骤 10) 形成侧墙- 2和源 /漏离子注入；
步骤 11 ) 高温快速热退火， 于 600- 1050°C下， 2- 30秒热退火；
步骤 12) NiSi硅化物形成；
步骤 13 )接触和金属化： 380- 45CTC温度下，在合金炉内 N2中合金退火 30-60分。
本发明的特点是只用一种金属栅材料和一种高 K栅介质，通过对 NM0S和 PM0S 器件的金属栅进行不同的离子注入掺杂，经过高温热退火将掺杂金属离子驱进到金属 栅与高 K栅介质的界面上和高 K栅介质与界面氧化层界面上，形成堆积或者通过界面 反应形成了双金属栅和双高 K介质， 导致各自相应栅有效功函数的调节， 实现了低的 阈值电压的控制。 可见， 本发明大大简化了通常的 "淀积 -光刻 腐蚀-再淀积-再光刻 -再腐蚀"制备双金属栅和双高 K介质的复杂工艺流程， 本发明操作简便可控， 能提 高产品成品率， 而且大幅度降低制造成本， 与常规 CMOS工艺完全兼容， 便于集成电 路产业化。
以下对本发明作进一步的介绍。
步骤 1 ) 清洗： 在器件隔离形成后， 进行界面氧化层形成前的清洗， 先采用常规 方法清洗， 然后用氢氟酸:异丙醇：水 (重量比) =0. 3- 0. 8% : 0. 01-0. 08%: 1%混合溶液 在室温下浸泡 2-10分， 去离子水冲洗， N2中甩干后立即进炉；
步骤 2 )界面层 SiOx形成：在 600-800Ό温度下，在 N2中快速热退火（RTA) 20- 120 秒， 生成 6-8 的氧化层； 步骤 3) 高介电常数（K)栅介质薄膜的形成： 采用磁控反应溅射工艺在 N2/Ar气 氛中交替溅射 Hf- La靶和 Hf靶淀积形成 HfLaON, 溅射工作压强为 5X 10 orr， 溅射 功率为 100- 500W, 淀积形成的 HfLaON高 k栅介质薄膜厚 10-60埃；
步骤 4)超声清洗； 采用丙酮、无水乙醇先后各超声清洗 5-10分钟， 去离子水冲 洗， N2 中甩干；
步骤 5)淀积高 K介质后快速热退火：片子甩干后立即进炉，温度 600- 100CTC, 时 间 10-120秒。
步骤 6) 金属氮化物栅薄膜淀积： 采用磁控反应溅射工艺在 N2/Ar气氛中溅射 Ti 靶形成 TiN 金属栅薄膜， 工作压强 5X1CT13 ¾， Ν2流量 2-8 sccm, 溅射功率为 600-lOOOw, TiN膜厚度 5- 100纳米。
步骤 7) 对 圆 0S， 往 TiN 膜中离子注入 Tb: 能量 lOKev- 120 Kev, 剂量 3X1014-5X10 cm2 ；
步骤 8) 对 PM0S， 往 TiN 膜中离子注入 Ga: 能量 5 Kev- 80 Kev, 剂量 3X10I4-4X10!'Vcm2 ;
步骤 9) 低压化学汽相淀积多晶硅膜和硬掩模， 然后进行光刻和硬掩膜的刻蚀； 步骤 10)去胶， 以硬掩膜为掩蔽， 依次刻蚀多晶硅膜 /金属栅 /高 K介质形成金属 栅叠层结构电极： 硬掩模釆用氟基刻蚀， 多晶硅采用 HBr加 C1基气体刻蚀， TiTbN、 TiGaN金属栅电极采用 C1基反应离子刻蚀形成金属栅电极， 射频功率 100- 400W; 步骤 11) 形成侧墙 -1和源 /漏延伸区低能注入和大角度注入；
步骤 12) 形成侧墙- 2和源 /漏注入；
步骤 13) 高温快速热退火， 在氮气保护下， 在 800至 1050° C温度下快速热退火 2至 30秒； 在完成源 /漏杂质激活的同时， 将金属离子驱动到金属栅与高 K栅介质的 界面上和高 K栅介质与界面氧化层界面上， 形成堆积或者通过界面反应生成偶极子， 分别实现对 NM0S 器件 和 PM0S器件金属栅有效功函数的调节。
步骤 12) NiSi硅化物形成： NiSi由溅射 11- 13麵 Ni薄膜后， 通过两步退火和其 间的选择腐蚀完成， NiSi膜厚 20- 24nm。
步骤 13) 接触和金属化： 380-45CTC度下， 在合金炉内 N2中合金退火 30- 60分。 由图 1可见， 随金属栅 TiN中 Tb的注入剂量的增加， C-V特性曲线向负方向大 幅度移动， 即金属栅的平带电压大幅度地向负方向移动， 表明 NM0S器件的有效功函 数大幅度减小。 由表 1可见， 在 Tb注入剂量为 5.5E14cnf2下， 与不掺杂 Tb比较， 平 带电压向负方向大幅度移动了 0. 38V, 极好地满足了 NM0S器件的需要。 由图 2可见， 随金属栅 TiGaN中 Ga注入剂量增加， C- V特性曲线向正方向大幅 度移动， 即平带电压向正方向大幅度移动， 表明 PM0S器件的有效功函数大幅度增加。 在中等 Ga注入剂量下， 与不掺杂 Ga比较， 平带电压向正方向大幅度移动了 IV, 非 常可观。 而且等效氧化层厚度大大减薄， 这是由于 Ga扩散到金属栅与高 K栅介质界 面处及高 K栅介质与 Si02界面处， 与其中的氧、 氮反应， 进一步提高了介质的 K值， 同时减小了界面 Si02层的厚度， 从而使等效氧化层厚度大大降低所致。
以上所述仅为本发明的较佳实施例， 并不用以限制本发明， 凡在本发明的精神和 原则之内，所作的任何修改、等同替换、改进等， 均应包含在本发明的保护范围之内。
表 1
Figure imgf000007_0001

Claims

1、 一种用于 CMOS器件的双金属栅双高 k栅介质的集成方法， 主要步骤如下- 步骤 1 ) 在完成常规的 L0C0S或 STI隔离后， 界面层 SiOx或 SiON的形成： 于 600- 800°C下， 20- 120秒快速热退火；
步骤 2) 高介电常数栅介质薄膜的形成， 并于 600- 1050°C下， 4- 120秒热退火； 步骤 3) 金属栅电极形成： 采用物理汽相淀积 TiN栅；
步骤 4)用光刻胶作掩模，先权后分别采用 P型或 N型金属离子注入对 PM0S或匪 0S 金属氮化物栅分别进行离子注入掺杂；
步骤 5) 低压化学汽相淀积多晶硅膜和硬掩模， 然后进行光刻和硬掩膜的刻蚀； 步骤 6) 去胶， 以硬掩膜为掩蔽， 依次刻蚀多晶硅膜 /金属栅 /高介电常数栅介质 薄膜形成金属栅叠层结构； 求
步骤 7 ) 形成侧墙 1和源 /漏延伸区低能离子注入和大角度注入；
步骤 8 ) 形成侧墙 2和源 /漏离子注入；
步骤 9 ) 于 600- 105CTC下， 2- 30秒热退火； 在完成源 /漏杂质激活的同时， 将金 属离子驱动到金属栅与高介电常数栅介质薄膜的界面上和高介电常数栅介质薄膜与 界面氧化层界面上， 形成堆积或者通过界面反应生成偶极子， 分别实现对 NM0S 器件 和 PM0S器件金属栅有效功函数的调节；
步骤 10) NiSi硅化物形成；
步骤 11 ) 接触和金属化： 380- 450°C温度下， 在合金炉内 N2中或 （N2+H2) 中合 金退火 30-60分。
2、 根据权利要求 1所述的方法， 其中， 步骤 1之前对完成常规的 L0C0S或 STI 隔离后的器件进行清洗， 先采用常规方法清洗， 然后用氢氟酸 /异丙醇 /水混合溶液在 室温下浸泡 2- 10分钟， 去离子水冲洗， 甩干后立即进炉； 氢氟酸:异丙醇：水的重量 比为 0. 2-1. 5% : 0. 01-0. 10% : l%o
3、 根据权利要求 1所述的方法， 其中， 步骤 1 中界面层是釆用先注入氮再快速 热退火形成， 或先快速热退火形成 Si0x， 再氮化形成 SiON; SiOx也可用 03化学处理 形成， 然后等离子氮化。
4、 根据权利要求 1所述的方法， 其中， 步骤 2 中高介电常数栅介质膜是 Hf02、 HfA10、 HfA10N、 HfSi0、 HfSi0N、 HfLaO或 HfLaON, 所述高介电常数栅介质膜通过物 理气相淀积、 金属有机化学气相沉积或原子层淀积工艺形成。
5、 根据权利要求 1所述的方法， 其中， 步骤 3中的 TiN金属栅厚度为 5- 100nm
6、 根据权利要求 1所述的方法， 其中， 步骤 4中 P型或 N型金属离子注入元素， 对匪 OS器件为 Yb或 Er或 Tb; 对 PM0S器件为 A1或 Ga或 Pt
7、 根据权利要求 1所述的方法， 其中， 步骤 5中的硬掩膜是 Si02 Si 或其叠 层 0/N或 0/N/0
8、 根据权利要求 1所述的方法， 其中， 步骤 6中硬掩膜采用氟基刻蚀， 多晶硅 采用 F基加 C1基或 HBr加 C1基刻蚀， TiN TaN或 MoN金属栅电极采用 C1基反应离 子刻蚀形成， 或采用化学湿法腐蚀形成。
9、 根据权利要求 1所述的方法， 其中， 步骤 10中的 NiSi由溅射 8- 20nm Ni薄 膜后， 通过两步退火和其间的选择腐蚀完成， NiSi膜厚 15- 40
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