CN101675513A - 高k栅极介电质互补金属氧化物半导体结构的阈值调整 - Google Patents
高k栅极介电质互补金属氧化物半导体结构的阈值调整 Download PDFInfo
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- CN101675513A CN101675513A CN200880014505A CN200880014505A CN101675513A CN 101675513 A CN101675513 A CN 101675513A CN 200880014505 A CN200880014505 A CN 200880014505A CN 200880014505 A CN200880014505 A CN 200880014505A CN 101675513 A CN101675513 A CN 101675513A
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Images
Classifications
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28176—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the definitive gate conductor
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/981—Utilizing varying dielectric thickness
Abstract
Description
Claims (20)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/743,101 US20080272437A1 (en) | 2007-05-01 | 2007-05-01 | Threshold Adjustment for High-K Gate Dielectric CMOS |
US11/743,101 | 2007-05-01 | ||
PCT/EP2008/054218 WO2008132026A1 (en) | 2007-05-01 | 2008-04-08 | Threshold adjustment for high-k gate dielectric cmos |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101675513A true CN101675513A (zh) | 2010-03-17 |
CN101675513B CN101675513B (zh) | 2011-07-13 |
Family
ID=39511049
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN200880014505.6A Expired - Fee Related CN101675513B (zh) | 2007-05-01 | 2008-04-08 | 高k栅极介电质互补金属氧化物半导体结构的阈值调整 |
Country Status (7)
Country | Link |
---|---|
US (2) | US20080272437A1 (zh) |
EP (1) | EP2165359B1 (zh) |
JP (1) | JP4917171B2 (zh) |
KR (1) | KR20090130845A (zh) |
CN (1) | CN101675513B (zh) |
TW (1) | TW200845384A (zh) |
WO (1) | WO2008132026A1 (zh) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
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CN102280376A (zh) * | 2010-06-08 | 2011-12-14 | 中国科学院微电子研究所 | 一种用于cmos器件的双金属栅双高介质的集成方法 |
CN102299111A (zh) * | 2010-06-23 | 2011-12-28 | 中芯国际集成电路制造(上海)有限公司 | 制作互补型金属氧化物半导体器件结构的方法 |
CN102347357A (zh) * | 2010-07-30 | 2012-02-08 | 中国科学院微电子研究所 | Mosfet结构及其制作方法 |
CN103890905A (zh) * | 2011-10-19 | 2014-06-25 | 国际商业机器公司 | FinFET结构和用于调整FinFET结构中的阈值电压的方法 |
CN104347507A (zh) * | 2013-07-24 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件的形成方法 |
CN105470295A (zh) * | 2014-09-09 | 2016-04-06 | 联华电子股份有限公司 | 鳍状结构及其制造方法 |
Families Citing this family (18)
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US7618868B2 (en) * | 2006-05-03 | 2009-11-17 | Samsung Electronics Co., Ltd. | Method of manufacturing field effect transistors using sacrificial blocking layers |
JP4994139B2 (ja) * | 2007-07-18 | 2012-08-08 | パナソニック株式会社 | 半導体装置及びその製造方法 |
JP5315784B2 (ja) * | 2008-05-14 | 2013-10-16 | 日本電気株式会社 | 半導体装置 |
US7932150B2 (en) * | 2008-05-21 | 2011-04-26 | Kabushiki Kaisha Toshiba | Lateral oxidation with high-K dielectric liner |
KR101448172B1 (ko) * | 2008-07-02 | 2014-10-08 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
JP5238627B2 (ja) * | 2009-06-26 | 2013-07-17 | 株式会社東芝 | 半導体装置およびその製造方法 |
CN102110651B (zh) * | 2009-12-29 | 2014-01-29 | 中国科学院微电子研究所 | 一种半导体器件及其制造方法 |
US8268689B2 (en) | 2010-08-23 | 2012-09-18 | International Business Machines Corporation | Multiple threshold voltages in field effect transistor devices |
US8304306B2 (en) | 2011-03-28 | 2012-11-06 | International Business Machines Corporation | Fabrication of devices having different interfacial oxide thickness via lateral oxidation |
KR20120125017A (ko) * | 2011-05-06 | 2012-11-14 | 삼성전자주식회사 | 반도체 장치 및 그 제조방법 |
US20130049134A1 (en) * | 2011-08-30 | 2013-02-28 | Renesas Electronics Corporation | Semiconductor device and method of making same |
DE102012205977B4 (de) * | 2012-04-12 | 2017-08-17 | Globalfoundries Inc. | Halbleiterbauelement mit ferroelektrischen Elementen und schnellen Transistoren mit Metallgates mit großem ε sowie Herstellungsverfahren |
US8809920B2 (en) * | 2012-11-07 | 2014-08-19 | International Business Machines Corporation | Prevention of fin erosion for semiconductor devices |
US9466492B2 (en) | 2014-05-02 | 2016-10-11 | International Business Machines Corporation | Method of lateral oxidation of NFET and PFET high-K gate stacks |
US10050147B2 (en) * | 2015-07-24 | 2018-08-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and manufacturing method thereof |
US9627484B1 (en) * | 2015-10-12 | 2017-04-18 | International Business Machines Corporation | Devices with multiple threshold voltages formed on a single wafer using strain in the high-K layer |
US11088258B2 (en) | 2017-11-16 | 2021-08-10 | Samsung Electronics Co., Ltd. | Method of forming multiple-Vt FETs for CMOS circuit applications |
KR20210013833A (ko) | 2019-07-29 | 2021-02-08 | 삼성전자주식회사 | 반도체 장치 |
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US5710450A (en) * | 1994-12-23 | 1998-01-20 | Intel Corporation | Transistor with ultra shallow tip and method of fabrication |
US5858866A (en) * | 1996-11-22 | 1999-01-12 | International Business Machines Corportation | Geometrical control of device corner threshold |
JP2002026139A (ja) * | 2000-06-30 | 2002-01-25 | Toshiba Corp | 半導体装置及び半導体装置の製造方法 |
JP2002141420A (ja) * | 2000-10-31 | 2002-05-17 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
JP2003031806A (ja) * | 2001-05-09 | 2003-01-31 | Hitachi Ltd | Mosトランジスタ及びその製造方法 |
US6514839B1 (en) * | 2001-10-05 | 2003-02-04 | Taiwan Semiconductor Manufacturing Company | ESD implantation method in deep-submicron CMOS technology for high-voltage-tolerant applications with light-doping concentrations |
US6605501B1 (en) * | 2002-06-06 | 2003-08-12 | Chartered Semiconductor Manufacturing Ltd. | Method of fabricating CMOS device with dual gate electrode |
CN1412826A (zh) * | 2002-12-04 | 2003-04-23 | 中芯国际集成电路制造(上海)有限公司 | 制造双扩散漏极高电压器件的工艺方法 |
JP2004303789A (ja) * | 2003-03-28 | 2004-10-28 | Toshiba Corp | 半導体装置及びその製造方法 |
US6946709B2 (en) * | 2003-12-02 | 2005-09-20 | International Business Machines Corporation | Complementary transistors having different source and drain extension spacing controlled by different spacer sizes |
US7148548B2 (en) * | 2004-07-20 | 2006-12-12 | Intel Corporation | Semiconductor device with a high-k gate dielectric and a metal gate electrode |
JP4938262B2 (ja) * | 2004-08-25 | 2012-05-23 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US7064066B1 (en) * | 2004-12-07 | 2006-06-20 | Intel Corporation | Method for making a semiconductor device having a high-k gate dielectric and a titanium carbide gate electrode |
US7488656B2 (en) * | 2005-04-29 | 2009-02-10 | International Business Machines Corporation | Removal of charged defects from metal oxide-gate stacks |
JP4220509B2 (ja) * | 2005-09-06 | 2009-02-04 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
US7432567B2 (en) * | 2005-12-28 | 2008-10-07 | International Business Machines Corporation | Metal gate CMOS with at least a single gate metal and dual gate dielectrics |
US20070152276A1 (en) * | 2005-12-30 | 2007-07-05 | International Business Machines Corporation | High performance CMOS circuits, and methods for fabricating the same |
JP4528727B2 (ja) * | 2006-01-23 | 2010-08-18 | 株式会社東芝 | 半導体装置の製造方法 |
-
2007
- 2007-05-01 US US11/743,101 patent/US20080272437A1/en not_active Abandoned
-
2008
- 2008-04-08 KR KR1020097014372A patent/KR20090130845A/ko active IP Right Grant
- 2008-04-08 CN CN200880014505.6A patent/CN101675513B/zh not_active Expired - Fee Related
- 2008-04-08 JP JP2010504608A patent/JP4917171B2/ja not_active Expired - Fee Related
- 2008-04-08 EP EP08735946A patent/EP2165359B1/en not_active Not-in-force
- 2008-04-08 WO PCT/EP2008/054218 patent/WO2008132026A1/en active Application Filing
- 2008-05-01 TW TW097116080A patent/TW200845384A/zh unknown
-
2009
- 2009-08-04 US US12/535,554 patent/US8187961B2/en not_active Expired - Fee Related
Cited By (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102280376A (zh) * | 2010-06-08 | 2011-12-14 | 中国科学院微电子研究所 | 一种用于cmos器件的双金属栅双高介质的集成方法 |
WO2011153845A1 (zh) * | 2010-06-08 | 2011-12-15 | 中国科学院微电子研究所 | 一种用于cmos器件的双金属栅双高介质的集成方法 |
CN102280376B (zh) * | 2010-06-08 | 2013-01-02 | 中国科学院微电子研究所 | 一种用于cmos器件的双金属栅双高介质的集成方法 |
US8748250B2 (en) | 2010-06-08 | 2014-06-10 | Institute of Microelectronics, Chinese Academy of Sciences | Method for integration of dual metal gates and dual high-K dielectrics in CMOS devices |
CN102299111A (zh) * | 2010-06-23 | 2011-12-28 | 中芯国际集成电路制造(上海)有限公司 | 制作互补型金属氧化物半导体器件结构的方法 |
CN102299111B (zh) * | 2010-06-23 | 2013-12-11 | 中芯国际集成电路制造(上海)有限公司 | 制作互补型金属氧化物半导体器件结构的方法 |
CN102347357A (zh) * | 2010-07-30 | 2012-02-08 | 中国科学院微电子研究所 | Mosfet结构及其制作方法 |
CN102347357B (zh) * | 2010-07-30 | 2013-11-06 | 中国科学院微电子研究所 | Mosfet结构及其制作方法 |
CN103890905A (zh) * | 2011-10-19 | 2014-06-25 | 国际商业机器公司 | FinFET结构和用于调整FinFET结构中的阈值电压的方法 |
CN103890905B (zh) * | 2011-10-19 | 2016-05-25 | 国际商业机器公司 | FinFET结构和用于调整FinFET结构中的阈值电压的方法 |
CN104347507A (zh) * | 2013-07-24 | 2015-02-11 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件的形成方法 |
CN104347507B (zh) * | 2013-07-24 | 2017-07-14 | 中芯国际集成电路制造(上海)有限公司 | 半导体器件的形成方法 |
CN105470295A (zh) * | 2014-09-09 | 2016-04-06 | 联华电子股份有限公司 | 鳍状结构及其制造方法 |
US10418251B2 (en) | 2014-09-09 | 2019-09-17 | United Microelectronics Corp. | Method of forming fin-shaped structure having ladder-shaped cross-sectional profile |
CN105470295B (zh) * | 2014-09-09 | 2020-06-30 | 联华电子股份有限公司 | 鳍状结构及其制造方法 |
US10930517B2 (en) | 2014-09-09 | 2021-02-23 | United Microelectronics Corp. | Method of forming fin-shaped structure |
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JP4917171B2 (ja) | 2012-04-18 |
CN101675513B (zh) | 2011-07-13 |
TW200845384A (en) | 2008-11-16 |
US20080272437A1 (en) | 2008-11-06 |
US20090291553A1 (en) | 2009-11-26 |
KR20090130845A (ko) | 2009-12-24 |
JP2010525590A (ja) | 2010-07-22 |
WO2008132026A1 (en) | 2008-11-06 |
EP2165359A1 (en) | 2010-03-24 |
US8187961B2 (en) | 2012-05-29 |
EP2165359B1 (en) | 2012-06-27 |
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