CN102110651B - 一种半导体器件及其制造方法 - Google Patents
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Abstract
一种半导体器件及其制造方法,所述方法在形成栅堆叠后,在PMOS栅堆叠的侧壁形成第二侧墙缓冲层,所述第二侧墙缓冲层由疏松的低k介质材料形成;而后形成器件的侧墙及源漏/halo区和源、漏极区;而后在氧环境中高温退火,以使氧气环境中的氧气通过所述第二侧墙缓冲层扩散到所述第二栅堆叠的高k栅介质层中。通过本发明不仅降低PMOS的阈值电压,且不影响NMOS器件的阈值电压,而且还可以避免传统工艺去除PMOS侧墙时对栅极及衬底的损伤,从而有效提高器件的整体性能。
Description
技术领域
本发明通常涉及一种半导体器件及其制造方法,具体来说,涉及一种可以降低高k栅介质/金属栅器件的PMOS阈值电压的器件及其制造方法。
背景技术
随着半导体技术的发展,具有更高性能和更强功能的集成电路要求更大的元件密度,而且各个部件、元件之间或各个元件自身的尺寸、大小和空间也需要进一步缩小。32/22纳米工艺集成电路核心技术的应用已经成为集成电路发展的必然趋势,也是国际上主要半导体公司和研究组织竞相研发的课题之一。以“高k栅介质/金属栅”技术为核心的CMOS器件栅工程研究是32/22纳米技术中最有代表性的核心工艺,与之相关的材料、工艺及结构研究已在广泛的进行中。
对于将高k栅介质材料和金属栅集成在一起的器件,实现了具有高迁移率沟道的晶体管,但是由于在集成中的高温处理,使金属和高k绝缘材料交界面的性质发生改变,引起了高k栅介质材料中的氧空位,这使PMOS的阈值电压升高,进而降低了器件的可靠性,如何有效控制PMOS阈值电压是“高k栅介质/金属栅”器件的首要问题。目前降低“高k栅介质/金属栅”器件PMOS阈值电压的一种方法是氧扩散的方法(Symposium on VLSItechnology Digest of Technical Papers,2009),该方法是将侧墙去除后,从高k/金属栅的侧壁扩散氧到高k栅介质材料中,但这种方法需要将侧墙去除,去除侧墙在工艺上比较难控制,会对栅介质层、栅电极以及源/漏区衬底等造成损伤,进而影响器件的性能。
因此,需要提出一种能够降低PMOS器件的阈值电压,且不会对器件造成损伤的制造半导体器件的方法及其器件结构。
发明内容
鉴于上述问题,本发明提供了一种制造所述半导体器件的方法,所述方法包括:提供具有NMOS区域和PMOS区域的半导体衬底,其中所述NMOS区域与所述PMOS区域相互隔离;在所述NMOS区域的半导体衬底上形成第一栅堆叠,在所述PMOS区域的半导体衬底上形成第二栅堆叠,其中所述第一栅堆叠的形成包括形成第一高k栅介质层和其上的第一金属栅电极,所述第二栅堆叠的形成包括形成第二高k栅介质层和其上的第二金属栅电极;在所述第二栅堆叠的侧壁形成第二侧墙缓冲层,其中所述第二侧墙缓冲层采用低k介质材料形成;在所述第一栅堆叠的侧壁形成第一侧墙,并且在所述第二侧墙缓冲层的侧壁形成第二侧墙;在所述半导体衬底中分别形成属于NMOS区域和PMOS区域的源/漏延伸区和/或halo区以及源极区和漏极区;对所述器件在氧气环境进行退火,以使氧气环境中的氧气通过所述第二侧墙缓冲层扩散到所述第二栅堆叠的第二高k栅介质层中。其中形成所述第二侧墙缓冲层的低k介质材料的相对介电常数小于3.5,形成所述第二侧墙缓冲层的低k介质材料包括:SiCOH、SiO或SiCO,所述第二侧墙缓冲层的厚度为大约1至100纳米。
本发明还提供了另一种制造所述半导体器件的方法,所述方法包括:提供具有NMOS区域和PMOS区域的半导体衬底,其中所述NMOS区域与所述PMOS区域相互隔离;在所述NMOS区域的半导体衬底上形成第一栅堆叠,在所述PMOS区域的半导体衬底上形成第二栅堆叠,其中所述第一栅堆叠的形成包括形成第一高k栅介质层和其上的第一金属栅电极,所述第二栅堆叠的形成包括形成第二高k栅介质层和其上的第二金属栅电极;在所述第二栅堆叠的侧壁形成第二侧墙缓冲层,其中所述第二侧墙缓冲层采用低k介质材料形成;在所述第一栅堆叠的侧壁形成第一侧墙,在所述第二侧墙缓冲层的侧壁形成第二侧墙;在所述半导体衬底中分别形成属于NMOS区域和PMOS区域的源/漏延伸区和/或halo区以及源极区和漏极区;去除所述第二侧墙;对所述器件在氧气环境进行退火,以使氧气环境中的氧气通过所述第二侧墙缓冲层扩散到所述第二栅堆叠的高k栅介质层中。其中形成所述第二侧墙缓冲层的低k介质材料的相对介电常数小于3.5,形成所述第二侧墙缓冲层的低k介质材料包括:SiCOH、SiO或SiCO,所述第二侧墙缓冲层的厚度为大约1至100纳米。
本发明还提供了由以上方法制造的器件,所述器件包括:具有NMOS区域和PMOS区域的半导体衬底,其中所述NMOS区域与所述PMOS区域相互隔离;形成于所述NMOS区域的半导体衬底上的第一栅堆叠和形成于所述PMOS区域的半导体衬底上的第二栅堆叠;其中所述第一栅堆叠包括:第一高k栅介质层;形成于所述第一高k栅介质层上的第一金属栅电极;所述第二栅堆叠包括:第二高k栅介质层;形成于所述第二高k栅介质层上的第二金属栅电极;其中所述第二栅堆叠侧壁有第二侧墙缓冲层,所述第二侧墙缓冲层可以使器件在氧环境中退火时,使氧环境中的氧气通过所述第二侧墙缓冲层扩散至所述第二栅堆叠的第二高k栅介质层中。其中所述第二侧墙缓冲层采用低k介质材料形成,所述第二侧墙缓冲层的厚度为大约1至100纳米。
通过采用本发明所述的器件结构及制造方法,不仅可以使氧原子扩散至PMOS所在的高k栅介质材料层中,进而降低PMOS器件的阈值电压,且不影响NMOS器件的阈值电压,而且还可以避免传统工艺去除PMOS侧墙时对栅极及衬底的损伤,从而有效提高器件的整体性能。
附图说明
图1示出了根据本发明的第一实施例的半导体器件的制造方法的流程图;
图2-6示出了根据本发明的第一实施例的半导体器件各个制造阶段的示意图;
图7示出了根据本发明的第二实施例的半导体器件的制造方法的流程图;
图8示出了根据本发明的第二实施例的半导体器件各个制造阶段的示意图。
具体实施方式
本发明通常涉及半导体器件及其制造方法。下文的公开提供了许多不同的实施例或例子用来实现本发明的不同结构。为了简化本发明的公开,下文中对特定例子的部件和设置进行描述。当然,它们仅仅为示例,并且目的不在于限制本发明。此外,本发明可以在不同例子中重复参考数字和/或字母。这种重复是为了简化和清楚的目的,其本身不指示所讨论各种实施例和/或设置之间的关系。此外,本发明提供了的各种特定的工艺和材料的例子,但是本领域普通技术人员可以意识到其他工艺的可应用于性和/或其他材料的使用。另外,以下描述的第一特征在第二特征之“上”的结构可以包括第一和第二特征形成为直接接触的实施例,也可以包括另外的特征形成在第一和第二特征之间的实施例,这样第一和第二特征可能不是直接接触。
第一实施例
根据本发明的第一实施例,参考图1,图1示出了根据本发明的实施例的半导体器件的制造方法的流程图。在步骤101,提供具有NMOS区域201和PMOS区域202的半导体衬底200,其中所述NMOS区域201与PMOS区域202相互隔离,参考图2。在本实施例中,衬底200包括位于晶体结构中的硅衬底(例如晶片),还可以包括其他基本半导体或化合物半导体,例如Ge、GeSi、GaAs、InP、SiC或金刚石等。根据现有技术公知的设计要求(例如p型衬底或者n型衬底),衬底200可以包括各种掺杂配置。此外,衬底200可以可选地包括外延层,可以被应力改变以增强性能,以及可以包括绝缘体上硅(SOI)结构。
在步骤102,在所述NMOS区域201的半导体衬底200上形成第一栅堆叠300,在所述PMOS区域202的半导体衬底200上形成第二栅堆叠400,如图2所示。其中所述第一栅堆叠300和第二栅堆叠400为包括高k栅介质和金属栅极的多层栅堆叠结构。在本实施例中,在半导体衬底200上依次沉积高k介质层为HfO2、金属栅电极为TiN以及多晶硅层为多晶硅,而后利用干法或湿法刻蚀技术将其图形化,分别形成属于NMOS区域201的包括第一高k栅介质层204、第一金属栅电极208和第一多晶硅层212的第一栅堆叠300,属于PMOS区域202的包括第二高k栅介质层206、第二金属栅电极210和第二多晶硅层214的第二栅堆叠400,如图2所示,这仅仅是作为示例,不局限于此,所述第一栅堆叠300和第二栅堆叠400还可以是包括高k栅介质层和金属栅极层的其他多层栅堆叠结构。所述高k介质层的材料还可以是HfZrOX、Al2O3或Gd2O3等。所述金属栅电极的材料还可以是TaN、Ta2C、HfN、HfC、TiC、Mo或Ru等。所述栅堆叠的沉积可以使用例如化学气相沉积(CVD)、物理气相沉积(PVD)、原子层沉积(ALD)及/或其他合适的工艺等方法形成。
在步骤103,在所述第二栅堆叠400的侧壁形成第二侧墙缓冲层218。如图3所示,先在所述器件上沉积低k介质材料层215,然后使用RIE的方法图形化所述低k介质材料层215,形成属于NMOS区域201的第一侧墙缓冲层216和属于PMOS区域202的第二侧墙缓冲层218,如图4所示。然后将PMOS区域202掩膜,使用干法或湿法刻蚀去除NMOS区域201的第一侧墙缓冲层216,在将PMOS区域202上的掩膜,从而形成第二栅堆叠400的第二侧墙缓冲层218,如图5所示。其中所述第二侧墙缓冲层218的厚度为大约1至100纳米,所述第二侧墙缓冲层218采用低k介质材料形成,可以是SiCOH、SiO或SiCO等。所述低k介质材料的相对介电常数小于3.5,由低k材料形成的所述第二侧墙缓冲层具有疏松的结构,因此可以成为之后氧原子扩散的通道,且由于缓冲层具有疏松的结构,较易去除,所以在去除过程中对栅极及衬底的损伤较小。所述低k材料的沉积可以使用例如化学气相沉积(CVD)、物理气相沉积(PVD)、原子层沉积(ALD)及/或其他合适的工艺等方法形成。
在步骤105,在所述第一栅堆叠300的侧壁形成第一侧墙228,在所述第二侧墙缓冲层218的侧壁形成第二侧墙230,以及在所述半导体衬底200中分别形成属于NMOS区域201的源/漏延伸区和/或halo区220以及源极区和漏极区222和PMOS区域202的源/漏延伸区和/或halo区224以及源极区和漏极区226,如图6所示。所述第一侧墙228和第二侧墙230可以是多层结构,可以由氮化硅、氧化硅、氮氧化硅、碳化硅、氟化物掺杂硅玻璃及其组合,和/或其他合适的材料形成。在本实施例中,第一侧墙228和第二侧墙230是两层结构,通过沉积、刻蚀依次形成第一侧墙层一228-1和第二侧墙层二为Si3N4,以及第一侧墙层二228-2和第二侧墙层二230-2为SiO2,如图6所示,这仅仅是作为示例,不局限于此。所述侧墙的沉积可以使用例如化学气相沉积(CVD)、物理气相沉积(PVD)、原子层沉积(ALD)及/或其他合适的工艺等方法形成。
源/漏延伸区和/或halo区220、224以及源/漏极区222、226可以通过根据期望的晶体管结构,注入p型或n型掺杂物或杂质到NMOS区域201和PMOS区域202的衬底200中而形成,如图6所示。源/漏极区222、226可以由包括光刻、离子注入、扩散和/或其他合适工艺的方法形成,而后对源/漏极222、226进行退火,以激活掺杂。
在通常的源/漏极区高温退火后,在步骤106,对所述器件在氧气环境进行退火,以使氧气环境中的氧气通过所述第二侧墙缓冲层218扩散到所述第二栅堆叠400的高k栅介质层206中。所述退火温度为大约300℃至800℃,所述退火时间为大约1至3000秒,所述退火保护气体为O2,由于所述第二侧墙缓冲层218由疏松结构的低k介质材料形成,氧原子可以沿着所述第二侧墙缓冲层218的通道,如图6箭头所示方向,扩散至第二高k栅介质层206中,以补充由于工艺集成过程中引起的高k栅介质材料的氧空位,进而达到降低PMOS阈值电压的作用。
上面对在PMOS区域202上形成第二侧墙缓冲层218,并在NMOS区域和PMOS侧墙形成后进行退火补充氧空位的方法和器件进行了描述。根据本发明第一实施例的方法,只在PMOS区域202的第二栅堆叠400侧壁形成第二侧壁缓冲层218,NMOS区域201的第一栅堆叠300的侧壁直接由第一侧墙228覆盖,而且第二侧墙缓冲层218为疏松的低k材料,如SiCOH、SiO、SiCO等。第一侧墙228为相对致密的材料,如Si3N4,这样在氧环境高温退火后,氧原子沿着第二侧壁缓冲层218扩散至第二高k介质层进而降低其PMOS器件的阈值电压,而受Si3N4第一侧墙228的保护,氧原子不会扩散至NMOS器件,NMOS器件的阈值电压将不受影响,此外,高温退火工艺在NMOS和PMOS有侧墙结构后进行,保护了器件的栅极及衬底不受破坏,有效控制PMOS器件的阈值电压以及提高了器件的整体性能。
第二实施例
下面将仅就第二实施例区别于第一实施例的方面进行阐述。未描述的部分应当认为与第一实施例采用了相同的步骤、方法或者工艺来进行,因此在此不再赘述。
参考图7,图7示出了根据本发明的第二实施例的制造半导体器件的方法的流程图,根据本发明的第二实施例的步骤101至步骤104,同第一实施例中的步骤101至步骤104相同,视为与第一实施例采用了相同的步骤、方法或者工艺来进行,在此不再赘述。
在步骤105,去除属于所述PMOS区域202的第二侧墙230。将NMOS区域201掩膜,使用干法或湿法刻蚀去除PMOS区域202的第二侧墙230,如图8所示。
在步骤106,对所述器件在氧气环境进行退火,以使氧气环境中的氧气通过所述第二侧墙缓冲层218扩散到所述第二栅堆叠400的高k栅介质层206中。所述退火温度为大约300℃至800℃,所述退火时间为大约1至3000秒,所述退火保护气体为O2,由于所述第二侧墙缓冲层218由疏松结构的低k介质材料形成,氧原子可以沿着所述第二侧墙缓冲层218的通道的竖直及侧壁方向,如图8箭头所示方向,扩散至第二高k栅介质层206中,以补充由于工艺集成过程中引起的高k栅介质材料的氧空位,进而达到降低PMOS阈值电压的作用,同本发明所述实施例一相比,所述实施例二有更多的方向沿第二侧墙缓冲层218的扩散通道实现氧扩散,具有更好的扩散效果。
本发明对在PMOS区域202上形成第二侧墙缓冲层218,并在NMOS区域侧墙形成后进行退火补充氧空位的方法和器件进行了描述。根据本发明的方法,只在PMOS区域202的第二栅堆叠400侧壁形成第二侧壁缓冲层218,NMOS区域201的第一栅堆叠300的侧壁直接由第一侧墙228覆盖,而且第二侧壁缓冲层218为疏松的低k材料,如SiCOH、SiO、SiCO。第一侧墙228为相对致密的材料,如Si3N4,这样在氧环境高温退火后,氧原子沿着第二侧壁缓冲层218扩散至第二高k介质层进而降低其PMOS器件的阈值电压,而受Si3N4第一侧墙228的保护,氧原子不会扩散至NMOS器件,NMOS器件的阈值电压将不受影响,有效控制PMOS器件的阈值电压以及提高了器件的整体性能。
虽然关于示例实施例及其优点已经详细说明,应当理解在不脱离本发明的精神和所附权利要求限定的保护范围的情况下,可以对这些实施例进行各种变化、替换和修改。对于其他例子,本领域的普通技术人员应当容易理解在保持本发明保护范围内的同时,工艺步骤的次序可以变化。
此外,本发明的应用范围不局限于说明书中描述的特定实施例的工艺、机构、制造、物质组成、手段、方法及步骤。从本发明的公开内容,作为本领域的普通技术人员将容易地理解,对于目前已存在或者以后即将开发出的工艺、机构、制造、物质组成、手段、方法或步骤,其中它们执行与本发明描述的对应实施例大体相同的功能或者获得大体相同的结果,依照本发明可以对它们进行应用。因此,本发明所附权利要求旨在将这些工艺、机构、制造、物质组成、手段、方法或步骤包含在其保护范围内。
Claims (6)
1.一种制造半导体器件的方法,所述方法包括:
提供具有NMOS区域和PMOS区域的半导体衬底,其中所述NMOS区域与所述PMOS区域相互隔离;
在所述NMOS区域的半导体衬底上形成第一栅堆叠,在所述PMOS区域的半导体衬底上形成第二栅堆叠,其中所述第一栅堆叠的形成包括形成第一高k栅介质层和其上的第一金属栅电极,所述第二栅堆叠的形成包括形成第二高k栅介质层和其上的第二金属栅电极;
仅在所述第二栅堆叠的侧壁形成第二侧墙缓冲层,其中所述第二侧墙缓冲层采用低k介质材料形成;
在所述第一栅堆叠的侧壁形成第一侧墙,在所述第二侧墙缓冲层的侧壁形成第二侧墙;
在所述半导体衬底中分别形成属于NMOS区域和PMOS区域的源/漏延伸区和/或halo区以及源极区和漏极区;
去除所述第二侧墙;
对所述器件在氧气环境进行退火,以使氧气环境中的氧气通过所述第二侧墙缓冲层扩散到所述第二栅堆叠的第二高k栅介质层中。
2.根据权利要求1所述的方法,其中所述低k介质材料的相对介电常数小于3.5。
3.根据权利要求1所述的方法,其中形成所述第二侧墙缓冲层的低k介质材料包括:SiCOH、SiO或SiCO。
4.根据权利要求1所述的方法,其中所述第二侧墙缓冲层的厚度为1至100纳米。
5.根据权利要求1所述的方法,其中所述退火温度为300℃至800℃。
6.根据权利要求1所述的方法,其中所述退火时间为1至3000秒。
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