JP2010525590A - 高kゲート誘電体cmosのための閾値調整 - Google Patents
高kゲート誘電体cmosのための閾値調整 Download PDFInfo
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- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 51
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- 125000006850 spacer group Chemical group 0.000 description 16
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 239000002210 silicon-based material Substances 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 3
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- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 description 1
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Abstract
【解決手段】 第1の型のFETが極めて薄い酸化物ライナを有する、CMOS構造体が開示される。この薄いライナは、酸素が第1の型のFETの高k誘電体のゲート絶縁体に達するのを防ぐことができる。CMOS構造体の第2の型のFETデバイスは、より厚い酸化物ライナを有する。その結果、酸素曝露により、第1の型のFETの閾値に影響を及ぼすことなく、第2の型のFETの閾値電圧をシフトさせることができる。この開示はまた、異なる型のFETデバイスが異なる厚さのライナを有し、異なる型のFETデバイスの閾値が互いに独立して設定される、CMOS構造体を製造する方法も教示する。
【選択図】 図1
Description
11:第2のゲート絶縁体
20:一時的ライナ
21:第2のライナ
22:第1のライナ
30、60:側壁スペーサ
40:ソース/ドレイン延長部
41:シリサイド化されたソース及びドレイン
42:シリサイド
50:デバイス本体
55、56:ゲート
55´、56´:金属層
55´´:キャップ層
99:浅いトレンチ
100:CMOS構造体
101:酸素曝露
150:ブロッキング・マスク
900:プロセッサ
901:チップ
Claims (20)
- 第1の高k誘電体を含む第1のゲート絶縁体と、
酸化物からなり、0.2nmから1.2nmまでの間の第1の厚さを有する第1のライナと、
を含む少なくとも1つの第1の型のFETデバイスと、
第2の高k誘電体を含む第2のゲート絶縁体と、
酸化物からなり、前記第1の厚さより少なくとも3倍厚い第2の厚さを有する第2のライナと、
を含む少なくとも1つの第2の型のFETデバイスと、
を備え、
前記第2の厚さは、酸素が前記第2のライナを通過し、前記第2のゲート絶縁体に達することができるように十分に厚いものであり、前記第1の厚さは、酸素が前記第1のライナを通過して前記第1のゲート絶縁体に達するのを実質的にブロックすることができ、前記第2の型のFETの前記閾値を実質的に変わらないままにしながら、酸素曝露により前記第1の型のFETの閾値をシフトさせることが可能になる、CMOS構造体。 - 前記第1の型のFETデバイはPFETデバイスであり、前記第2の型のFETデバイスはNFETデバイスである、請求項1に記載のCMOS構造体。
- 前記第1の型のFETデバイスはNFETデバイスであり、前記第2の型のFETデバイスはPFETデバイスである、請求項1に記載のCMOS構造体。
- 前記第1の高k誘電体及び前記第2の高k誘電体は同じ材料のものである、請求項1に記載のCMOS構造体。
- 前記同じ材料はHfO2である、請求項1に記載のCMOS構造体。
- 前記第1の型のFETデバイスは第1のゲートを含み、前記第1のゲートは第1の金属を含む、請求項1に記載のCMOS構造体。
- 前記第1の金属は前記第1のゲート絶縁体と直接接触している、請求項6に記載のCMOS構造体。
- キャップ層が、前記第1の金属と前記第1のゲート絶縁体との間に挟まれている、請求項6に記載のCMOS構造体。
- 前記第2の型のFETデバイスは第2のゲートを含み、前記第2のゲートは第2の金属を含み、前記第2の金属は前記第2のゲート絶縁体と直接接触している、請求項1に記載のCMOS構造体。
- CMOS構造体を処理する方法であって、
第1の型のFETデバイスにおいて、第1の高k誘電体を含む第1のゲート絶縁体を実装し、一時的ライナを製造することと、
前記第1の型のFETデバイスにおいて、エッチングによって前記一時的ライナを完全に除去することと、
前記第1の型のFETデバイスにおいて、前記一時的ライナの代わりに、0.2nmから1.2nmまでの間の第1の厚さを有する化学酸化物ライナを堆積させることと、
第2の型のFETデバイスにおいて、第2の高k誘電体を含む第2のゲート絶縁体を実装し、本質的に酸化物からなり、前記第1の厚さより少なくとも3倍厚くなるように選択された第2の厚さを有する第2のライナを製造することと、
前記第1の型のFETデバイス及び前記第2の型のFETデバイスを酸素に曝露することであって、酸素は前記第2のライナを通って前記第2のゲート絶縁体の前記第2の高k誘電体に達する、前記曝露することと、前記第2の型のFETデバイスの閾値電圧の所定のシフトを引き起こすことであって、前記第1の厚さのために、酸素は前記第1のゲート絶縁体の前記第1の高k誘電体に通ることが本質的に防止され、前記第1の型のFETデバイスの閾値電圧は変わらないままである、前記引き起こすことと、
を含む方法。 - 前記第1の型のFETデバイスは、PFETデバイスとなるように選択され、前記第2の型のFETは、NFETデバイスとなるように選択される、請求項10に記載の方法。
- 前記第1の型のFETデバイスは、NFETデバイスとなるように選択され、前記第2の型のFETデバイスは、PFETデバイスとなるように選択される、請求項10に記載の方法。
- 前記第1の高k誘電体及び前記第2の高k誘電体は、同じ材料のものになるように選択される、請求項10に記載の方法。
- 前記同じ材料は、HfO2であるように選択される、請求項13に記載の方法。
- 前記第1の型のFETデバイス及び前記第2の型のFETデバイスの上に単一の酸化物層を堆積させ、前記単一の酸化物層から前記一時的ライナ及び前記第2のライナを製造することをさらに含む、請求項10に記載の方法。
- 前記第1の型のFETデバイスにおいて、第1の金属を含む第1のゲートを実装することと、
前記第2の型のFETデバイスにおいて、第2の金属を含む第2のゲートを実装することと、
をさらに含む、請求項10に記載の方法。 - 前記第1のゲートについて、前記第1のゲート絶縁体と前記第1の金属との間に挟まれるようにキャップ層を処理することをさらに含む、請求項16に記載の方法。
- 前記第2のゲートについて、前記第2の絶縁体と直接接触するように前記第2の金属を処理することをさらに含む、請求項16に記載の方法。
- 少なくとも1つのCMOS回路を備え、前記CMOSは、
第1の高k誘電体を含む第1のゲート絶縁体と、0.2nmから1.2nmまでの間の厚さを有する酸化物からなる第1のライナと、を有する少なくとも1つの第1の型のFETデバイスと、
第2の高k誘電体を含む第2のゲート絶縁体と、酸化物からなり前記第1のライナより少なくとも3倍厚い第2のライナと、を有する少なくとも1つの第2の型のFETデバイスと、
をさらに含むプロセッサ。 - 前記プロセッサは、複数の前記第2の型のFETデバイスを有し、前記複数の第2の型のFETデバイスの閾値は、少なくとも2つの異なる値を有し、前記異なる値は、少なくとも50mVだけ分離される、請求項19に記載のプロセッサ。
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US11/743,101 | 2007-05-01 | ||
US11/743,101 US20080272437A1 (en) | 2007-05-01 | 2007-05-01 | Threshold Adjustment for High-K Gate Dielectric CMOS |
PCT/EP2008/054218 WO2008132026A1 (en) | 2007-05-01 | 2008-04-08 | Threshold adjustment for high-k gate dielectric cmos |
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EP (1) | EP2165359B1 (ja) |
JP (1) | JP4917171B2 (ja) |
KR (1) | KR20090130845A (ja) |
CN (1) | CN101675513B (ja) |
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JP2009277816A (ja) * | 2008-05-14 | 2009-11-26 | Nec Corp | 半導体装置及びその製造方法 |
JP2011009555A (ja) * | 2009-06-26 | 2011-01-13 | Toshiba Corp | 半導体装置およびその製造方法 |
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TW200845384A (en) | 2008-11-16 |
EP2165359A1 (en) | 2010-03-24 |
US20080272437A1 (en) | 2008-11-06 |
EP2165359B1 (en) | 2012-06-27 |
KR20090130845A (ko) | 2009-12-24 |
JP4917171B2 (ja) | 2012-04-18 |
CN101675513A (zh) | 2010-03-17 |
CN101675513B (zh) | 2011-07-13 |
WO2008132026A1 (en) | 2008-11-06 |
US20090291553A1 (en) | 2009-11-26 |
US8187961B2 (en) | 2012-05-29 |
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