WO2011153843A1 - 一种先栅工艺中叠层金属栅结构的制备方法 - Google Patents

一种先栅工艺中叠层金属栅结构的制备方法 Download PDF

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WO2011153843A1
WO2011153843A1 PCT/CN2011/071055 CN2011071055W WO2011153843A1 WO 2011153843 A1 WO2011153843 A1 WO 2011153843A1 CN 2011071055 W CN2011071055 W CN 2011071055W WO 2011153843 A1 WO2011153843 A1 WO 2011153843A1
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gate
metal gate
etching
hard mask
depositing
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French (fr)
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徐秋霞
李永亮
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中国科学院微电子研究所
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Priority to US13/129,584 priority Critical patent/US8598002B2/en
Publication of WO2011153843A1 publication Critical patent/WO2011153843A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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    • H01L21/02057—Cleaning during device manufacture
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H01L21/31122—Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes

Definitions

  • the invention relates to a method for preparing a stacked metal gate structure by a gate-first process, in particular to a method for preparing a TiN metal gate stacked structure with a barrier layer of A1N or TaN in a gate-first process, which is suitable for 32/22 nm and
  • CMOS nano-complementary metal oxide semiconductor
  • CMOS devices As the feature size of CMOS devices continues to shrink, the application of high dielectric constant (K) gate dielectrics and metal gate electrodes is imperative. With high-k dielectrics, the gate tunneling leakage current can be greatly reduced due to its thicker physical thickness at the same equivalent oxide thickness (EOT).
  • EOT equivalent oxide thickness
  • the conventional polysilicon gate is not compatible with the high ⁇ gate dielectric, and there is a serious Fermi pinning effect, so a new metal gate electrode must be used instead.
  • the metal gate not only eliminates the depletion effect of the polysilicon gate, reduces the gate F3 ⁇ 4 resistance, but also eliminates boron penetration and improves device reliability.
  • the object of the present invention is to provide a method for preparing a stacked metal gate structure in a gate-first process, in which a layer of thermally stable A1N or TaN metal nitride is added as a barrier layer between a TiN metal gate and a polysilicon layer. Thermal stability.
  • the high-density plasma etching of BCl 3 /Cl 2 /0 2 /Ar mixed gas under low pressure and reverse bias conditions is used to solve the etching difficulty of the TiN metal gate laminated structure with A1N or TaN as the barrier layer.
  • a steep continuous etch profile also has a high etch selectivity ratio for Si substrates, which eliminates the metal gate/high K integration technology. Obstacles.
  • the present invention provides a method for preparing a stacked metal gate structure in a gate-first process, and the main steps are as follows:
  • Step 1) After completing the conventional L0C0S or STI isolation, the interfacial layer SiOx or SiON is formed by rapid thermal annealing at 600 800"C for 20 120 seconds or by chemical treatment with 0 :i treatment;
  • Step 2 depositing a high dielectric constant K gate dielectric film
  • Step 3) depositing a high dielectric constant K gate dielectric film and then annealing at 600-1050"C for 4-120 seconds; step 4) forming a metal gate electrode: using a physical vapor deposition TiN gate;
  • Step 5 depositing an A1N or TaN barrier layer by physical vapor deposition
  • Step 6) depositing a polysilicon film and a hard mask by a low pressure chemical vapor phase, and then performing photolithography and hard mask etching; Step 7) After etching, masking the polysilicon film/A1N with a hard mask as a mask
  • the TaN barrier layer/TiN metal gate/high dielectric constant K gate dielectric film forms a metal gate stacked structure.
  • the conventional method is first cleaned before the step 1, and then immersed in a hydrofluoric acid/isopropanol/water mixed solution at room temperature, rinsed with deionized water, and dried immediately after being dried; hydrofluoric acid: Isopropyl alcohol: water weight ratio is 0. 2-1. 5%: 0. 01-0. 10%: 1%; soaking time is 2 10 minutes.
  • the interfacial layer formation in step 1 is formed by first injecting nitrogen and then rapidly annealing, or rapidly forming a SiOx by rapid thermal annealing, and then nitriding to form SiON; SiOx may also be formed by chemical treatment of 0 3 , and then plasma nitrogen Chemical.
  • the high dielectric constant K gate dielectric film in step 2 is Hf0 2 , HfA10, HfA10N, HfSiO, HfSi0N, HfLaO or HfLaON, and the high dielectric constant K gate dielectric film is deposited by physical vapor deposition, metal organic Formed by chemical vapor deposition or atomic layer deposition processes.
  • the TiN metal gate described in step 4 has a thickness of 5-100 nm.
  • the thickness of the A1N or TaN barrier layer in step 5 is 2-12 nm.
  • the hard mask of step 6 is SiO 2 , Si, or a stack thereof, 0/N or 0/N/0; and the hard mask is etched using an F-based plasma.
  • step 7 uses a F-based plus C1-based or HBr-plus-C1-based plasma etch on the polysilicon to perform plasma on the A1N or TaN barrier metal layer, the TiN metal gate, and the high dielectric constant K-gate dielectric film.
  • etching 8 ( 13 and Cl 2 are used as the main etching gas, and one of 0 2 and Ar or two of them are added as an auxiliary etching gas to improve etching characteristics.
  • step 7 mainly etching gas BCl : i and Cl 2 , the volume ratio of Cl 2 to BCl : i is 0 1 : 4; The volume ratio of the added gas 0 2 to BCl :i is 0 1 : 8, and the volume ratio of the added gas Ar to BC1: is 1:5 to 1:2.
  • the etching conditions of the A1N or TaN barrier layer/TiN metal gate/high dielectric constant K gate dielectric film in step 7 are: the upper electrode power is 140-450 W, and the lower electrode power is 50 150 W.
  • the pressure is 4-15 mt, the total flow rate of the BC13-based etching gas is 60-150 sc Cm , and the temperature of the cavity and the electrode is controlled at 60-200 degrees.
  • the method for preparing a TiN metal gate stack structure using A1N or TaN as a barrier layer in the gate-first process proposed by the present invention does not increase the etching process by adding an A1N or TaN barrier layer to the TiN metal gate. Complexity, etching of the barrier layer and the TiN metal gate is completed by one-step etching;
  • the method for preparing a TiN metal gate stack structure using A1N or TaN as a barrier layer in the gate-first process proposed by the present invention can not only obtain a steep etch profile, but also has a small loss to the Si substrate, which satisfies The requirements of the etching process after the introduction of high K and metal gate materials in the integrated process.
  • the method for preparing a TiN metal gate stack structure using A1N or TaN as a barrier layer in the first gate process provided by the present invention is suitable for integration of a high dielectric constant medium eight metal gate in a nano CMOS device, in order to achieve high
  • the integration of the K/metal grid removes the barrier.
  • Figure 1 (a) is a scanning electron micrograph with a SiO 2 hard mask / polysilicon / A1N barrier layer / TiN metal gate / high K dielectric / interface SI0 2 laminated structure.
  • Figure 1 (b) shows the structure without the A1N barrier layer.
  • Figure 2 is a high-density plasma etching of a mixed gas of BCl 3 /Cl 2 /0 2 /Ar under low pressure and reverse bias conditions to obtain a Si0 2 hard mask/polysilicon/A1N or TaN barrier layer/TiN metal gate/ High K dielectric/interface SI0 2 laminate structure with a steep continuous etch profile.
  • the invention provides a new method for integrating a high K/metal gate in the preparation of a nano CMOS device, and provides a method for preparing a TiN laminated metal gate structure with a barrier layer of A1N and TaN in a gate-first process.
  • Step 1) Cleaning After the device is formed, the cleaning before the formation of the interface oxide layer is performed.
  • the method is cleaned, then immersed in a hydrofluoric acid/isopropanol/water mixed solution at room temperature, rinsed with deionized water, and dried immediately after feeding into the furnace;
  • hydrofluoric acid: isopropanol: water weight ratio is 0.2 1.5%: 0.01- 0.10% : 1%;
  • Step 2) Interfacial layer Formation of SiOx or SiON: formed at 600-800"C, 20 120 seconds rapid thermal annealing; or chemically treated with 03;
  • High K dielectric film can be Hf, HfA10,
  • the high-k gate dielectric layer is formed by physical vapor deposition, metal organic chemical vapor deposition or atomic layer deposition process;
  • Step 4) Rapid thermal annealing after deposition of high-k dielectric thermal annealing at 600-1050C for 4-120 seconds;
  • Step 6 using a physical vapor deposition A1N or TaN barrier layer, the thickness is 5-12;
  • Step 7) depositing a polysilicon film and a hard mask by a low pressure chemical vapor phase, and then performing etching and hard mask etching, the hard mask may be Si0 2 (0), or Si 3 , (N), or a stack thereof Layer: 0/N or 0/N/0; hard mask etching
  • Step 8) After the glue is removed, the polysilicon film/barrier metal layer/metal gate/high K dielectric is sequentially etched by using a hard mask as a mask to form a metal gate stacked structure.
  • a hard mask as a mask to form a metal gate stacked structure.
  • polycrystalline silicon is coated with F-based C1 or HBr plus C1-based plasma.
  • BC1 3 and Cl 2 are used as the main method for high-density plasma etching of A1N or TaN barrier layers, TiN metal gates and high-k dielectrics. Etching the gas, adding one or both of 0 2 and Ar as an auxiliary etching gas to improve the etching characteristics.
  • Step 1) Cleaning After the device is isolated, the cleaning before the formation of the interface oxide layer is performed by conventional methods, and then immersed in a hydrofluoric acid/isopropyl alcohol/water mixed solution for 5 minutes at room temperature. Rinse with water, immediately after drying, into the furnace; concentration ratio of hydrofluoric acid / isopropanol / water is 0.2-1.5%: 0.01 0.10%: 1%;
  • Step 2) Interfacial layer Formation of SiOx or SiON: Formed by rapid thermal annealing at 600-800"C for 30-120 seconds;
  • Step 4) Rapid thermal annealing after deposition of high-k dielectric: thermal annealing at 600-1050C for 4-60 seconds;
  • Step 5) Formation of metal gate electrode: deposition of TiN gate by magnetron reactive sputtering, thickness 10 -50 n m ;
  • Step 6) depositing an A1N or TaN barrier layer by magnetron reactive sputtering with a thickness of 5-12 nm ;
  • Step 7) depositing a polysilicon film and a hard mask by a low pressure chemical vapor phase, and then performing photolithography and hard mask etching,
  • the hard mask is Si (3 ⁇ 4, the hard mask is etched using an F-based plasma;
  • Step 8) After the glue is removed, the polysilicon film/barrier metal layer/metal gate/high K dielectric is sequentially etched to form a metal gate stacked structure with a hard mask as a mask.
  • the polysilicon is etched by HBr plus C1, and the high-density plasma etching of the A1N or TaN barrier layer, the TiN metal gate and the high-k dielectric is performed by using BCl :i and Cl 2 as the main etching gas. 3 ⁇ 4, Ar is used as an auxiliary etching gas to improve the etching characteristics.
  • FIG. 1( a ) The SiO 2 hard mask/polysilicon/A1N barrier layer/TiN metal gate/high K dielectric/interface SI0 2 laminate structure prepared in this embodiment is shown in FIG. 1( a ).
  • the structure without the A1N barrier layer is shown in Figure 1 (b). Comparing Fig. 1(a) with Fig. 1(b), it can be clearly seen that Fig. 1(b) has a significant interfacial reaction at the polysilicon/TiN interface, while Fig. 1(a) acts on the A1N barrier layer, The interface reaction occurs and the interface is relatively flat.
  • Figure 2 shows the high-density plasma etching of BCl :i /Cl 2 / /Ar mixed gas under low pressure and reverse bias conditions to obtain Si0 2 hard mask / polysilicon / A1N or TaN barrier layer / TiN metal gate / high K
  • the dielectric/interface Si0 2 stack structure has a steep continuous etch profile, and no loss of Si is seen, indicating a high etch selectivity ratio for the Si substrate.

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Description

一种先栅工艺中叠层金属栅结构的制备方法 技术领域
本发明涉及先栅工艺屮一种叠层金属栅结构的制备方法，尤其涉及先栅工艺中以 A1N或 TaN为势垒层的 TiN金属栅叠层结构的制备方法， 适合于 32/22纳米及以下技 术代高性能纳米互补型金属氧化物半导体 （CMOS ) 器件的应用。 背景技术
随着 CMOS器件特征尺寸的不断缩小， 高介电常数（K)栅介质和金属栅电极的应 用势在必行。 采用高 K介质， 由于其在同样等效氧化物厚度 （EOT) 下有较厚的物理 厚度，所以可以大幅度降低栅隧穿漏电流。但是传统的多晶硅栅与高 κ栅介质不兼容， 存在严重的费米钉扎效应， 所以必须采用新型金属栅电极代替之。 金属栅不仅能消除 多晶硅栅的耗尽效应， 减小栅 F¾阻， 还能消除硼穿透， 提高器件可靠性。 但是金属栅 集成到高 κ栅介质上仍有许多问题急待解决， 如热稳定性问题， 界面态问题， 特别是 费米钉扎效应使纳米 CMOS器件需要的适当低的阈值电压的获得面临很大挑战， 尤其 是 PM0S器件。
为了得到合适的阈值， N管和 P管的功函数分别应在 Si的导带底附近（4. leV左 右）和价带顶附近（5. 2eV左右）。 TiN金属栅由于具有低的电阻率和优良的热和化学 稳定性， 而成为金属栅材料的有力候选者。 在集成技术中为了降低刻蚀的难度， 不过 多地增加原有 CMOS工艺的复杂性， 一般釆用插入式金属栅的叠层结构（即多晶硅 /金 属栅的叠层结构） 代替纯金属栅电极来实现高 K、 金属栅材料的集成。 但由于直接在 TiN金属栅上淀积多晶硅层时的高温工艺会导致 TiN金属栅与多晶硅层发生反应， 成 为实现金属栅 /高 K集成技术的障碍。 发明内容
本发明的目的在于提供一种先栅工艺中叠层金属栅结构的制备方法，在 TiN金属 栅与多晶硅层间加入了一层热稳定性很高的 A1N或 TaN金属氮化物作为势垒层提高了 热稳定性。 同时釆用低压和反偏条件下 BCl3/Cl2/02/Ar混合气体高密度等离子刻蚀， 解决了以 A1N或 TaN为势垒层的 TiN金属栅叠层结构的刻蚀难度，获得了陡直的连续 的刻蚀剖面， 对 Si衬底也有高的刻蚀选择比， 这为实现金属栅 /高 K集成技术清除了 障碍。
为实现上述目的， 本发明提供的先栅工艺中叠层金属栅结构的制备方法， 主要歩 骤如下：
歩骤 1 ) 在完成常规的 L0C0S或 STI隔离后， 于 600 800"C下， 20 120秒快速热 退火形成或用 0:i处理的化学方法形成界面层 SiOx或 SiON;
歩骤 2 ) 淀积形成高介电常数 K栅介质薄膜；
歩骤 3 )淀积形成高介电常数 K栅介质薄膜后于 600-1050"C下， 4-120秒热退火； 歩骤 4) 金属栅电极形成： 采用物理汽相淀积 TiN栅；
步骤 5 ) 利用物理汽相淀积 A1N或 TaN势垒层；
步骤 6) 低压化学汽相淀积多晶硅膜和硬掩模， 然后进行光刻和硬掩膜的刻蚀； 步骤 7 ) 刻蚀后， 以硬掩膜为掩蔽， 依次刻蚀多晶硅膜 /A1N或 TaN势垒层 /TiN 金属栅 /高介电常数 K栅介质薄膜形成金属栅叠层结构。
所述的方法中， 歩骤 1之前先进行常规方法清洗， 然后用氢氟酸 /异丙醇 /水混合 溶液在室温下浸泡， 去离子水冲洗， 甩干后立即进炉； 氢氟酸：异丙醇:水的重量比为 0. 2-1. 5% : 0. 01-0. 10%： 1%； 浸泡时间为 2 10分钟。
所述的方法中， 步骤 1中界面层形成是釆用先注入氮再快速热退火形成， 或先快 速热退火形成 SiOx, 再氮化形成 SiON; SiOx也可用 03化学处理形成， 然后等离子氮 化。
所述的方法中，步骤 2中高介电常数 K栅介质薄膜是 Hf02、HfA10、HfA10N、HfSiO、 HfSi0N、 HfLaO或 HfLaON, 所述高介电常数 K栅介质薄膜通过物理气相淀积、 金属有 机化学气相沉积或原子层淀积工艺形成。
所述的方法中， 步骤 4所述的 TiN金属栅厚度为 5- 100nm。
所述的方法中， 歩骤 5所述 A1N或 TaN势垒层厚度为 2-12纳米。
所述的方法中， 步骤 6所述硬掩模为 Si02、 Si 、 或其叠层 0/N或 0/N/0; 硬掩 模的刻蚀采用 F基等离子体。
所述的方法中， 步骤 7对多晶硅采用 F基加 C1基或 HBr加 C1基等离子体刻蚀， 对 A1N或 TaN势垒金属层、 TiN金属栅和高介电常数 K栅介质薄膜进行等离子体刻蚀 时采用 8( 13和 Cl2作为主要刻蚀气体， 添加 02和 Ar中的一种或其两种气体作为辅助 刻蚀气体， 以改善刻蚀特性。
所述的方法中，步骤 7主要刻蚀气体 BCl:i和 Cl2中， Cl2与 BCl:i的体积比为 0 1 : 4; 添加气体 02与 BCl:i的体积比为 0 1 : 8， 添加气体 Ar与 BC1:,的体积比为 1 : 5到 1 : 2。 所述的方法中， 歩骤 7中对 A1N或 TaN势垒层 /TiN金属栅 /高介电常数 K栅介质 薄膜的刻蚀条件为：上电极功率为 140-450W,下电极功率为 50 150W,压强为 4- 15mt , BC13基刻蚀气体的总流量为 60-150scCm， 腔体和电极的温度控制在 60-200度。
本发明具有以下三个优点：
1 ) 本发明提出的先栅工艺中以 A1N或 TaN为势垒层的 TiN金属栅叠层结构的制 备方法，没有因为在 TiN金属栅上增加了 A1N或 TaN势垒层而增加刻蚀工艺的复杂性， 势垒层与 TiN金属栅的刻蚀通过一步刻蚀完成；
2 ) 本发明提出的先栅工艺中以 A1N或 TaN为势垒层的 TiN金属栅叠层结构的制 备方法， 不仅可以得到陡直的刻蚀剖面， 而且对 Si衬底的损耗很小， 满足集成工艺 中引入高 K、 金属栅材料后对刻蚀工艺的要求。
3 ) 本发明提出的先栅工艺中以 A1N或 TaN为势垒层的 TiN金属栅叠层结构的制 备方法， 与现有的 CMOS工艺完全兼容。
因此，本发明所提供的先栅工艺中以 A1N或 TaN为势垒层的 TiN金属栅叠层结构 的制备方法，适于纳米 CMOS器件中高介电常数介质八金属栅的集成需要， 为实现高 K/ 金属栅的集成清除了障碍。 附图说明
图 1(a)为具有 Si02硬掩膜 /多晶硅 /A1N势垒层 /TiN金属栅 /高 K介质 /界面 SI02 叠层结构的扫描电镜照片。
图 1 ( b ) 为无 A1N势垒层的结构。
图 2是釆用低压和反偏条件下 BCl3/Cl2/02/Ar混合气体高密度等离子刻蚀， 获得 了 Si02硬掩膜 /多晶硅 /A1N或 TaN势垒层 /TiN金属栅 /高 K介质 /界面 SI02叠层结构陡 直的连续的刻蚀剖面。 具体实施方式
本发明为在纳米 CMOS器件制备中集成高 K/金属栅新技术， 提供一种先栅工艺中 以 A1N和 TaN为势垒层的 TiN叠层金属栅结构的制备方法。
本发明的主要步骤如下： 歩骤 1 ) 清洗： 在器件隔离形成后， 进行界面氧化层形成前的清洗， 先采用常规 方法清洗， 然后用氢氟酸 /异丙醇 /水混合溶液在室温下浸泡， 去离子水冲洗， 甩干后 立即进炉； 氢氟酸：异丙醇：水的重量比为 0.2 1.5% :0.01- 0.10% :1%；
步骤 2) 界面层 SiOx或 SiON的形成： 于 600- 800"C下， 20 120秒快速热退火形 成； 或用 03处理的化学方法形成；
歩骤 3) 高介电常数 （K) 栅介质薄膜的形成： 高 K介质膜可以是 Hf 、 HfA10、
HfA10N、 HfSiO、 HfSiON、 HfLaO或 HfLaON等， 所述高 K栅介质层通过物理气相淀积、 金属有机化学气相沉积或原子层淀积工艺形成；
歩骤 4) 淀积高 K介质后快速热退火： 于 600- 1050C下, 4- 120秒热退火； 歩骤 5) 金属栅电极形成： 采用物理汽相淀积 TiN栅， 厚度为 5- lOOnm;
步骤 6 ) 采用物理汽相淀积 A1N或 TaN势垒层， 厚度为 5- 12 ；
步骤 7) 低压化学汽相淀积多晶硅膜和硬掩模， 然后进行光刻和硬掩膜的刻蚀， 硬掩模可以是 Si02 (0)， 或 Si3 , (N), 或其叠层： 0/N或 0/N/0; 硬掩模的刻蚀采用
F基等离子体；
歩骤 8)去胶后， 以硬掩膜为掩蔽， 依次刻蚀多晶硅膜 /势垒金属层 /金属栅 /高 K 介质形成金属栅叠层结构。其中对多晶硅采用 F基加 C1基或 HBr加 C1基等离子体刻 蚀，对 A1N或 TaN势垒层、 TiN金属栅和高 K介质进行高密度等离子体刻蚀时采用 BC13 和 Cl2作为主要刻蚀气体， 添加 02、 Ar中的一种或两种气体作为辅助刻蚀气体， 以改 善刻蚀特性。
以下结合实施例作进一步的说明。
歩骤 1) 清洗： 在器件隔离形成后， 进行界面氧化层形成前的清洗， 先釆用常规 方法清洗， 然后用氢氟酸 /异丙醇 /水混合溶液在室温下浸泡 5分钟， 去离子水冲洗， 甩干后立即进炉； 氢氟酸 /异丙醇 /水的浓度比为 0.2-1.5%:0.01 0.10%： 1%；
歩骤 2) 界面层 SiOx或 SiON的形成： 于 600- 800"C下， 30-120秒快速热退火形 成；
歩骤 3) 高介电常数 （K) 栅介质薄膜的形成。 采用 HfSi0N、 HfSiAlON, HfLaON 等， 通过物理气相淀积工艺形成；
歩骤 4) 淀积高 K介质后快速热退火： 于 600- 1050C下， 4-60秒热退火； 歩骤 5) 金属栅电极形成： 采用磁控反应溅射淀积 TiN栅， 厚度为 10-50nm; 歩骤 6) 利用磁控反应溅射淀积 A1N或 TaN势垒层， 厚度为 5- 12nm;
步骤 7) 低压化学汽相淀积多晶硅膜和硬掩模， 然后进行光刻和硬掩膜的刻蚀， 硬掩模是 Si(¾， 硬掩模的刻蚀采用 F基等离子体；
歩骤 8 ) 去胶后， 以硬掩膜为掩蔽， 依次刻蚀多晶硅膜 /势垒金属层 /金属栅 /高 K 介质形成金属栅叠层结构。 其中对多晶硅采用 HBr加 C1基等离子体刻蚀， 对 A1N或 TaN势垒层、 TiN金属栅和高 K介质进行高密度等离子体刻蚀时采用 BCl:i和 Cl2作为主 要刻蚀气体， 添加 ¾、 Ar作为辅助刻蚀气体， 以改善刻蚀特性。
本实施例制备的具有 Si02硬掩膜 /多晶硅 /A1N势垒层 /TiN金属栅 /高 K介质 /界面 SI02叠层结构如图 1 ( a)所示。 没有 A1N势垒层的结构如图 1 (b ) 所示。 将图 1 (a) 与图 1 ( b ) 比较可以明显看出， 图 1 (b ) 在多晶硅 /TiN界面存在明显的界面反应， 而图 1 ( a) ώ于 A1N势垒层的作用， 没有界面反应发生， 界面比较平整。
图 2是采用低压和反偏条件下 BCl:i/Cl2/ /Ar混合气体高密度等离子刻蚀， 获得 了 Si02硬掩膜 /多晶硅 /A1N或 TaN势垒层 /TiN金属栅 /高 K介质 /界面 Si02叠层结构陡 直的连续的刻蚀剖面， 没有看见 Si的损失， 表明对 Si衬底有高的刻蚀选择比。
以上所述仅为本发明的较佳实施例， 并不用以限制本发明， 凡在本发明的精神和 原则之内， 所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims

权 利 要 求
1、 一种先栅工艺中叠层金属栅结构的制备方法， 主要歩骤如下：
歩骤 1 ) 在完成常规的 L0C0S或 STI隔离后， 于 600 800"C下， 20-120秒快速热 退火形成或用 0:1处理的化学方法形成界面层 SiOx或 SiON;
歩骤 2 ) 淀积形成高介电常数 K栅介质薄膜；
歩骤 3 )淀积形成高介电常数 K栅介质薄膜后于 600- 1050Ϊ下， 4-120秒热退火； 歩骤 4 ) 金属栅电极形成： 采用物理汽相淀积 TiN栅；
步骤 5 ) 利用物理汽相淀积 A1N或 TaN势垒层；
步骤 6 ) 低压化学汽相淀积多晶硅膜和硬掩模， 然后进行光刻和硬掩膜的刻蚀； 歩骤 7 ) 刻蚀后， 以硬掩膜为掩蔽， 依次刻蚀多晶硅膜 /A1N或 TaN势垒层 /TiN 金属栅 /高介电常数 K栅介质薄膜形成金属栅叠层结构。
2、 根据权利要求 1所述的方法， 其中， 歩骤 1之前先进行常规方法清洗， 然后 用氢氟酸 /异丙醇 /水混合溶液在室温下浸泡， 去离子水冲洗， 甩干后立即进炉； 氢氟 酸：异丙醇：水的重量比为 0. 2-1. 5% : 0. 01-0. 10% : 1%； 浸泡时间为 2-10分钟。
3、 根据权利要求 1所述的方法， 其中， 步骤 1 中界面层形成是釆用先注入氮再 快速热退火形成， 或先快速热退火形成 SiOx, 再氮化形成 SiON; SiOx也可用 03化学 处理形成， 然后等离子氮化。
4、根据权利要求 1所述的方法，其中，步骤 2中高介电常数 K栅介质薄膜是 Hf02、 HfA10、 HfA10N、 HfSi0、 HfSi0N、 HfLaO或 HfLaON, 所述高介电常数 K栅介质薄膜通 过物理气相淀积、 金属有机化学气相沉积或原子层淀积工艺形成。
5、根据权利要求 1所述的方法，其中，步骤 4所述的 TiN金属栅厚度为 5 100nm。
6、根据权利要求 1所述的方法，其中，歩骤 5所述 A1N或 TaN势垒层厚度为 2-12 纳米。
7、 根据权利要求 1所述的方法， 其中， 歩骤 6所述硬掩模为 Si02、 Si: 或其叠 层 0/N或 0/N/0; 硬掩模的刻蚀釆用 F基等离子体。
8、 根据权利要求 1所述的方法， 其中， 步骤 7对多晶硅采用 F基加 C1基或 HBr 加 C1基等离子体刻蚀，对 A1N或 TaN势垒层、 TiN金属栅和高介电常数 K栅介质薄膜 进行等离子体刻蚀时采用 BC13和 Cl2作为主要刻蚀气体， 添加 02和 Ar中的一种或其 两种气体作为辅助刻蚀气体， 以改善刻蚀特性。
9、 根据权利要求 8所述的方法， 其中， 主要刻蚀气体 BCl;i和 Cl2中， Cl2与 BCL 的体积比为 0 1:4; 添加气体 02与 BCl:i的体积比为 0-1:8， 添加气体 Ar与 BCl:i的体 积比为 1:5到 1 :2ο
10、根据权利要求 1所述的方法， 其中， 步骤 7中对 A1N或 TaN势垒层 /TiN金属 栅 /高介电常数 K栅介质薄膜的刻蚀条件为： 上电极功率为 140 450W, 下电极功率为
50-150W, 压强为 4 15mt， BC13基刻蚀气体的总流量为 60 150SCcm， 腔体和电极的温 度控制在 60- 200度。
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Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104011868B (zh) 2011-12-19 2017-02-15 英特尔公司 Ⅲ族‑n纳米线晶体管
CN103311110B (zh) * 2012-03-12 2016-08-31 中芯国际集成电路制造(上海)有限公司 半导体结构的形成方法，晶体管的形成方法
CN103456614A (zh) * 2012-06-04 2013-12-18 中芯国际集成电路制造(上海)有限公司 一种采用高k金属栅的半导体器件的制造方法
CN103632941A (zh) * 2012-08-23 2014-03-12 中芯国际集成电路制造(上海)有限公司 一种含金属栅极的半导体器件及其制备方法
CN103794481B (zh) * 2012-10-30 2016-10-05 中芯国际集成电路制造(上海)有限公司 高k金属栅极结构及其制造方法
CN104599943B (zh) * 2013-10-31 2018-01-05 上海矽睿科技有限公司 一种氮化钽反应离子刻蚀方法
CN104810241B (zh) * 2014-01-24 2018-06-08 上海矽睿科技有限公司 一种金属层上含钽薄膜的刻蚀方法
KR102212267B1 (ko) 2014-03-19 2021-02-04 삼성전자주식회사 반도체 장치 및 그 제조 방법
CN109830440A (zh) * 2019-01-24 2019-05-31 重庆平伟实业股份有限公司 功率半导体器件及其制造方法
CN114400253A (zh) * 2022-01-19 2022-04-26 长鑫存储技术有限公司 半导体结构及制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1404113A (zh) * 2002-10-18 2003-03-19 中国科学院微电子中心 一种氮化氧化膜的制备方法
US20080188044A1 (en) * 2006-10-25 2008-08-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices with dual-metal gate structures and fabrication methods thereof
CN101533842A (zh) * 2008-03-12 2009-09-16 台湾积体电路制造股份有限公司 形成mos器件的金属栅的混合方法
CN101685780A (zh) * 2008-09-26 2010-03-31 台湾积体电路制造股份有限公司 半导体装置及制造具有金属栅极堆叠的半导体装置的方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5294571A (en) * 1992-07-22 1994-03-15 Vlsi Technology, Inc. Rapid thermal oxidation of silicon in an ozone ambient
US6271094B1 (en) * 2000-02-14 2001-08-07 International Business Machines Corporation Method of making MOSFET with high dielectric constant gate insulator and minimum overlap capacitance
US7189652B1 (en) * 2002-12-06 2007-03-13 Cypress Semiconductor Corporation Selective oxidation of gate stack
US7098141B1 (en) 2003-03-03 2006-08-29 Lam Research Corporation Use of silicon containing gas for CD and profile feature enhancements of gate and shallow trench structures
US8183161B2 (en) 2006-09-12 2012-05-22 Tokyo Electron Limited Method and system for dry etching a hafnium containing material
US8138076B2 (en) * 2008-05-12 2012-03-20 Taiwan Semiconductor Manufacturing Co., Ltd. MOSFETs having stacked metal gate electrodes and method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1404113A (zh) * 2002-10-18 2003-03-19 中国科学院微电子中心 一种氮化氧化膜的制备方法
US20080188044A1 (en) * 2006-10-25 2008-08-07 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices with dual-metal gate structures and fabrication methods thereof
CN101533842A (zh) * 2008-03-12 2009-09-16 台湾积体电路制造股份有限公司 形成mos器件的金属栅的混合方法
CN101685780A (zh) * 2008-09-26 2010-03-31 台湾积体电路制造股份有限公司 半导体装置及制造具有金属栅极堆叠的半导体装置的方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
LI YONGLIANG ET AL.: "Latest development of integration of High-k/dual metal gate in gate first process.", MICROELECTRONICS., vol. 39, no. 6, December 2009 (2009-12-01), pages 829 - 834 *

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