CN104011868B - Ⅲ族‑n纳米线晶体管 - Google Patents

Ⅲ族‑n纳米线晶体管 Download PDF

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Publication number
CN104011868B
CN104011868B CN201180075624.4A CN201180075624A CN104011868B CN 104011868 B CN104011868 B CN 104011868B CN 201180075624 A CN201180075624 A CN 201180075624A CN 104011868 B CN104011868 B CN 104011868B
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iii race
iii
race
nano wire
transistor
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CN104011868A (zh
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H·W·田
R·周
B·舒-金
G·杜威
J·卡瓦列罗斯
M·V·梅茨
N·慕克吉
R·皮拉里塞泰
M·拉多萨夫列维奇
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Google LLC
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Intel Corp
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    • H01L29/158—Structures without potential periodicity in a direction perpendicular to a major surface of the substrate, i.e. vertical direction, e.g. lateral superlattices, lateral surface superlattices [LSS]
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    • B82—NANOTECHNOLOGY
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Abstract

Ⅲ族‑N纳米线设置于衬底上。纵向长度的纳米线被限定在第一Ⅲ族‑N材料的沟道区中，源极区与沟道区的第一端电耦合，并且漏极区与沟道区的第二端电耦合。在第一Ⅲ族‑N材料上的第二Ⅲ族‑N材料用作纳米线表面上的电荷诱导层，和/或势垒层。栅极绝缘体和/或栅极导体在沟道区内完全同轴地环绕纳米线。漏极触点和源极触点可以类似地完全同轴地环绕漏极区和源极区。

Description

Ⅲ族-N纳米线晶体管
技术领域
本发明的实施例总体涉及微电子器件和制造，并且更具体地涉及Ⅲ族-N晶体管。
背景技术
在过去几十年中已经以大容量的方式实施了片上系统(SoC)。SoC解决方案提供了板级部件集成所比不上的缩放优势。尽管长时间以来将模拟电路和数字电路集成到同一衬底上来提供SoC(其提供混合的信号能力)的形式，但是用于移动计算平台(例如智能电话和平板电脑)的SoC解决方案仍然难以得到，因为这些设备通常包括利用两个或多个具有高电压、高功率和高频率的信号来操作的部件。同样，常规的移动计算平台通常利用Ⅲ-Ⅴ族化合物半导体(例如GaAs异质结双极晶体管(HBT))来在GHz载频处产生足够的功率放大，并且利用横向扩散硅MOS(LDMOS)技术来管理电压转换和功率分配(包括升压和/或降压转换的电池电压调节，等等)。随后，实现CMOS工艺的常规的硅场效应晶体管是第三种器件技术，其用于移动计算平台内的逻辑和控制功能。
在移动计算平台内使用的多个晶体管技术限制了器件作为整体的可扩展性，并且因此是更强功能、更高集成水平、更低成本和更小形状因数等的障碍。因此，尽管用于将这三种器件技术中的两种或多种器件技术集成的移动计算空间的SoC解决方案是有吸引力的，但是SoC解决方案的一个障碍是缺乏具有足够的速度(即，足够高的增益截止频率，Ft)以及足够高的击穿电压(BV)的可扩展的晶体管技术。
一种有希望的晶体管技术是基于Ⅲ族氮化物(Ⅲ-N)。然而，在缩放到小于100nm的特征尺寸(例如，栅极长度)方面该晶体管技术面临根本性困难，在小于100nm的情况下，短沟道效应变得难以控制。因此具有良好控制的短沟道效应的缩放的Ⅲ-N晶体管对实现具有足够高的击穿电压(BV)的高Ft非常重要。对于用于传送移动计算平台的产品特定电流和功率要求的SoC解决方案，需要能够处理高输入电压摆动、以及在RF频率处提供高的功率附加效率的快速切换高电压晶体管。因此经得起缩放和具有这样的性能的改进的Ⅲ-N晶体管是有优势的。
附图说明
通过示例的方式而不是限制的方式对本发明的实施例进行说明，并且结合附图参考下文的具体实施方式可以更充分地理解本发明的实施例，其中：
图1A是根据实施例的Ⅲ族-N晶体管的等距图；
图1B是图1A中所示的Ⅲ族-N晶体管的沟道区的截面图；
图1C是根据实施例的Ⅲ族-N晶体管的等距图；
图2A是根据实施例的用于Ⅲ族-N晶体管的GaN晶体取向的等距图；
图2B是采用非平面GaN体的Ⅲ族-N晶体管的沟道区的截面图，其中非平面GaN主体具有图2A中所示的晶体取向；
图2C是图2B中所示的沟道区的能带图；
图2D是根据实施例的用于Ⅲ族-N晶体管的GaN晶体取向的等距图；
图2E是采用非平面GaN主体的Ⅲ族-N晶体管的沟道区的截面图，其中非平面GaN主体具有图2D中所示的晶体取向；
图3是示出根据实施例的制造非平面高电压晶体管的方法的流程图；
图4A、4B、4C、4D和4E是根据图3中所示的方法的实施例所制造的非平面高电压晶体管的等距图；以及
图5是根据本发明实施例的移动计算平台的SoC实施方式的功能框图。
具体实施方式
在下文的说明中，阐释了大量的细节，然而对于本领域技术人员来说显而易见的是，本发明可以在没有这些具体细节的情况下实现。在一些实例中，以框图的形式、而不是以细节的方式示出公知的方法和器件，以避免使本发明难以理解。整个说明书中提及的“实施例”表示结合实施例描述的特定特征、结构、功能或特性包含在本发明的至少一个实施例中。因此，在整个说明书中术语“在实施例中”在各种地方的出现不必指代本发明的相同实施例。此外，特定特征、结构、功能或特性可以以任何适合的方式组合在一个或多个实施例中。例如，第一实施例可以与第二实施例结合，只要这两个实施例不互相排斥。
在本文中，术语“耦合”和“连接”以及它们的衍生物可以用于描述部件之间的结构关系。应该理解的是，这些术语不是要作为彼此的同义词。相反，在特定实施例中，“连接”可以用于表示两个或多个元件彼此直接物理或电接触。“耦合”可以用于表示两个或多个元件彼此直接或非直接(在它们之间具有其它中间元件)的物理或电接触，和/或两个或多个元件彼此合作或互动(例如，作为造成影响的关系)。
在本文中使用的术语“在……之上”、“在……之下”、“在……之间”和“在……上”指的是一个材料层相对于另一层的相对位置。同样，例如，设置在另一层之上或之下的一层可以直接与另一层接触，或可以具有一个或多个中间层。此外，设置在两层之间的一层可以直接与这两层接触，或可以具有一个或多个中间层。相比之下，在第二层“上”的第一层与第二层直接接触。
在本文中描述的是Ⅲ族氮化物(Ⅲ-N)半导体纳米线、以及用于制造高电压、高带宽场效应晶体管的制造技术的实施例。在特定实施例中，在集成高功率无线数据传输和/或具有低功率CMOS逻辑数据处理的高电压功率管理功能的SoC架构中采用这种晶体管。纳米线结构需要用于短沟道效应极好的静电控制的“环绕式栅极”，并且因此，容许将Ⅲ族-N晶体管超缩放至低于100nm的尺度。适合于宽带无线数据传输应用的高频操作是可能的，而大带隙Ⅲ-N材料的使用还提供高BV，从而可以产生用于无线数据传输应用的足够的RF输出功率。高Ft和高电压容量的这种组合还使本文中所描述的晶体管的使用成为可能，这是因为DC到DC转换器中的高速切换应用使用减小尺寸的电感元件。由于功率放大和DC到DC切换应用均是智能手机、平板电脑和其它移动平台中的关键功能块，所以针对这样的设备，本文描述的结构可以用于SoC解决方案中。
在实施例中，利用可以包括多种Ⅲ族-N材料的多层半导体结构来形成纳米线、多个垂直叠置的纳米线，并且可以进一步用于将具有不同带隙的半导体材料合并到晶体管的各个区中(例如，可以将更宽带隙的材料合并在器件沟道与漏极触点之间的非本征漏极区中)。在示例性实施例中，栅极结构环绕沟道区的所有边，以提供用于缩放栅极长度(Lg)的沟道电荷的全选通限制。根据实施例，纳米线的一个或多个表面覆盖有宽带隙Ⅲ族-N材料，以提供以下中的一个或多个：增强的沟道迁移率、自发和压电极化的表层电荷[二维电子气(2DEG)]、界面状态的钝化、以及用于沟道电荷载流子限制的能量势垒。
图1A是根据实施例的Ⅲ族-N晶体管100的等距图。通常，Ⅲ族-N晶体管100是通常被称为高电子迁移率晶体管(HEMT)的栅极电压控制的器件(即，FET)。Ⅲ族-N晶体管100包括至少一个非平面结晶半导体主体，其位于与衬底层205的顶表面平行的平面上，晶体管100设置于衬底层205的顶表面上。在实施例中，衬底层205是绝缘的、或半绝缘的、和/或具有设置于其上的绝缘或半绝缘层，其上设置纳米线210A。在一个这样的实施例中，衬底层205是生长在支撑衬底上或转移到施主衬底上(未示出支撑衬底和施主衬底)的Ⅲ族-N半导体的顶层(图1A中所示)。在特定实施例中，衬底层205包括硅支撑衬底，Ⅲ族-N层外延生长在所述硅支撑衬底上，然而，所述支撑衬底还可以具有可选的材料(其可以或可以不与硅组合)，包括但不限于锗、锑化铟、碲化铅、砷化铟、磷化铟、砷化镓、或锑化镓、碳(SiC)和蓝宝石。在另一个实施例中，其上设置晶体管100的衬底层205是介电层，从而衬底层205是掩埋氧化层(BoX)，其可以例如通过将形成纳米线210A的一个或多个半导体层转移到衬底层205上来形成。
如图1A进一步示出的，Ⅲ族-N晶体管100的纵向长度L划分为源极区220、沟道区145、漏极区230和设置于它们之间的非本征漏极区235A。必须特别强调非本征漏极区235A，因为其对器件的BV具有显著影响。至少在沟道区245内，非平面结晶半导体主体通过除了形成主体的结晶半导体或形成衬底层205的材料以外的中间材料与衬底层205物理分隔开，以形成横向取向的纳米线210A。对于本文描述的实施例，纳米线210A的横截面几何结构可以从圆形到矩形有相当大的变化，从而纳米线210A的厚度(即，在z维度上)可以近似等于纳米线210A的宽度(即，在y维度上)，或纳米线210A的厚度和宽度彼此可以有很大的不同(即，物理上类似于带状物，等等)，以形成圆柱形和平行六面体的半导体主体。对于示例性实施例，纳米线210A的宽度在5和50纳米(nm)之间，但是这可以取决于实施方式而变化。
在沟道区245内，纳米线210A具有比多晶材料大得多的长程有序(long rangeorder)。在示例性实施例中，沟道区245基本上是单晶，并且尽管此处被称为“单晶”，普通技术人员将意识到，低水平的晶体缺陷仍然可能作为不完美外延生长过程的工件而出现。在沟道区245内，纳米线210A是包括一种或多种Ⅲ族元素和氮(即，Ⅲ族-N半导体)的第一半导体材料的晶体排列。通常，沟道区245中的该第一Ⅲ族氮化物材料应该具有相对高的载流子迁移率，并且因此在实施例中，为了最小的杂质散射，沟道区245是基本上未掺杂的Ⅲ族氮化物材料(即，杂质浓度最小化)。在第一示例性实施例中，沟道区245是GaN。在第二示例性实施例中，沟道区245是氮化铟(InN)。因为InN具有比GaN大的载流子迁移率(与1900cm2/Vs相比的2700cm2/Vs)，晶体管的度量(例如比导通电阻(Ron))可能对于InN实施例来说相对较好。在第三示例性实施例中，沟道区245是GaN的三元合金，例如铝镓氮化物(AlxGa1-xN)，其中x小于1。在第四示例性实施例中，沟道区245是InN的三元合金，例如铝铟氮化物(AlxIn1-xN)，其中x小于1。在其它实施例中，沟道区245是四元合金，其包括至少一种Ⅲ族元素和氮，例如InxAlyGa1-x-yN。
至少在沟道区245内，纳米线210A被覆盖有第二半导体层215，其设置于纳米线210A的侧壁、顶部、和/或底表面中的一个或多个之上。在示例性实施例中，半导体层215直接设置于纳米线210A的至少两个相对的表面处。图1B是沿着穿过Ⅲ族-N晶体管200的沟道区245的B平面的截面图，其示出设置于纳米线210A(和纳米线210B)的全周长表面上的半导体215。如图2A中进一步示出的，半导体层215在非本征漏极区235A内也覆盖纳米线210A，其中层215用作电荷诱导层。
半导体层215具有第二半导体成分，其带隙宽于沟道区245内的纳米线210A中使用的Ⅲ族-N材料的带隙。优选地，结晶半导体层215基本上是单晶(即，具有小于临界厚度的厚度)，晶格与沟道区245内的纳米线210A中使用的Ⅲ族-N材料匹配。在示例性实施例中，半导体层215具有结晶度与纳米线210的结晶度相同的第二Ⅲ族-N材料，以在沟道区245内形成量子阱异质界面。
通常，用于纳米线210A的所描述的任何Ⅲ族-N材料均可以用于半导体层215，这取决于纳米线210A所选择的材料，以便提供带隙比纳米线210A的带隙大的半导体层215。在纳米线210A是GaN的第一示例性实施例中，半导体层215是AlN。在纳米线210A是InN的第二示例性实施例中，半导体层215是GaN。在纳米线210A是AlxIn1-xN的第三示例性实施例中，半导体层215是AlyIn1-yN，其中y大于x。在纳米线210A是AlxGa1-xN的第四示例性实施例中，半导体层215是AlyGa1-yN，其中y大于x。包括至少一种Ⅲ族元素和氮的四元合金，例如Al1-x-yInxGayN(x、y<1)也是可能的。半导体层215还可以包括这些Ⅲ族氮化物的任何多层叠置，例如，AlxIn1-xN/AIN叠置有邻近(例如，GaN)纳米线210A的叠置的AIN层。
即使在纳米线210A的所有表面上(顶部、底部和侧壁)出现半导体层215的情况下，如图1B中所描述的，厚度仍可以变化。半导体层215在沟道区245内用于至少两种功能。这两种功能是由于半导体结晶体210A内的极性键所引起的不对称和源于相对于半导体层215的这些键的极化方向。根据纳米线210A的晶体取向，纳米线210A的各种相对的表面与不同晶体平面对齐，从而使由半导体层215在这些相对的表面上导致的电场的影响发生变化。
在图2A所示的一个实施例中，纳米线210A的Ⅲ族氮化物所具有的晶体结构被称为纤锌矿结构。可以利用纤锌矿结构来形成本文所描述的GaN和其它Ⅲ族氮化物，所述纤锌矿结构因为其是非中心对称而著名，非中心对称意味着晶体缺少反对称性，并且更具体地，{0001}平面不相等。对于示例性GaN实施例，{0001}平面中的一个通常称为Ga-面(+c极性)，并且另一个被称为N-面(-c极性)。通常对于平面Ⅲ族-N器件，{0001}平面中的一个或另一个更紧邻衬底表面，并且因此如果Ga(或其它Ⅲ族元素)的三个键指向衬底则可以被称为Ga极性(+c)，或者如果Ga(或其它Ⅲ族元素)的三个键指向远离衬底的方向则可以被称为N极性(-c)。然而对于Ⅲ族-N晶体管200的第一实施例，纤锌矿晶体取向是使得具有晶格常数c的(1010)平面形成晶体的顶表面并且连接衬底层205。
如图2B中所进一步示出的，其中纳米线210A具有如图2A中取向的Ⅲ族氮化物材料，半导体层215包括在一个侧壁(例如，215B)上用作电荷诱导层的侧壁部分215A和215B，从而可以在邻近半导体层215的纳米线210A中形成2DEG211A。如此取向，半导体层侧壁部分215A还可以用作背面势垒，以在沟道区245内限制电荷载流子。如图所示，第一侧壁部分215A基本上沿着平面，从而使第一侧壁部分215A的大部分表面位于纳米线210A的平面上。类似地，第二侧壁部分215B基本上沿着(0001)平面，从而使第二侧壁部分110B的大部分表面由(0001)平面界定。因此，将纳米线210A内的自发极化场PSP从第二侧壁部分215B导向第一侧壁部分215B。同样，非平面Ⅲ族-N晶体管200的极化穿过纳米线210A的宽度方向(沿着y维度的横向方向)。
如图2B所进一步示出的，由于半导体层215的结晶，自发极化场PSP也出现在半导体层215内，并且与纳米线210A的自发极化场对齐。此外，当半导体层215处于与侧壁部分215A和215B的高度维度平行的方向(沿着如图2B所示的z维度)上的拉伸应变下时，压电极化场PPE在从第二侧壁部分215B到第一侧壁部分215A的方向上也与PSP对齐。因此，纳米线210A和半导体层215的极化在沿着紧邻第二侧壁部分215B的(0001)平面的异质界面处形成极化场。如麦克斯韦方程所描述的，极化场引起2DEG211A。
对于Ⅲ族-N晶体管200的第二个实施例，纤锌矿晶体取向使得具有晶格常数a的(0001)平面形成晶体的顶表面并且连接衬底层205，如图2D所示。对于该实施例，如图4E所进一步示出的，出现在纳米线210A的顶部和底部上(215D和215C)的半导体层215分别用作电荷诱导层和背面势垒。于是纳米线210A内的半导体层215自发极化场PSP从顶表面部分215D被导向底表面部分215C。同样，非平面Ⅲ族-N晶体管200的极化穿过纳米线210A的厚度方向(沿着z维度的垂直方向)。因此，如图2E所示，纳米线210A以及半导体层部分215D和215C的极化分别在沿着(0001)平面和平面的异质界面处形成极化场，并且该极化场引起与纳米线210A的顶表面相邻的2DEG211A。
在任一个晶体取向(图2A或图2D)中，背面势垒和电荷诱导层均由栅极叠置体250选通。图2C是根据纳米线210A(和纳米线210B)是GaN并且半导体层215是AlN的示例性实施例的非平面Ⅲ族氮化物晶体管的能带图，该非平面Ⅲ族氮化物晶体管由图2B所示的非平面结晶半导体主体形成，其中环绕的栅极结构如图1A中所示。如图2C所示，在零栅极偏压处，能带在纳米线210A的整个截面宽度上并且在半导体层部分215A和半导体层部分215B之间是非对称的。在纳米线210A内的能带由于极化场而弯曲在费米(Fermi)能级EF以下的位置处，出现电荷载流子。如能带图所示，图1B中所示的对称的栅极结构具有由纳米线210A的极化引起的非对称功能。因此，紧邻半导体层部分215B的栅极导体250调制沟道区内的2DEG111的电荷载流子密度，而紧邻半导体层部分215A的栅极导体250调制背面势垒。对于图2D中的取向，在栅极导体填充在纳米线210A与衬底层205之间以完全同轴地环绕纳米线210A的地方，提供相同的选通的背面势垒，如图1A中由沟道区245内的虚线所示。因此图2C的能带图还可以用于图2D的晶体取向。
如图1B中所进一步示出的，栅极叠置体包括栅极导体250，其通过设置于栅极导体下的栅极介电材料240与纳米线210A电隔离，以减少栅极导体与纳米线210A之间的泄露电流。由于栅极叠置体250A设置于半导体层215之上，所以可以将半导体层215和栅极叠置体215的栅极介电材料看作是复合介电叠置体。在图1B中示出的实施例中，还将栅极介电材料240设置于衬底层205与栅极导体250之间。如图1A中所示，同轴缠绕需要设置在纳米线210A与衬底层205之间的区域250A内的栅极导体。
通常，栅极介电材料240可以包括本领域公知的适合于FET栅极电介质的任何材料中的一种或多种，并且优选为高K电介质(即，介电常数比大于氮化硅(Si3N4)的介电常数)，例如，但不限于诸如氧化钆(Gd2O3)、氧化铪(HfO2)的高K氧化物；诸如HfSiO、TaSiO、AlSiO的高K硅酸盐；以及诸如HfON的高K氮化物。类似地，栅极导体250可以是本领域中公知的适合于晶体管栅极电极的任何材料。在实施例中，栅极导体250包括功函数金属，可以选择该功函数金属来获取期望的阈值电压(Vt)(例如，大于0V，等等)。示例性导电栅极材料包括钨(W)、铝(Al)、钛(Ti)、钽(Ta)、镍(Ni)、钼(Mo)、锗(Ge)、铂(Pt)、金(Au)、钌(Ru)、钯(Pd)、铱(Ir)、它们的合金和硅化物、碳化物、氮化物、磷化物、及其碳氮化物。
回到图1A，纳米线210A还包括源极区220和漏极区230。在示例性实施例中，在源极区220和漏极区230内，纳米线210A是在沟道区245中出现的相同的Ⅲ族氮化物半导体材料，但是还包括更高的掺杂浓度，例如n型杂质(即，N+)。在特定实施例中，源极区220和漏极区230内的纳米线210A与沟道区245内的纳米线210A保持相同的单晶。在第一实施例中，半导体材料层212A与源极区220和/或漏极区230内的纳米线210接触。对于Ⅲ族氮化物晶体管200，纳米线210A夹在半导体材料层212A与212B之间。在示例性实施例中，在半导体材料层212A有助于纳米线210A在沟道区245内的底切的地方，半导体材料层212A与纳米线210A具有不同的材料。
在实施例中，半导体材料层212A是针对纳米线210A的实施例所描述的不同于纳米线210A所使用的任何Ⅲ族氮化物。例如，半导体材料层212A可以是AlN、GaN、InN、AlzIn1-zN或AlzGa1-zN，其中z不同于x。在一个实施例中，半导体材料层212A的带隙低于纳米线210A的带隙(例如，z小于x，其中纳米线210A和半导体材料层212A均是三元的)，以帮助减小源极/漏极接触电阻。在可选的实施例中，半导体材料层212A的带隙高于纳米线210A的带隙(例如，z大于x，其中纳米线210A和半导体材料层212A均是三元的)。在纳米线210A的Ⅲ族氮化物和半导体材料层212A的Ⅲ族氮化物是合金或混合的情况下，可以将非本征漏极区235A内的带隙有利地增加到沟道区245中的带隙与半导体材料层212A中的带隙的中间，从而实现甚至更高的BV。同样，根据实施例，晶体管100可以将牺牲性的半导体并入沟道区245内，以选择性地减少或增加沟道区245中采用的半导体材料的带隙。
图1C是根据实施例的Ⅲ族-N晶体管200的等距图。尽管Ⅲ族-N晶体管100具有非本征漏极区235A，其近似等于源极触点222A与沟道区245之间的间距(即，由电介质垫片255确定)，但是Ⅲ族-N晶体管200具有非本征漏极区235B，其大于源极触点222B与沟道区245之间的间距。非本征漏极区235A、235B可以是轻掺杂的并且还包括半导体层215，如图1A和1C中所示。在非本征漏极区235A、B内，半导体层215用作电荷诱导层并且由于非本征漏极区的纵向长度是BV所期望的函数，因此Ⅲ族-N晶体管200具有比Ⅲ族-N晶体管100大的BV。
在一个示例性实施例中，非本征漏极区235B是第一和第二半导体材料的合金，以提供介于第一和第二半导体材料的带隙之间的带隙。如图1C中的空心箭头所示出的，在非本征漏极区235B内，第一和第二半导体材料的合金是无序的多层结构的形式。该多层结构包括夹在半导体材料层212A与212B之间的纳米线210A的Ⅲ族氮化物材料，其通过非本征漏极区235B延伸并且将沟道区245耦合到漏极区230。利用与半导体材料层212A和212B相邻的纳米线210A的相对的边，可以在非本征漏极区235B的部分内实现好的合金均匀性。
在实施例中，Ⅲ族氮化物晶体管包括嵌有源极和/或漏极触点的纳米线的源极区和/或漏极区。图1C示出源极触点222B，其完全同轴地环绕纳米线210A以填充在纳米线210A与衬底层205之间的间隙中。如图1A所示，源极触点222A并未完全环绕纳米线210A，这是因为半导体层212A和212B的存在。源极触点222A、222B可以包括欧姆性金属化层，并且还可以包括与纳米线210A不同成分的外延生长半导体。例如，源极触点222A、222B可以包括隧道结(例如，在源极区220内环绕纳米线210A的p+层)。可以利用这种隧道结来提供超陡峭的导通和截止(即，改进的亚阈值性能)，以减少断开状态泄露电流。
纳米线210A还包括漏极区230。类似于源极区，漏极区可以或多或少地嵌有漏极触点232。在图1C中，在漏极区230内漏极触点232B完全同轴地环绕纳米线210A，以填充在纳米线210A与衬底层205之间的间隙中。如图1A所示，漏极触点232A并未完全环绕纳米线210A，这是由于半导体层212A和212B的存在。类似于源极触点222A、222B，漏极触点232A、232B可以包括欧姆性金属化层，并且还可以包括与纳米线210A不同成分的外延生长半导体。
在实施例中，如图1A和1C中所示，Ⅲ族-N晶体管包括纳米线的垂直叠置体，以针对衬底层上的给定的占用空间来实现较大的电流携载能力(例如，较大的驱动电流)。可以将任何数量的纳米线垂直叠置，这取决于制造限制，并且每个纳米线的纵轴基本上平行于衬底层205的顶表面。在图1A或1C中所示出的示例性实施例中，纳米线210A、210B的每一个在沟道区245内具有相同的第一半导体材料。在其它实施例中，纳米线210A、210B的每一个由栅极叠置体250A(例如，如图1B、2B和2E中所进一步示出的)同轴环绕。至少栅极介电层240将被设置于纳米线210A与210B之间，但是在图1B所示的示例性实施例中，栅极导体也出现在纳米线210A、210B的每一个的沟道区之间。
在图1C所示的实施例中，多个纳米线210B中的每一个通过非本征漏极区235B中的半导体材料物理耦合在一起。对于包括多个纳米线210A、210B的实施例，Ⅲ族-N晶体管100、200具有多个漏极区，在纳米线的垂直叠置体内的每个纳米线对应一个漏极区。可以利用漏极触点(例如，232B)同轴地环绕每个漏极区，该漏极触点完全同轴地环绕漏极区中的每一个，从而填充在纳米线210A、210B之间的间隙中。类似地，源极触点222B可以完全同轴地环绕多个源极区。
现在提供针对晶体管200和201中的每一个的制造过程的显著部分的简要描述。图3是示出根据实施例的制造非平面高电压晶体管200和201的方法300的流程图。尽管方法300突出了主要操作，但是每个操作可能需要更多的过程顺序，并且图3中的操作的标号或操作的相对位置并不暗示任何顺序。图4A、4B、4C、4D和4E是根据方法300的实施例制造的非平面Ⅲ族-N晶体管100、200的等距图。
在操作301处，利用任何标准化学气相沉积(CVD)、分子束外延(MBE)、氢化物气相外延(HVPE)生长技术等(利用标准前驱体、温度，等)来生长单晶半导体材料的叠置体。生长至少两种不同的半导体层来作为外延叠置体的一部分。在实施例中，层212A、212B和212C是第一Ⅲ族氮化物材料，其中第二Ⅲ族氮化物设置在它们之间。
在操作305处，通过针对作为外延叠置体的部分而生长的特定材料，利用本领域公知的任何等离子或湿式化学蚀刻技术，对外延叠置体进行蚀刻来界定纳米线(例如，长和宽)。如图4A中所示，在操作303处，将鳍结构410蚀刻到外延叠置体中以形成纳米线210A、210B，其可以与半导体层212A、212B和212C交替。如图所示，纳米线210A和210B中的每一个均设置于半导体层212A、212B之上和之下。层的厚度T1—T4取决于所期望的纳米线尺寸，并且还取决于在纳米线210A和210B上形成半导体层215之后，利用栅极叠置体回填厚度T1、T3的能力。图4A中还示出，在衬底层205之上的鳍结构401的任一侧上，例如通过浅沟槽隔离技术来形成绝缘层407。
回到图3，在操作305处，形成漏极触点以部分地(如图1A中)或完全地(如图1C中)环绕纳米线210A和210B。在操作310处，以类似的方法形成源极触点。在操作315处，栅极导体完全同轴地环绕纳米线210A和210B的纵向沟道长度。于是在操作320处例如使用常规的互连技术完成器件。
图4B示出需要形成设置于鳍结构410上的牺牲栅极412的操作305、310和315的一个实施例。在一个这样的实施例中，牺牲栅极412由牺牲栅极氧化层和牺牲多晶硅栅极层组成，将所述牺牲栅极氧化层和牺牲多晶硅栅极层均厚沉积并利用常规的光刻和等离子蚀刻技术来图案化。在牺牲栅极412的侧壁上形成垫片，并且可形成夹层介电层来覆盖牺牲栅极412。可对夹层介电层进行抛光来暴露用于替换栅极、或后栅极、过程的牺牲栅极412。参考图4C，已经去除牺牲栅极412，留下垫片255和夹层介电层(ILD)420、421的部分。如图4C中所进一步示出的，在最初由牺牲栅极412覆盖的沟道区中去除半导体层212A、212B和212C。于是留下第一半导体材料的分立的纳米线210A和210B。
如图4D中所示，然后在沟道区245内形成同轴环绕纳米线210A、210B的栅极叠置体250A。图4D示出在半导体层215的外延生长、栅极电介质240的沉积以及栅极导体250的沉积以回填由选择性蚀刻半导体层212A、212B和212C所形成的间隙的栅极叠置体。也就是说，将外延叠置体蚀刻成分立的Ⅲ族-N纳米线之后，在夹层介电层420、421之间的沟槽中形成栅极叠置体。此外，图4D示出了在栅极叠置体250A形成之后，去除夹层介电层420后的结果。对于包括非本征漏极区235B(例如，Ⅲ族氮化物晶体管200)的实施例，在非本征漏极区235A内保留一部分夹层介电层421(例如，利用夹层电介质的光刻界定的掩蔽蚀刻)。对于可选的实施例(例如，对于晶体管Ⅲ族氮化物晶体管100)，不保留ILD421的部分。
对于包括完全同轴地环绕纳米线210A、210B的源极触点和漏极触点的实施例，一旦去除ILD层420、421，那么没有被栅极叠置体保护的半导体层212A和212B的部分则相对于第一半导体材料的纳米线210A、210B被选择性地去除，以在纳米线210A、210B与衬底层205之间形成间隙。于是第一半导体的分立部分保留在源极区220和漏极区230中，如图4D中所示的。然后可以通过回填形成在源极区220和漏极区230内的间隙来形成源极触点222和漏极触点232(如图2A中所示)。在一个这样的实施例中，通过CVD、原子层沉积(ALD)或金属回流来统一沉积触点金属。在可选的实施例中，在半导体层212A和212B以及源极区和漏极区内的纳米线210A和210B的侧壁上形成源极触点222A和漏极触点232A。然后在操作320处例如利用常规的互连金属化等来准备完成器件。
在图4E所示的其它实施例中，可以将ILD421的任何保留的部分选择性地迁移到垫片255、栅极导体250和源极触点222B、漏极触点232B。然后可以在纳米线210A、210B和半导体层212A、212B、212C中的一个之上选择性地去除纳米线210A、210B和半导体层212A、212B、212C中的另一个。在示例性实施例中，然后在(多个)底切间隙中重新外延生长具有比纳米线210A、210B大的带隙的结晶半导体材料。然后半导体层212A、212B、212C可以用作非本征漏极区235B内的电荷诱导层。可以在纳米线210A、210B的侧壁上(例如，在晶体取向是如图2B中所示的情况下)另外生长半导体层215。可替换地，或此外，在去除ILD421的剩余部分之后，可以将诸如Al、Ga或Zn之类的扩散元素并入到非本征漏极区235B内的第一半导体上。
在实施例中，在非本征漏极区235B内出现的半导体材料通过热退火熔合。例如，可以混合第一半导体材料210A、210B和半导体层212A、212B和212C(即，无序的多层结构)。可替换地，热退火可以将半导体材料与扩散元素(例如，Al、Ga或Zn)混合。在一个这样的实施例中，热退火与源极触点和漏极触点的形成(例如，操作305和310)同时进行。值得注意的是，可以在源极触点222和漏极触点232形成之后、和/或在非本征漏极区235B退火之后进行牺牲栅极412的替换。同样，可以在非本征漏极区235B的热退火之后生长半导体层215，以保持沟道区245和/或非本征漏极区235B内的半导体层215与纳米线210A、210B之间的不连贯的异质界面。
图5是根据本发明的实施例的移动计算平台的SoC实施方式的功能性框图。移动计算平台700可以是被配置为电子数据显示、电子数据处理、以及无线电子数据传输中的每一个的任何便携式设备。例如，移动计算平台700可以是平板电脑、智能手机、膝上型计算机等中的任何一个，并且包括在示例性实施例中是允许接收用户输入的触摸屏(例如，电容性、电感性、电阻性，等)的显示屏705、SoC710、以及电池713。如所示，SoC710的集成水平越高，在移动计算平台700内的形状因素就可以越多地被电池713占据以用于在充电之间最长的运转寿命，或越多地被诸如固态硬盘的存储器(未描述)占据以用于最大的功能。
根据其应用，移动计算平台700可以包括其它部件，其包括但不限于易失性存储器(例如，DRAM)、非易失性存储器(例如，ROM)、闪存存储器、图形处理器、数字信号处理器、密码处理器、芯片组、天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编解码器、视频编解码器、功率放大器、全球定位系统(GPS)设备、罗盘、加速计、陀螺仪、扬声器、相机、以及大容量存储设备(例如硬盘驱动器、光盘(CD)、数字通用光盘(DVD)，等等)。
在扩展视图720中进一步示出了SoC710。根据实施例，SoC710包括硅衬底500(即，芯片)的一部分，其上制造以下部件中的两个或多个：功率管理集成电路(PMIC)715、包括RF发送器和/或接收器的RF集成电路(RFIC)725、其控制器711，以及一个或多个中央处理器核730、731。如本领域技术人员将领会的，关于这些功能不同的电路模块，除了在PMIC715和RFIC725中，通常采用专用的CMOS晶体管，该PMIC715和RFIC725通常分别使用LDMOS和Ⅲ-ⅤHBT技术。然而在本发明的实施例中，PMIC715和RFIC725采用本文描述的Ⅲ族氮化物晶体管(例如，Ⅲ族氮化物晶体管100或200)。在其它实施例中，采用本文描述的Ⅲ族氮化物晶体管的PMIC715和RFIC725与一个或多个控制器711集成，并且在硅CMOS工艺中提供的处理器核720、730与PMIC715和RFIC725单片地集成到硅衬底500上。应该领会的是，在PMIC715和/或RFIC725内，本文描述的高电压、高频能力Ⅲ族氮化物晶体管不需要被用于将CMOS排除在外，而是相反还可以将硅CMOS包括在PMIC715和RFIC725中的每一个中。
RFIC725可以实现多种无线标准或协议中的任何一种，包括但不限于Wi-Fi(IEEE802.11系列)、WiMAX(IEEE802.16系列)、IEEE802.20、长期演进(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、蓝牙、它们的衍生物、以及任何其它定名为3G、4G、5G及其以后的无线协议。平台725可以包括多个通信芯片。例如，第一个通信芯片可以专用于较短范围无线通信，例如Wi-Fi和蓝牙；并且第二个通信芯片可以专用于较长范围的无线通信，例如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO、等等。
本文描述的Ⅲ族氮化物晶体管可以特别用于出现高电压摆动的情况(例如，在PMIC715内的7-10V电池功率调节、DC到DC转换，等等)。如所示出的，在示例性实施例中，PMIC715具有耦合到电池713的输入端，并且具有向SoC710中的所有其它功能模块提供电流源的输出端。在其它实施例中，在移动计算平台700内但在SoC710外提供附加的IC的情况下，PMIC715的输出端还向SoC710外部的所有这些附加的IC提供电流源。如进一步示出的，在示例性实施例中，RFIC715具有耦合到天线的输出端，并且还可以具有耦合到SoC710上的诸如RF模拟和数字基带模块(未示出)的通信模块的输入端。可替换地，可以从SoC710在片下IC上提供这种通信模块，并且将其耦合到SoC710中用于传输。根据使用的Ⅲ族氮化物材料，本文描述的Ⅲ族氮化物晶体管(例如，200或201)还可以提供功率放大晶体管所需要的大的功率附加效率(PAE)，该功率放大晶体管具有至少是载频的十倍大小的Ft(例如，在为3G或GSM蜂窝通信而设计的RFIC725中是1.9GHz)。
应该理解的是，上述描述是示例性而非限制性的。例如，尽管附图中的流程图示出了由本发明的特定实施例所执行的操作的特定顺序，但是应该理解的是，可以不需要这种顺序(例如，可选的实施例可以采用不同的顺序来执行操作、组合特定操作、重叠特定操作，等等)。此外，对于本领域技术人员来说，一经阅读并理解了上述描述后，许多其它实施例将是显而易见的。尽管已经参考特定的示例性实施例描述了本发明，但是应该认识到，本发明并不限于所描述的实施例，而是可以在所附权利要求的精神和范围内，在做出修改和替换的情况下实现。因此，应该参考所附权利要求、以及为这些权利要求赋予权利的等价物的完整范围来确定本发明的范围。

Claims (26)

1.一种Ⅲ族-N晶体管，包括：
设置于衬底上的纳米线，其中纵向长度的所述纳米线还包括：
第一Ⅲ族-N材料的沟道区；
与所述沟道区的第一端电耦合的源极区；以及
与所述沟道区的第二端电耦合的漏极区，
栅极叠置体，其包括完全地同轴环绕所述沟道区的栅极绝缘体和栅极导体，以及
第二Ⅲ族-N材料，其沿着所述沟道区的至少一部分而设置在所述第一Ⅲ族-N材料与所述栅极叠置体之间。
2.根据权利要求1所述的Ⅲ族-N晶体管，其中所述第二Ⅲ族-N材料将给背面势垒提供沿着所述纳米线的第一表面形成的异质结，并且利用沿着所述纳米线的第二表面的异质结在所述沟道区内引起2DEG。
3.根据权利要求2所述的Ⅲ族-N晶体管，其中所述第一表面沿着所述纳米线的顶表面，与所述衬底相对，并且其中所述第二表面沿着底表面侧壁，与所述顶表面相对。
4.根据权利要求1所述的Ⅲ族-N晶体管，其中所述纳米线设置在纳米线的垂直叠置体内，其中纳米线中的每一个具有由所述第一Ⅲ族-N材料构成的沟道区，并且其中多个纳米线中的至少两个通过与所述第一Ⅲ族-N材料不同的第三结晶半导体材料，沿着所述纵向长度在一点处物理耦合到一起。
5.根据权利要求4所述的Ⅲ族-N晶体管，其中所述第三结晶半导体材料的带隙大于所述第一Ⅲ族-N材料的带隙。
6.根据权利要求5所述的Ⅲ族-N晶体管，其中所述第一Ⅲ族-N材料和所述第三结晶半导体材料包括外延叠置体，其中所述纳米线各自具有平行于所述衬底而延伸的纵向轴。
7.根据权利要求1所述的Ⅲ族-N晶体管，其中所述漏极区通过非本征漏极区与所述沟道区分隔开，所述非本征漏极区包括第三Ⅲ族-N材料，所述第三Ⅲ族-N材料的带隙宽于所述第一Ⅲ族-N材料的带隙。
8.根据权利要求7所述的Ⅲ族-N晶体管，其中所述非本征漏极区是所述第一Ⅲ族-N材料和所述第三Ⅲ族-N材料的合金，所述非本征漏极区的带隙介于所述第一Ⅲ族-N材料的带隙和所述第三Ⅲ族-N材料的带隙之间。
9.根据权利要求7所述的Ⅲ族-N晶体管，其中所述源极区通过第一纵向长度与所述沟道区间隔开，并且其中所述非本征漏极区具有大于所述第一纵向长度的第二纵向长度。
10.根据权利要求1所述的Ⅲ族-N晶体管，还包括：
完全地同轴环绕所述漏极区的漏极触点；以及
完全地同轴环绕所述源极区的源极触点。
11.根据权利要求1所述的Ⅲ族-N晶体管，其中所述第一Ⅲ族-N材料由GaN构成；或由InN构成；或由AlxIn1-xN构成，其中x小于1；或由AlxGa1-xN构成，其中x小于1。
12.根据权利要求11所述的Ⅲ族-N晶体管，其中所述第二Ⅲ族-N材料包括AlN、GaN、AlyIn1-yN或AlyGa1-xN，其中y大于x。
13.根据权利要求7所述的Ⅲ族-N晶体管，其中所述第三Ⅲ族-N材料包括AlN、GaN、InN、AlzIn1-zN或AlzGa1-zN，其中z不同于x。
14.根据权利要求13所述的Ⅲ族-N晶体管，其中所述漏极区由所述第一Ⅲ族-N材料构成。
15.一种在衬底上形成Ⅲ族-N晶体管的方法，所述方法包括：
在所述衬底上外延生长半导体材料的叠置体，所述叠置体包括至少一种第一Ⅲ族-N材料；
蚀刻所述叠置体以界定纳米线；
沿着所述纳米线的沟道区，在所述第一Ⅲ族-N材料上外延生长第二Ⅲ族-N材料；以及
沿着所述纳米线的纵向沟道长度，形成完全地同轴环绕第一半导体且在所述第二Ⅲ族-N材料之上的栅极导体。
16.根据权利要求15所述的方法，其中蚀刻所述叠置体还包括相对于所述第一Ⅲ族-N材料选择性地去除所述叠置体中所包括的第三Ⅲ族-N材料，以沿着所述纵向沟道长度在所述第一Ⅲ族-N材料与所述衬底之间形成间隙；
其中外延生长所述第二Ⅲ族-N材料还包括在由所述间隙暴露的所述第一Ⅲ族-N材料的表面上生长所述第二Ⅲ族-N材料；以及
其中形成栅极导体还包括利用栅极绝缘体和所述栅极导体沿着所述纵向沟道长度回填所述间隙。
17.根据权利要求16所述的方法，其中外延生长所述半导体材料的叠置体还包括在所述第三Ⅲ族-N材料上生长所述第一Ⅲ族-N材料，并且其中相对于所述第一Ⅲ族-N材料选择性地去除所述第三Ⅲ族-N材料还包括去除所述第三Ⅲ族-N材料以对所述第一Ⅲ族-N材料进行底切。
18.根据权利要求17所述的方法，其中外延生长所述第一Ⅲ族-N材料还包括外延生长一种材料，这种材料由GaN构成；或由InN构成；或由AlxIn1-xN构成，其中x小于1；或由AlxGa1- xN构成，其中x小于1；并且
其中外延生长所述第三Ⅲ族-N材料包括外延生长AlN、GaN、AlzIn1-zN或AlzGa1-zN，其中z不同于x。
19.根据权利要求18所述的方法，其中外延生长所述第二Ⅲ族-N材料还包括生长AlN、GaN、AlyIn1-yN，其中y大于x；或AlyGa1-xN，其中y大于x。
20.根据权利要求17所述的方法，还包括：
在形成所述栅极导体之后，在足以对作为外延叠置体而保留下来的所述第一Ⅲ族-N材料和所述第三Ⅲ族-N材料进行混合的温度处进行热退火。
21.根据权利要求15所述的方法，还包括：
沿着所述纳米线的漏极区，形成完全地同轴环绕所述第一Ⅲ族-N材料的漏极触点；以及
沿着所述纳米线的源极区，形成完全地同轴环绕所述第一Ⅲ族-N材料的源极触点。
22.根据权利要求21所述的方法，其中形成所述漏极触点和所述源极触点还包括：
相对于所述第一Ⅲ族-N材料选择性地去除所述叠置体中所包括的第三Ⅲ族-N材料，以沿着所述源极区和所述漏极区中的每一个在所述第一Ⅲ族-N材料与所述衬底之间形成第二间隙；以及
利用欧姆性金属回填所述第二间隙。
23.一种片上系统(SoC)，包括：
功率管理集成电路(PMIC)，其包括开关稳压器或开关模式DC-DC转换器中的至少一个；以及
RF集成电路(RFIC)，其包括功率放大器，操作所述功率放大器而使其以至少20GHz的截至频率Ft和至少20GHz的最大振荡频率Fmax工作，并且产生至少为2GHz的载波频率，其中将所述功率管理集成电路和所述RF集成电路单片集成到同一个衬底上，并且其中所述功率管理集成电路和所述RF集成电路中的至少一个包括根据权利要求1所述的Ⅲ族-N晶体管。
24.根据权利要求23所述的片上系统，还包括：
集成到所述衬底上的所述功率管理集成电路和所述RF集成电路中的至少一个的控制器，其中所述控制器包括利用硅场效应晶体管制造的CMOS工艺。
25.一种移动计算设备，包括：
触摸屏；
电池；
天线；以及
根据权利要求23所述的片上系统，其中将所述功率管理集成电路耦合到所述电池，并且其中将所述RF集成电路耦合到所述天线。
26.根据权利要求25所述的移动计算设备，还包括第一处理器核和第二处理器核，每个核可操作地耦合到所述触摸屏、所述功率管理集成电路和所述RF集成电路，其中所述第一处理器核和所述第二处理器核包括利用硅场效应晶体管制造的CMOS工艺。
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Families Citing this family (65)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013095342A1 (en) * 2011-12-19 2013-06-27 Intel Corporation High voltage field effect transistors
WO2013095343A1 (en) * 2011-12-19 2013-06-27 Intel Corporation Group iii-n nanowire transistors
WO2013101004A1 (en) * 2011-12-28 2013-07-04 Intel Corporation Contact techniques and configurations for reducing parasitic resistance in nanowire transistors
US8896101B2 (en) * 2012-12-21 2014-11-25 Intel Corporation Nonplanar III-N transistors with compositionally graded semiconductor channels
US20160204207A1 (en) * 2013-09-27 2016-07-14 Intel Corporation Composite High-K Metal Gate Stack for Enhancement Mode GaN Semiconductor Devices
CN108365002B (zh) * 2013-09-27 2021-11-30 英特尔公司 具有ⅲ-ⅴ族材料有源区和渐变栅极电介质的半导体器件
WO2015047354A1 (en) 2013-09-27 2015-04-02 Intel Corporation Improved cladding layer epitaxy via template engineering for heterogeneous integration on silicon
US9455150B2 (en) 2013-12-24 2016-09-27 Intel Corporation Conformal thin film deposition of electropositive metal alloy films
CN106030815B (zh) * 2014-03-24 2020-01-21 英特尔公司 制造纳米线器件的内部间隔体的集成方法
JP2015207651A (ja) * 2014-04-21 2015-11-19 日本電信電話株式会社 半導体装置
US9543440B2 (en) * 2014-06-20 2017-01-10 International Business Machines Corporation High density vertical nanowire stack for field effect transistor
US9269777B2 (en) * 2014-07-23 2016-02-23 Taiwan Semiconductor Manufacturing Company, Ltd. Source/drain structures and methods of forming same
US9306019B2 (en) * 2014-08-12 2016-04-05 GlobalFoundries, Inc. Integrated circuits with nanowires and methods of manufacturing the same
CN106575670B (zh) 2014-09-18 2020-10-16 英特尔公司 用于硅cmos相容半导体器件中的缺陷扩展控制的具有倾斜侧壁刻面的纤锌矿异质外延结构
KR102203497B1 (ko) 2014-09-25 2021-01-15 인텔 코포레이션 독립형 실리콘 메사들 상의 iii-n 에피택셜 디바이스 구조체들
US10573647B2 (en) 2014-11-18 2020-02-25 Intel Corporation CMOS circuits using n-channel and p-channel gallium nitride transistors
US10056456B2 (en) 2014-12-18 2018-08-21 Intel Corporation N-channel gallium nitride transistors
WO2016099570A1 (en) * 2014-12-19 2016-06-23 Intel Corporation Selective deposition utilizing sacrificial blocking layers for semiconductor devices
CN105990414A (zh) * 2015-02-06 2016-10-05 联华电子股份有限公司 半导体结构及其制作方法
CN104934479A (zh) * 2015-05-11 2015-09-23 中国科学院半导体研究所 基于soi衬底的ⅲ-v族纳米线平面晶体管及制备方法
EP3298628A4 (en) 2015-05-19 2019-05-22 INTEL Corporation SEMICONDUCTOR DEVICES WITH SURFACE-DOPED CRYSTALLINE STRUCTURES
EP3314659A4 (en) 2015-06-26 2019-01-23 INTEL Corporation HETEROSEPITAXIAL STRUCTURES WITH STABLE SUBSTRATE INTERFACE MATERIAL AT HIGH TEMPERATURE
US9818872B2 (en) 2015-06-30 2017-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device and method of fabrication thereof
US9853101B2 (en) 2015-10-07 2017-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Strained nanowire CMOS device and method of forming
US9899387B2 (en) * 2015-11-16 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-gate device and method of fabrication thereof
US10204985B2 (en) * 2015-11-16 2019-02-12 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of semiconductor device structure
US10978591B2 (en) * 2015-12-07 2021-04-13 Institute of Microelectronics, Chinese Academy of Sciences Nanowire semiconductor device having high-quality epitaxial layer and method of manufacturing the same
CN105633166B (zh) * 2015-12-07 2019-06-18 中国科学院微电子研究所 具有高质量外延层的纳米线半导体器件及其制造方法
KR102434993B1 (ko) * 2015-12-09 2022-08-24 삼성전자주식회사 반도체 소자
US9425291B1 (en) 2015-12-09 2016-08-23 International Business Machines Corporation Stacked nanosheets by aspect ratio trapping
US9548381B1 (en) * 2015-12-14 2017-01-17 Globalfoundries Inc. Method and structure for III-V nanowire tunnel FETs
WO2017111869A1 (en) 2015-12-24 2017-06-29 Intel Corporation Transition metal dichalcogenides (tmdcs) over iii-nitride heteroepitaxial layers
KR102413782B1 (ko) 2016-03-02 2022-06-28 삼성전자주식회사 반도체 장치
US9570552B1 (en) * 2016-03-22 2017-02-14 Globalfoundries Inc. Forming symmetrical stress liners for strained CMOS vertical nanowire field-effect transistors
US9882000B2 (en) * 2016-05-24 2018-01-30 Northrop Grumman Systems Corporation Wrap around gate field effect transistor (WAGFET)
FR3051970B1 (fr) * 2016-05-25 2020-06-12 Commissariat A L'energie Atomique Et Aux Energies Alternatives Realisation d'une structure de canal formee d'une pluralite de barreaux semi-conducteurs contraints
US9620611B1 (en) 2016-06-17 2017-04-11 Acorn Technology, Inc. MIS contact structure with metal oxide conductor
CN105870062B (zh) * 2016-06-17 2019-05-31 中国科学院微电子研究所 高质量纳米线cmos器件及其制造方法及包括其的电子设备
CN107546125B (zh) * 2016-06-24 2020-05-15 上海新昇半导体科技有限公司 一种基于纳米线的高电子迁移率晶体管及其制作方法
US10134905B2 (en) * 2016-06-30 2018-11-20 International Business Machines Corporation Semiconductor device including wrap around contact, and method of forming the semiconductor device
CN106549047B (zh) * 2016-11-03 2020-10-02 武汉华星光电技术有限公司 一种纳米线无结晶体管及其制备方法
CN108063143B (zh) * 2016-11-09 2020-06-05 上海新昇半导体科技有限公司 一种互补晶体管器件结构及其制作方法
WO2018094205A1 (en) * 2016-11-18 2018-05-24 Acorn Technologies, Inc. Nanowire transistor with source and drain induced by electrical contacts with negative schottky barrier height
US10290546B2 (en) * 2016-11-29 2019-05-14 Taiwan Semiconductor Manufacturing Co., Ltd. Threshold voltage adjustment for a gate-all-around semiconductor structure
US10170378B2 (en) * 2016-11-29 2019-01-01 Taiwan Semiconductor Manufacturing Co., Ltd. Gate all-around semiconductor device and manufacturing method thereof
CN106847910B (zh) * 2017-03-09 2020-07-07 复旦大学 一种GaN基半导体器件及其制备方法
US10535780B2 (en) * 2017-05-08 2020-01-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including an epitaxial layer wrapping around the nanowires
US11101270B2 (en) * 2017-06-29 2021-08-24 Intel Corporation Techniques and mechanisms for operation of stacked transistors
US11233053B2 (en) 2017-09-29 2022-01-25 Intel Corporation Group III-nitride (III-N) devices with reduced contact resistance and their methods of fabrication
US20210367047A1 (en) * 2017-09-29 2021-11-25 Intel Corporation Group iii-nitride (iii-n) devices with reduced contact resistance and their methods of fabrication
WO2019066973A1 (en) * 2017-09-29 2019-04-04 Intel Corporation REDUCED CONTACT RESISTANCE GROUP III (N-N) NITRIDE DEVICES AND METHODS OF MAKING THE SAME
US11557667B2 (en) 2017-09-30 2023-01-17 Intel Corporation Group III-nitride devices with improved RF performance and their methods of fabrication
US11094716B2 (en) 2018-01-12 2021-08-17 Intel Corporation Source contact and channel interface to reduce body charging from band-to-band tunneling
CN108519174B (zh) * 2018-03-27 2020-09-08 中国电子科技集团公司第十三研究所 GaN电桥式绝压压力传感器及制作方法
US11257818B2 (en) 2018-09-27 2022-02-22 Taiwan Semiconductor Manufacturing Co., Ltd. Fin-based field effect transistors
KR102254858B1 (ko) * 2018-09-27 2021-05-26 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 핀 기반의 전계 효과 트랜지스터
US11387329B2 (en) * 2018-09-28 2022-07-12 Intel Corporation Tri-gate architecture multi-nanowire confined transistor
US11101360B2 (en) * 2018-11-29 2021-08-24 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a semiconductor device and a semiconductor device
CN109616519A (zh) * 2018-12-06 2019-04-12 贵阳学院 一种零亚阈摆幅零碰撞电离晶体管器件及制造方法
US11355363B2 (en) 2019-08-30 2022-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacturing
CN114342209A (zh) 2019-09-13 2022-04-12 米沃奇电动工具公司 具有宽带隙半导体的功率转换器
CN111243960A (zh) * 2020-01-20 2020-06-05 中国科学院上海微系统与信息技术研究所 一种半导体纳米线及场效应晶体管的制备方法
US11855225B2 (en) * 2020-02-27 2023-12-26 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with epitaxial bridge feature and methods of forming the same
US11257917B2 (en) 2020-06-05 2022-02-22 Qualcomm Incorporated Gate-all-around (GAA) transistors with additional bottom channel for reduced parasitic capacitance and methods of fabrication
KR20220051884A (ko) 2020-10-19 2022-04-27 삼성전자주식회사 반도체 소자

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6921700B2 (en) * 2003-07-31 2005-07-26 Freescale Semiconductor, Inc. Method of forming a transistor having multiple channels
CN101252148A (zh) * 2007-02-23 2008-08-27 高丽大学校产学协力团 非易失性电子存储器件及其制作方法

Family Cites Families (54)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6664575B2 (en) 2000-12-05 2003-12-16 Showa Denko Kabushiki Kaisha GaInP stacked layer structure and field-effect transistor manufactured using the same
US7030428B2 (en) 2001-12-03 2006-04-18 Cree, Inc. Strain balanced nitride heterojunction transistors
US7135728B2 (en) 2002-09-30 2006-11-14 Nanosys, Inc. Large-area nanoenabled macroelectronic substrates and uses therefor
US7101761B2 (en) * 2003-12-23 2006-09-05 Intel Corporation Method of fabricating semiconductor devices with replacement, coaxial gate structure
FR2875338B1 (fr) 2004-09-13 2007-01-05 Picogiga Internat Soc Par Acti Methode d'elaboration de structures hemt piezoelectriques a desordre d'alliage nul
US20060086977A1 (en) * 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
KR100594327B1 (ko) * 2005-03-24 2006-06-30 삼성전자주식회사 라운드 형태의 단면을 가지는 나노와이어를 구비한 반도체소자 및 그 제조 방법
KR100618900B1 (ko) * 2005-06-13 2006-09-01 삼성전자주식회사 다중 채널을 갖는 모스 전계효과 트랜지스터의 제조방법 및그에 따라 제조된 다중 채널을 갖는 모스 전계효과트랜지스터
CN101273459B (zh) * 2005-06-16 2013-01-02 昆南诺股份有限公司 半导体纳米线晶体管
US7354831B2 (en) * 2005-08-08 2008-04-08 Freescale Semiconductor, Inc. Multi-channel transistor structure and method of making thereof
US8853666B2 (en) 2005-12-28 2014-10-07 Renesas Electronics Corporation Field effect transistor, and multilayered epitaxial film for use in preparation of field effect transistor
FR2897204B1 (fr) * 2006-02-07 2008-05-30 Ecole Polytechnique Etablissem Structure de transistor vertical et procede de fabrication
US7388236B2 (en) 2006-03-29 2008-06-17 Cree, Inc. High efficiency and/or high power density wide bandgap transistors
US7945208B2 (en) 2006-08-14 2011-05-17 Gct Semiconductor, Inc. Radio frequency integrated circuit
JP4296195B2 (ja) 2006-11-15 2009-07-15 シャープ株式会社 電界効果トランジスタ
JP4436843B2 (ja) 2007-02-07 2010-03-24 株式会社日立製作所 電力変換装置
GB0801494D0 (en) * 2007-02-23 2008-03-05 Univ Ind & Acad Collaboration Nonvolatile memory electronic device using nanowire used as charge channel and nanoparticles used as charge trap and method for manufacturing the same
TW200903858A (en) 2007-03-09 2009-01-16 Univ California Method to fabricate III-N field effect transistors using ion implantation with reduced dopant activation and damage recovery temperature
JP4584293B2 (ja) 2007-08-31 2010-11-17 富士通株式会社 窒化物半導体装置、ドハティ増幅器、ドレイン電圧制御増幅器
US8188513B2 (en) 2007-10-04 2012-05-29 Stc.Unm Nanowire and larger GaN based HEMTS
JP4966153B2 (ja) * 2007-10-05 2012-07-04 株式会社東芝 電界効果トランジスタおよびその製造方法
WO2009113612A1 (ja) 2008-03-12 2009-09-17 日本電気株式会社 半導体装置
US8106459B2 (en) 2008-05-06 2012-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs having dielectric punch-through stoppers
US8017933B2 (en) 2008-06-30 2011-09-13 Intel Corporation Compositionally-graded quantum-well channels for semiconductor devices
US8120063B2 (en) * 2008-12-29 2012-02-21 Intel Corporation Modulation-doped multi-gate devices
US7893492B2 (en) * 2009-02-17 2011-02-22 International Business Machines Corporation Nanowire mesh device and method of fabricating same
US7816275B1 (en) * 2009-04-03 2010-10-19 International Business Machines Corporation Gate patterning of nano-channel devices
US7902541B2 (en) * 2009-04-03 2011-03-08 International Business Machines Corporation Semiconductor nanowire with built-in stress
US20100270591A1 (en) 2009-04-27 2010-10-28 University Of Seoul Industry Cooperation Foundation High-electron mobility transistor
US8963118B2 (en) * 2009-07-31 2015-02-24 Agency For Science, Technology And Research Transistor arrangement and a method of forming a transistor arrangement
US8216902B2 (en) * 2009-08-06 2012-07-10 International Business Machines Corporation Nanomesh SRAM cell
WO2011038228A1 (en) * 2009-09-24 2011-03-31 President And Fellows Of Harvard College Bent nanowires and related probing of species
US8623451B2 (en) * 2009-11-10 2014-01-07 Georgia Tech Research Corporation Large-scale lateral nanowire arrays nanogenerators
US8563395B2 (en) * 2009-11-30 2013-10-22 The Royal Institute For The Advancement Of Learning/Mcgill University Method of growing uniform semiconductor nanowires without foreign metal catalyst and devices thereof
US8598003B2 (en) * 2009-12-21 2013-12-03 Intel Corporation Semiconductor device having doped epitaxial region and its methods of fabrication
US20110147840A1 (en) * 2009-12-23 2011-06-23 Cea Stephen M Wrap-around contacts for finfet and tri-gate devices
US8193523B2 (en) 2009-12-30 2012-06-05 Intel Corporation Germanium-based quantum well devices
US8344425B2 (en) 2009-12-30 2013-01-01 Intel Corporation Multi-gate III-V quantum well structures
US8921894B2 (en) 2010-03-26 2014-12-30 Nec Corporation Field effect transistor, method for producing the same, and electronic device
CN102280375B (zh) 2010-06-08 2013-10-16 中国科学院微电子研究所 一种先栅工艺中叠层金属栅结构的制备方法
US8298881B2 (en) * 2010-06-28 2012-10-30 International Business Machines Corporation Nanowire FET with trapezoid gate structure
US8536563B2 (en) * 2010-09-17 2013-09-17 International Business Machines Corporation Nanowire field effect transistors
KR101713920B1 (ko) * 2011-09-29 2017-03-09 인텔 코포레이션 반도체 응용을 위한 양전성 금속 포함 층
US8580624B2 (en) * 2011-11-01 2013-11-12 International Business Machines Corporation Nanowire FET and finFET hybrid technology
WO2013095342A1 (en) * 2011-12-19 2013-06-27 Intel Corporation High voltage field effect transistors
WO2013095343A1 (en) * 2011-12-19 2013-06-27 Intel Corporation Group iii-n nanowire transistors
WO2013096821A1 (en) 2011-12-21 2013-06-27 Massachusetts Institute Of Technology Aluminum nitride based semiconductor devices
US8890119B2 (en) * 2012-12-18 2014-11-18 Intel Corporation Vertical nanowire transistor with axially engineered semiconductor and gate metallization
US8896101B2 (en) * 2012-12-21 2014-11-25 Intel Corporation Nonplanar III-N transistors with compositionally graded semiconductor channels
US9184269B2 (en) * 2013-08-20 2015-11-10 Taiwan Semiconductor Manufacturing Company Limited Silicon and silicon germanium nanowire formation
US8872161B1 (en) * 2013-08-26 2014-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. Integrate circuit with nanowires
US9450046B2 (en) * 2015-01-08 2016-09-20 Taiwan Semiconductor Manufacturing Co., Ltd Semiconductor structure with fin structure and wire structure and method for forming the same
US20170170268A1 (en) * 2015-12-15 2017-06-15 Qualcomm Incorporated NANOWIRE METAL-OXIDE SEMICONDUCTOR (MOS) FIELD-EFFECT TRANSISTORS (FETs) (MOSFETs) EMPLOYING A NANOWIRE CHANNEL STRUCTURE HAVING ROUNDED NANOWIRE STRUCTURES
US10157992B2 (en) * 2015-12-28 2018-12-18 Qualcomm Incorporated Nanowire device with reduced parasitics

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6921700B2 (en) * 2003-07-31 2005-07-26 Freescale Semiconductor, Inc. Method of forming a transistor having multiple channels
CN101252148A (zh) * 2007-02-23 2008-08-27 高丽大学校产学协力团 非易失性电子存储器件及其制作方法

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