TWI556448B - 第三族氮化物奈米線電晶體 - Google Patents

第三族氮化物奈米線電晶體 Download PDF

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TWI556448B
TWI556448B TW104104569A TW104104569A TWI556448B TW I556448 B TWI556448 B TW I556448B TW 104104569 A TW104104569 A TW 104104569A TW 104104569 A TW104104569 A TW 104104569A TW I556448 B TWI556448 B TW I556448B
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Taiwan
Prior art keywords
group iii
iii nitride
nanowire
layer
channel region
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TW104104569A
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TW201539761A (zh
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漢威 陳
羅伯特 趙
班傑明 朱功
吉伯特 狄威
傑克 卡瓦李耶羅
馬修 梅茲
尼洛依 穆可吉
拉維 皮拉瑞斯提
馬可 拉多撒福傑維克
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英特爾股份有限公司
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Description

第三族氮化物奈米線電晶體
本發明之實施例大致關於微電子裝置及製造，更具體地關於第三族氮化物電晶體。
系統單晶片(SoC)在過去幾十年內已實現一些功能。SoC解決方案提供無法由板級元件集成所匹敵的微縮(scaling)優點。當類比及數位電路早已被集成到相同基底上以提供Soc的一種形式，該種SoC形式提供混合信號功能時，用於諸如智慧型手機及平板之行動計算平台的SoC解決方案仍然難以捉摸，因為這些裝置典型地包括以兩個以上之高電壓、高功率及高頻率操作之元件。因此，傳統的行動計算平台典型地使用第三至五族化合物半導體，例如GaAs異質接面雙極電晶體(HBTs)，以產生在GHz載波頻率之足夠的功率放大，及使用橫向擴散矽MOS(LDMOS)技術以管理電壓轉換及功率分佈(包括升壓及/或降壓的電壓轉換等的電池電壓調節)。實現CMOS技術之傳統的矽場效電晶體係成為行動計算平台內 用於邏輯及控制功能的第三裝置技術。
在行動計算平台中使用的多個電晶體技術整體而言限制了裝置的可微縮性，且因而成為更多功能、更高集成度、更低成本及更小形狀因素等的障礙。當用於行動計算空間之SoC解決方案，其可集成兩個以上之這些第三裝置技術，因而有吸引力時，SoC解決方案之一個障礙為缺乏具有足夠速度(即，足夠高的增益截止頻率，Ft)及足夠高的崩潰電壓(BV)兩者之可微縮的電晶體技術。
一個有前景的電晶體技術係基於第三族氮化物(III-N)。然而，這種電晶體技術面臨微縮至特徵尺寸(例如，閘極長度)小於100nm的基本困難，在此情形下短通道效應變得難以控制。具有良好控制之短通道效應的微縮第三族氮化物電晶體因而對於以足夠高的崩潰電壓(BV)來達到高Ft係重要的。對於提供產品特定電流及行動計算平台之功率要求的SoC解決方案而言，需要能夠處理高輸入電壓波動(swing)及提供在RF頻率之高功率附加效率的快速切換高電壓電晶體。可微縮及順應此種性能之先進的第三族氮化物電晶體因此係有利的。
100‧‧‧第三族氮化物電晶體
200‧‧‧第三族氮化物電晶體
205‧‧‧基底層
210A‧‧‧奈米線
210B‧‧‧奈米線
211A‧‧‧二維電子氣
220‧‧‧源極區
245‧‧‧通道區
230‧‧‧汲極區
235A‧‧‧外部汲極區
235B‧‧‧外部汲極區
215‧‧‧半導體層
215A‧‧‧側壁部分
215B‧‧‧側壁部分
215D‧‧‧頂表面部分
215C‧‧‧底表面部分
250‧‧‧閘極堆疊
250A‧‧‧閘極堆疊
240‧‧‧閘極介電層
212A‧‧‧半導體材料層
212B‧‧‧半導體材料層
212C‧‧‧半導體材料層
255‧‧‧間隔物
222‧‧‧源極接觸
222A‧‧‧源極接觸
222B‧‧‧源極接觸
232‧‧‧汲極接觸
232A‧‧‧汲極接觸
232B‧‧‧汲極接觸
407‧‧‧絕緣層
410‧‧‧鰭狀結構
412‧‧‧犧牲閘極
420‧‧‧層間介電層
421‧‧‧層間介電層
700‧‧‧行動計算平台
705‧‧‧顯示螢幕
710‧‧‧系統單晶片
713‧‧‧電池
500‧‧‧矽基板
715‧‧‧電源管理積體電路
725‧‧‧RF積體電路
711‧‧‧控制器
730‧‧‧中央處理器核心
731‧‧‧中央處理器核心
本發明之實施例係透過示例的方式而非透過限制的方式示出，且當結合附圖考慮時，可參照下面詳細說明而更全面地了解，其中：圖1A係依據一實施例之第三族氮化物電晶體的等角 圖；圖1B係圖1A中所示之第三族氮化物電晶體之通道區的橫截面圖；圖1C係依據一實施例之第三族氮化物電晶體的等角圖；圖2A係依據一實施例之第三族氮化物電晶體之GaN晶體取向的等角圖；圖2B係第三族氮化物電晶體之通道區的橫截面圖，該第三族氮化物電晶體採用具有圖2A中所示之晶體取向的非平面GaN本體；圖2C係圖2B中所示之通道區的能帶圖；圖2D係依據一實施例之第三族氮化物電晶體之GaN晶體取向的等角圖；圖2E係第三族氮化物電晶體之通道區的橫截面圖，該第三族氮化物電晶體採用具有圖2D中所示之晶體取向的非平面GaN本體；圖3係圖示依據一實施例之非平面高電壓電晶體之製造方法的流程圖；圖4A、4B、4C、4D及4E係依據圖3中所示之方法實施例所製造的非平面高電壓電晶體的等角圖；及圖5係依據本發明之實施例之行動計算平台之SoC實作的功能方塊圖。
【發明內容及實施方式】
在下面說明中闡述許多細節，熟習此技藝之人士將更清楚的是無需這些具體細節亦可實施本發明。在某些情況下，以方塊圖形式而非詳細地示出習知的方法及裝置，以避免模糊本發明。本說明書中所指之「一實施例」意味著結合該實施例所描述之特定特徵、結構、功能或特性係包含於本發明之至少一個實施例中。因此，在本說明書中多處出現之「在一實施例中」之詞不一定指本發明之相同的實施例。此外，特定特徵、結構、功能或特性可能在一或多個實施例中以任何適合的方式結合。例如，一第一實施例可能與一第二實施例結合，該兩個實施例在各處係互斥的。
「耦合」與「連結」之詞及它們的衍生詞可在本文被用來描述元件之間的結構關係。應可了解的是，這些詞並非企圖成為彼此的同義詞。相反地，在特定實施例中，「連結」可被用來指示兩個或更多個元件係彼此直接物理接觸或電性接觸。「耦合」可被用來指示兩個或更多個元件係彼此直接或間接(以它們之間的其他中間元件)物理接觸或電性接觸，及/或指示兩個或更多個元件彼此合作或交互(例如，作為一因果關係)。
本文所使用之「之上」、「之下」、「之間」及「上」之詞指的是一個材料層相對於其他層的相對位置。因此，例如，設置在其他層之上或之下的一層可能直接地接觸該其他層或可能具有一或多個中間層。此外，設置在兩層之間的一層可能直接地接觸該兩層或可能具有一或多 個中間層。相反地，在一第二層「上」的一第一層係直接地接觸該第二層。
本文所述為第三族氮化物(III-N)半導體奈米線之實施例，及致能高電壓、高帶寬場效電晶體之製造的製造技術。在特定實施例中，在集成高功率無線資料傳輸及/或具有低功率CMOS邏輯資料處理之高電壓功率管理功能的SoC架構中採用此種電晶體。奈米線結構涉及用於短通道效應之優異靜電控制的「環繞式閘極(gate-all-around)」，且因此，允許第三族氮化物電晶體之超微縮至次百奈米(sub-100nm)定制。適用於寬頻無線資料傳輸應用之高頻率操作係可能的，同時大能帶隙第三族氮化物材料之使用亦提供高BV，使得可能產生用於無線資料傳輸應用之足夠的RF輸出功率。高Ft及高電壓能力之此種組合亦使得可以將本文所述之電晶體用於使用縮小尺寸之感應元件的DC至DC轉換器中的高速切換應用。由於功率放大及DC至DC切換應用兩者為智慧型手機、平板、及其他行動平台中的關鍵功能塊，本文所述之結構可被用於此種裝置之SoC解決方案。
在實施例中，可包括複數個第三族氮化物材料之一多層半導體結構，被充分利用來形成奈米線、複數個垂直堆疊的奈米線，且可被進一步利用來將具有不同能帶隙的半導體材料併入電晶體的各種區域(例如，更寬能帶隙的材料可被併入裝置通道及汲極接觸之間的外部汲極區)。在範例實施例中，閘極結構環繞通道區域之所有側，以提供 用於閘極長度(Lg)之微縮的通道電荷的完整閘極式侷限。取決於實施例，奈米線的一或多個表面係以寬能帶隙之第三族氮化物材料覆蓋，以提供下列之一或多者：增強型通道遷移率、由自發及壓電極化產生之片電荷[二維電子氣(2DEG)]、界面狀態的鈍化、及通道電荷載子侷限之能量障礙。
圖1A係依據一實施例之第三族氮化物電晶體100的等角圖。通常，第三族氮化物電晶體100為閘極電壓控制裝置(即，FET)，其通常被稱為高電子遷移率電晶體(HEMT)。第三族氮化物電晶體100包括至少一個非平面結晶半導體本體，其在平行於其上設置有電晶體100的基底層205之上表面的平面上。在一實施例中，基底層205係絕緣的或半絕緣的，及/或具有設置於其上的絕緣或半絕緣層，在該基底層上設置有奈米線210A。在這樣一個實施例中，基底層205係成長於支撐基底上或轉移至施體基底上(支撐及施體基底未圖示)之第三族氮化物半導體(示於圖1A中)的上層。在特定實施例中，基底層205包括矽支撐基底，其上磊晶成長有第三族氮化物層，然而，支撐基底亦可具有可能或可能不與矽結合的替代材料，包括但不限於，鍺、銻化銦、碲化鉛、砷化銦、磷化銦、砷化鎵或銻化鎵、碳(SiC)及藍寶石。在另一實施例中，其上設置有電晶體100的基底層205為介電層，使得基底層205為埋入式氧化物(BoX)，其可能例如由轉移半導體之一或多層至基底層205而形成，奈米線210A 係由該半導體所形成。
如圖1A中進一步所示，第三族氮化物電晶體100之縱向長度L在被劃分為源極區220、通道區245、汲極區230及設置於其間的外部汲極區235A。特別強調外部汲極區235A，因為其在裝置之BV上具有顯著效果。至少在通道區245內，非平面結晶半導體本體係藉由除了形成本體的結晶半導體或形成基底層205的材料之外的中間材料，而被物理地自基底層205分開，以形成橫向取向的奈米線210A。對於本文所述之實施例而言，奈米線210A之橫截面的幾何形狀可能自圓形至矩形非常不同，使得奈米線210A之厚度(即，在z維度)可能大約等於奈米線210A之寬度(即，在y維度)，或者奈米線210A之厚度及寬度可能彼此顯著地不同(即，物理地類似於帶狀等)，以形成圓柱體及平行六面體的半導體本體。對於範例實施例而言，奈米線210A之寬度在5及50奈米(nm)之間，但這可能取決於實作而不同。
在通道區245之內，奈米線210A具有比多晶材料更大的長程有序(long range order)。在範例實施例中，通道區245為實質上單晶，雖然本文稱為「單晶體(monocrystalline)」，然而熟習此技藝之人士將理解到，一低程度的晶體缺陷可能存在作為不完善的磊晶成長製程的人造物(artifact)。在通道區245之內，奈米線210A為包括一或多個第三族元素及氮的第一半導體材料(即，第三族氮化物半導體)之結晶排列。通常，通道區 245中的此第一第三族氮化物材料應具有相對高的載子遷移率，且因此在實施例中，通道區245將成為用於最小雜質散射之實質上未摻雜的第三族氮化物材料(即，雜質濃度最小化)。在第一範例實施例中，通道區245為GaN。 在第二範例實施例中，通道區245為氮化銦(InN)。因為InN具有大於GaN的載子遷移率(2700cm2/Vs，相比於1900cm2/Vs)，對於InN實施例而言，電晶體度量指標，諸如特定導通電阻(Ron)，可能相對較佳。在第三範例實施例中，通道區245為GaN的三元合金，諸如氮化鋁鎵(AlxGa1-xN)，其中x小於1。在第四範例實施例中，通道區245為InN的三元合金，諸如氮化鋁銦(AlxIn1-xN)，其中x小於1。在其他實施例中，通道區245為包括至少一個第三族元素及氮的四元合金，諸如InxAlyGa1-x-yN。
至少在通道區245內，奈米線210A被一第二半導體層215覆蓋，該第二半導體層215被設置在奈米線210A之一或多個側壁、頂表面及/或底表面之上。在範例實施例中，半導體層215被直接設置在奈米線210A之至少兩個相對的表面。圖1B為通過第三族氮化物電晶體100之通道區245沿著B平面的橫截面圖，示出設置在奈米線210A(及奈米線210B)之所有周邊表面上的半導體層215。如圖1A中進一步所示，半導體層215亦覆蓋在外部汲極區235A內的奈米線210A，其中層215作用如同電荷誘導層。
半導體層215具有第二半導體組成物，其具有較通道區245內之奈米線210A中所使用之第三族氮化物材料之能帶隙更寬的能帶隙。較佳地，結晶半導體層215為實質上單晶體(即，具有低於臨界厚度之厚度)，其與通道區245內之奈米線210A中所使用之第三族氮化物材料晶格匹配。在範例實施例中，半導體層215具有第二第三族氮化物材料，其具有與奈米線210之結晶度相同的結晶度，以形成通道區245內之量子阱異質界面。
通常，所述用於奈米線210A之任何第三族氮化物材料可被用於半導體層215，如同取決於所選用於奈米線210A之材料以提供半導體層215大於奈米線210A之能帶隙。在奈米線210A為GaN之第一範例實施例中，半導體層215為AlN。在奈米線210A為InN之第二範例實施例中，半導體層215為GaN。在奈米線210A為AlxIn1-xN之第三實施例中，半導體層215為AlyIn1-yN，其中y大於x。在奈米線210A為AlxGa1-xN之第四實施例中，半導體層215為AlyGa1-yN，其中y大於x。包括至少一個第三族元素及氮之四元合金，諸如Al1-x-yInxGayN(x,y<1)，亦為可能的。半導體層215可能另外包含這些第三族氮化物之任何多層堆疊，例如，AlxIn1-xN/AlN堆疊，具有相鄰於(例如，GaN)奈米線210A之堆疊的AlN層。
即使在半導體層215存在於奈米線210A之所有表面上(頂表面、底表面及側壁)的情形中，如圖1B中所示，厚度仍可能不同。半導體層215在通道區245內提供 至少兩個功能。該兩個功能為半導體結晶體210A內之極性鍵所導致之不對稱的結果以及由相對於半導體層215的這些鍵所造成的極化方向。取決於奈米線210A之晶體取向，奈米線210A之各相對表面係與不同的結晶平面對齊，使得由於在這些相對表面上的半導體層215所導致的電場效應不同。
在一實施例中，由圖2A所示，奈米線210A之第三族氮化物具有已知為纖鋅礦(wurtzite)結構的結晶結構。本文所述之GaN及其他第三族氮化物可能以纖鋅礦結構形成，該纖鋅礦結構係以其為非中心對稱而著名，此意味著結晶缺乏反轉對稱，更具體的是{0001}平面係不相等的。對於範例GaN實施例而言，{0001}平面之一係典型地被稱為Ga-面(+c極性)，而其他被稱為N-面(-c極性)。通常對於平面第三族氮化物裝置而言，{0001}平面之其中一者或另一者係更靠近基板表面，因而，若Ga(或其他第三族元素)的三個鍵指向該基板，則可能被稱為Ga極性(+c)，或者若Ga(或其他第三族元素)的三個鍵指離該基板，則可能被稱為N極性(-c)。然而對於第三族氮化物電晶體200之第一實施例而言，纖鋅礦晶體取向係如：具有晶格常數c的(1010)平面形成該結晶的頂表面，並界面接合基底層205。
如圖2B中進一步所示，在奈米線210A具有如圖2A中之取向的第三族氮化物材料的情形中，半導體層215包括側壁部分215A及215B，其作用如同在側壁之其中一者 (例如，215B)上的電荷誘導層，使得2DEG 211A可形 成在鄰近半導體層215之奈米線210A中。如此取向，半導體層側壁部分215A可進一步作為背阻障(back barrier)以侷限通道區245內之電荷載子。如所示，第一側壁部分215A係實質上沿著(000)平面，使得第一側壁部分215A的大部分表面在奈米線210A的(000)平面上。相同地，第二側壁部分215B係實質上沿著(0001)平面，使得第二側壁215B的大部分表面係由(0001)平面來定義。在奈米線210A內之自發極化場PSP係因此由第二側壁部分215B指向第一側壁部分215A。如此，非平面第三族氮化物電晶體200之極性係通過奈米線210A之寬度(沿y-維度橫向)。
如圖2B中進一步所示，因為半導體層215的結晶性，自發極化場PSP亦存在半導體層215內，且與奈米線210A之自發極化場對齊。此外，當半導體層215在平行於側壁部分215A及215B之高度維度(沿著如圖2B中所示之z-維度)方向中的拉伸應變下時，壓電極化場PPE亦在自第二側壁部分215B至第一側壁部分215A的方向中對齊PSP。奈米線210A及半導體層215之極化因而在沿著靠近第二側壁部分215B之(0001)平面的異質界面處形成極化場。如麥斯威爾方程組(Maxwell’s equations)所述，極化場誘導2DEG 211A。
對於第三族氮化物電晶體200之第二實施例而言，纖鋅礦晶體取向係如：具有晶格常數a的(0001)平面形成 該結晶的頂表面，並界面接合基底層205，如圖2D中所示。對於此實施例而言，如圖2E中進一步所示，存在奈米線210A之頂部及底部上之半導體層215(215D及215C)，分別作用如同電荷誘導層及背阻障。奈米線210A內之自發極化場PSP係因而由頂表面部分215D指向底表面部分215C。如此，非平面第三族氮化物電晶體200之極化係通過奈米線210A之厚度(沿z-維度垂直)。如圖2E中所示，奈米線210A及半導體層部分215D及215C之極化因而分別在沿著(0001)平面及(000)之異質界面處形成極化場，具有誘導鄰近奈米線210A之頂表面之2DEG 211A的極化場。
在任一晶體取向(圖2A或圖2D)中，背阻障及電荷誘導層兩者皆由閘極堆疊250所閘控。圖2C係依據奈米線210A(及奈米線210B)為GaN且半導體層215為AlN之範例實施例之自圖2B中所示之非平面結晶半導體本體所形成之非平面第三族氮化物電晶體的能帶圖，具有如圖1A中所示之環繞閘極結構。如圖2C中所示，在零閘極偏壓處，跨過奈米線210A之橫截面寬度及在半導體層部分215A及半導體層部分215B之間的波段係不對稱的。在奈米線210A內波段自極化場彎曲低於費米能階EF的位置處，存在有電荷載子。如由該能帶圖所示，圖1B中所示之對稱閘極結構具有由奈米線210A之極性所引起的不對稱功能。當靠近半導體層部分215A之閘極導體250調變背阻障時，靠近半導體層部分215B之閘極導體250因此 調變通道區內2DEG 111之電荷載子密度。對於圖2D中之取向而言，於閘極導體填滿奈米線210A及基底層205之間提供相同閘控背阻障，以在通道區245內完全地同軸環繞奈米線210A，如圖1A中以虛線所示。圖2C之能帶圖係因此亦可適用於圖2D之晶體取向。
如圖1B中進一步所示，閘極堆疊包括閘極導體250，其藉由設置在該閘極導體之下的閘極介電材料240與奈米線210A電性隔離，以減少該閘極導體與奈米線210A之間的漏電流。因為閘極堆疊係設置於半導體層215之上，半導體層215及閘極堆疊之閘極介電材料可被視為複合介電堆疊。在圖1B所示之實施例中，閘極介電材料240係進一步設置在基底層205及閘極導體250之間。如圖1A中所示，同軸環繞涉及在區域250A內設置於奈米線210A及基底層205之間的閘極導體。
通常，閘極介電材料240可能包括適於FET閘極介電質之一或多個本領域已知的任何材料，且較佳為高K介電質(即，具有介電常數大於氮化矽(Si3N4)的介電常數)，諸如，但不限於，如氧化釓(Gd2O3)、氧化鉿(HfO2)之高K氧化物、諸如HfSiO,TaSiO,AlSiO之高K矽酸鹽、及諸如HfON之高K氮化物。相同的，閘極導體250可具有用於電晶體閘極電極之本領域已知的任何材料。在一實施例中，閘極導體250包括功函數金屬，其可被選擇來獲得所欲之臨界電壓(Vt)(例如，大於0V等)。範例導電閘極材料包括鎢(W)、鋁(Al)、鈦 (Ti)、鉭(Ta)、鎳(Ni)、鉬(Mo)、鍺(Ge)、 鉑(Pt)、金(Au)、釕(Ru)、鈀(Pd)、銥(Ir)、該等元素之合金及其矽化物、碳化物、氮化物、磷化物及碳氮化物。
回到圖1A，奈米線210A進一步包括源極區220及汲極區230。在範例實施例中，在源極區220及汲極區230內，奈米線210A係存在通道區245中之相同的第三族氮化物半導體材料，但可能另外包括更高濃度的摻雜物，諸如n型雜質(即，N+)。在某些實施例中，源極區220及汲極區230內之奈米線210A保持與在通道區245內相同的單結晶體。在第一實施例中，半導體材料層212A係與源極及/或汲極區220、230內之奈米線210接觸。對於第三族氮化物電晶體200而言，奈米線210A係夾在半導體材料層212A及212B之間。在範例實施例中，在半導體材料層212A促進通道區245內之奈米線210A的下部切割的情形下，半導體材料層212A具有與奈米線210A不同的材料。
在實施例中，半導體材料層212A係所述用於奈米線210A之實施例之第三族氮化物的任一者，其不同於用於奈米線210A之該者。例如，半導體材料層212A可為AlN、GaN、InN、AlzIn1-zN或AlzGa1-zN，其中z不同於x。在一實施例中，半導體材料層212A之能帶隙低於奈米線210A之能帶隙(例如，z小於x，其中奈米線210A及半導體材料層212A兩者均為三元的)，以協助降低源極/ 汲極接觸電阻。在替代實施例中，半導體材料層212A之能帶隙高於奈米線210A之能帶隙(例如，z大於x，其中奈米線210A及半導體材料層212A兩者均為三元的)。 在奈米線210A之第三族氮化物及半導體材料層212A之第三族氮化物係合金的或混合(intermixed)的情形中，外部汲極區235A內之能帶隙可被有利的增加為通道區245中之能帶隙及半導體材料層212A之能帶隙的中間值，致能甚至更高的BV。如上所述，取決於實施例，電晶體100可併入在通道區245內為犧牲的半導體，以選擇性地減少或增加在通道區245中所採用之半導體材料的能帶隙。
圖1C係依據一實施例之第三族氮化物電晶體200的等角圖。第三族氮化物電晶體100具有一外部汲極區235A，其係大致等於源極接觸222A與通道區245之間的間隔(即，由介質間隔物255所決定)，然而第三族氮化物電晶體200具有一外部汲極區235B，其係大於源極接觸222B與通道區245之間的間隔。外部汲極區235A、235B可能被輕微地摻雜且進一步包括半導體層215，如圖1A及1C兩者中所示。在外部汲極區235A、B內，半導體層215作用如同一電荷誘導層，且因為外部汲極區的縱向長度係BV所欲之函數，因此第三族氮化物電晶體200具有比第三族氮化物電晶體100大的BV。
在一範例實施例中，外部汲極區235B為第一及第二半導體材料的合金，以將一介於其間的能帶隙中間值提供 給該第一及第二半導體材料之能帶隙。如圖1C中之空心箭頭所示，在外部汲極區235B內，第一及第二半導體材料的合金為一無序的多層結構之形式。該多層結構包括奈米線210A之第三族氮化物材料，其延伸通過外部汲極區235B，並將通道區245耦合至汲極區230，其之間夾有半導體材料層212A及212B。隨著相鄰半導體材料層212A及212B之奈米線210A的相對側，在外部汲極區235B之部分內可能達到好的合金均勻性。
在一實施例中，第三族氮化物電晶體包括內嵌有源極及/或汲極接觸之奈米線的源極區及/或汲極區。圖1C示出源極接觸222B，其完全地同軸環繞奈米線210A以填滿奈米線210A與基底層205之間的間隙。如圖1A中所示，因為半導體層212A及212B殘留，因此源極接觸222A並未完全地環繞奈米線210A。源極接觸222A、222B可能包括一歐姆金屬層，且可能進一步包括與奈米線210A不同組成之一磊晶生長半導體。例如，源極接觸222A、222B可能包括一穿隧接面(例如，一p+層，其環繞源極區220內之奈米線210A)。可能以此種穿隧接面提供超陡峭的導通及關閉(即，改良的次臨界效能)，用於減少關閉狀態漏電流。
奈米線210A進一步包括一汲極區230。如同源極區，該汲極區可能或多或少內嵌在汲極接觸232內。在圖1C中，汲極接觸232B完全地同軸環繞汲極區230內的奈米線210A，以填滿奈米線210A與基底層205之間的間 隙。如圖1A中所示，因為半導體層212A及212B殘留，因此汲極接觸232A並未完全地環繞奈米線210A。如同源極接觸222A、222B，汲極接觸232A、232B可能包括一歐姆金屬層，並亦可能進一步包括與奈米線210A不同組成之一磊晶生長半導體。
在實施例中，如圖1A及1C中所示，第三族氮化物電晶體包括奈米線之垂直堆疊，以達到基底層之上給定足跡(footprint)之更大的電流承載能力(例如，更大驅動電流)。取決於製造限制，以實質平行於基底層205之頂表面的各個奈米線的縱軸，可能垂直地堆疊任意數量的奈米線。在圖1A或1C中所示之範例實施例中，奈米線210A、210B之各者係具有相同的通道區245內之第一半導體材料。在其他實施例中，奈米線210A及210B之各者係由閘極堆疊250A同軸環繞(例如，如圖1B、2B及2E中進一步所示)。至少閘極介電層240被設置於奈米線210A及210B之間，但在圖1B所示之範例實施例中，閘極導體亦存在於奈米線210A、210B之各者的通道區之間。
在圖1C所示之實施例中，複數個奈米線210B之各者係藉由在外部汲極區235B中的半導體材料而物理地耦合在一起。對於包括複數個奈米線210A、210B的實施例而言，第三族氮化物電晶體100、200具有複數個汲極區，各者用於奈米線之垂直堆疊內的各個奈米線。各個汲極區可能以汲極接觸(例如，232B)同軸包住，該汲極接 觸完全地同軸環繞填充於奈米線210A、210B之間的間隙中的各個汲極區。相同地，源極接觸222B可完全地同軸環繞複數個源極區。
現在提供針對電晶體200及100之各者的製造過程的顯著部份之簡單描述。圖3係依據一實施例之流程圖，描述製造非平面高電壓電晶體200及100之方法300。當方法300強調主要操作時，各操作可能涉及更多的程序流程，且圖3中之操作的編號或該等操作的相對位置並無暗示任何順序。圖4A、4B、4C、4D及4E係依據方法300之實施例所製造的非平面第三族氮化物電晶體100、200的等角圖。
在操作301，使用任何標準化學氣相沈積(CVD)、分子束磊晶(MBE)、氫化物氣相磊晶(HVPE)生長技術等(使用標準前驅物、溫度等)來生長單晶體半導體材料之堆疊。生長至少兩個不同的半導體層作為該磊晶堆疊的部分。在一實施例中，層212A、212B及212C係第一第三族氮化物材料，該等層中設置有第二第三族氮化物。
在操作305，藉由以任何電漿或本技術領域已知之用於生長為磊晶堆疊之部分的特定材料的濕化學蝕刻技術蝕刻磊晶堆疊，來定義奈米線(例如，長度及寬度)。如圖4A中所示，在操作303，蝕刻鰭狀結構410成為奈米線210A、210B與半導體層212A、212B及212C交錯的磊晶堆疊。如所示，奈米線210A及210B之各者均被設置在半導體層212A、212B之上及之下。層厚度T1-T4係取決 於所欲之奈米線維度，且亦取決於在奈米線210A及210B上形成半導體層215之後，在閘極堆疊內回填厚度T1,T3的能力。亦示於圖4A中，例如藉由淺溝渠隔離技術，在基底層205之上的鰭狀結構410之任一側上形成絕緣體層407。
回到圖3，在操作305，形成汲極接觸以部分地(如圖1A中所示)或完全地(如圖1C中所示)環繞奈米線210A及210B。在操作310，相同地形成源極接觸。在操作315，閘極導體係完全地同軸環繞奈米線210A及210B之縱向通道長度。然後在操作320完成該裝置，例如使用傳統的互連技術。
圖4B描述操作305、310及315之一實施例，涉及設置在鰭狀結構410上之犧牲閘極412的形成。在這樣一個實施例中，犧牲閘極412係由一犧牲閘極氧化層及一犧牲多晶閘極層組成，該等層係均厚沉積(blanket deposited)，且以傳統光刻及電漿蝕刻製程來圖案化。可能在犧牲閘極412的側壁上形成間隔物，且可能形成一層間介電層以覆蓋犧牲閘極412。可能拋光層間介電層以暴露犧牲閘極412，用於取代型閘極(replacement gate)或閘極最後(gate-last)製程。參考圖4C，犧牲閘極412已被移除，留下間隔物255及層間介電層(ILD)420、421之部分。如圖4C中進一步所示，在原先由犧牲閘極412所覆蓋之通道區中，移除半導體層212A、212B及212C。然後留下第一半導體材料之分離的奈米線210A及 210B。
如圖4D中所示，接著形成閘極堆疊250A，同軸環繞通道區245內之奈米線210A、210B。圖4D示出半導體層215之磊晶生長後的閘極堆疊、閘極介電質240之沉積、及閘極導體250之沉積以回填藉由選擇性地蝕刻半導體層212A、212B及212C所形成之間隙。即，在將磊晶堆疊蝕刻成分離的第三族氮化物奈米線之後，在層間介電層420、421之間的隧道中形成閘極堆疊。此外，圖4D示出閘極堆疊250A之形成後隨即除去層間介電層420的結果。對於包括外部汲極區235B(例如，第三族氮化物電晶體200)的實施例而言，保留外部汲極區235B內之層間介電層421之部分(例如，以層間介電質之光刻定義屏蔽的蝕刻)。對於替代實施例(例如，對於第三族氮化物電晶體100)而言，不保留ILD 421之部分。
對於包括完全地同軸環繞奈米線210A、210B之源極及汲極接觸的實施例而言，一旦移除ILD層420、421，未被閘極堆疊(及殘留的層間介電層421之任何部分)所保護的半導體層212A及212B的部分接著相對於第一半導體材料之奈米線210A、210B而被選擇性地移除，以形成奈米線210A、210B與基底層205之間的間隙。第一半導體之分離部分然後留在源極及汲極區220及230中，如圖4D中所示。接著，藉由回填在源極及汲極區220、230內形成的間隙，可能形成源極及汲極接觸222A及232A(如圖1A中所示)。在這樣一個實施例中，接觸金屬係 藉由CVD、原子層沉積(ALD)、或金屬回流而被保形地沉積。在替代實施例中，源極及汲極接觸222A、232A係形成在半導體層212A及212B上以及形成在極及汲極區內之奈米線210A及210B的側壁上。接著，在操作320準備完成裝置，例如以傳統的互連金屬化等。
在進一步實施例中，由圖4E所示，ILD 421之任何保留的部份可能被選擇性地移至間隔物255、閘極導體250、及源極、汲極接觸222B、232B。奈米線210A、210B與半導體層212A、212B、212C之其中一者可能接著越過奈米線210A、210B與半導體層212A、212B、212C之其中另一者而被選擇性地移除。在範例實施例中，能帶隙大於奈米線210A、210B之能帶隙的結晶半導體材料係在下部切割的間隙中磊晶再生長。接著，半導體層212A、212B、212C可能作用如同外部汲極區235B內之電荷誘導層。半導體層215可能另外生長於奈米線210A、210B之側壁上(例如，如圖2B中所示之晶體取向)。替代地，或另外地，在ILD 421之殘留部分被移除之後，諸如Al、Ga或Zn的擴散元素可能被併至外部汲極區235B內之第一半導體上。
在實施例中，存在於外部汲極區235B內的半導體材料係藉由熱退火而被合金。例如，第一半導體材料210A、210B與半導體層212A、212B及212C可能被混合(即，無序多層結構)。替代地，熱退火可能以擴散元素(例如，Al、Ga或Zn)來混合半導體材料。在這樣一個 實施例中，熱退火係與源極及汲極接觸之形成同時發生(例如，操作305及310)。尤其，犧牲閘極412之取代可能發生在源極及汲極接觸222、232之形成之後、及/或在外部汲極區235B之退火之後。並且，在外部汲極區235B之熱退火之後可生長半導體層215，以維持在半導體層215與通道區245內之奈米線210A、210B之間的突然異質界面，及/或外部汲極區235B。
圖5係依據本發明之一實施例之行動計算平台之SoC實作的功能方塊圖。行動計算平台700可為任何可攜式裝置，組態用於電子資料顯示、電子資料處理、及無線電子資料傳輸之各者。例如，行動計算平台700可為平板、智慧型手機、膝上型電腦等之任一者，且包括顯示螢幕705、SoC 710、及電池713，該顯示螢幕在範例實施例中為允許接收使用者輸入之觸控螢幕(例如，電容式、電感式、電阻式等)。如所示，SoC 710之集成程度越大，由用於充電之間最長工作壽命的電池713所佔用或由用於最大功能之諸如固態硬碟的記憶體(未圖示)所佔用的行動計算裝置700內之形狀因素越大。
取決於其之應用，行動計算平台700可包括其他組件，包括但不限於揮發性記憶體(例如，DRAM)、非揮發性記憶體(例如，ROM)、快閃記憶體、圖形處理器、數位信號處理器、加密處理器、晶片組、天線、顯示器、觸控螢幕顯示器、觸控螢幕控制器、電池、音訊編解碼器、視訊編解碼器、功率放大器、全球定位系統(GPS) 裝置、指南針、加速度計、陀螺儀、揚聲器、照相機、及大量儲存裝置(諸如硬碟機、光碟(CD)、數位多功能光碟(DVD)等等)。
在展開視圖720中進一步描述SoC 710。取決於該實施例，SoC 710包括矽基板500之部分(即，晶片)，其上製造有電源管理積體電路(PMIC)715、包括RF發射器及/或接收器之RF積體電路(RFIC)725、其之控制器711及一或多個中央處理器核心730、731之兩者或多者。如熟習本技藝之人士將可理解的，在這些功能不同的電路模組中，除了在PMIC 715及RFIC 725中，係典型地專門採用CMOS電晶體，PMIC 715及RFIC 725分別典型地使用LDMOS及III-V HBT技術。然而在本發明之實施例中，PMIC 715及RFIC 725採用本文所述之第三族氮化物電晶體(例如，第三族氮化物電晶體100或200)。在其他實施例中，採用本文所述之第三族氮化物電晶體之PMIC 715及RFIC 725係與控制器711及處理器核心720、730之一或多者集成，以與PMIC 715及/或RFIC 725單片集成至矽基板500上的矽CMOS技術提供。將可理解的是，在PMIC 715及/或RFIC 725內，本文所述之有高電壓、高頻率能力的第三族氮化物電晶體不需要排除CMOS而被使用，而是矽CMOS可進一步被包括在PMIC 715及RFIC 725之各者中。
RFIC 725可實作任何許多無線標準或協議，包括但不限於Wi-Fi(IEEE 802.11家族)、WiMAX(IEEE 802.16家族)、IEEE 802.20、長程演進(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、藍牙、該等之衍生物，以及被指定為3G、4G、5G及之後的任何其他無線協議。 平台725可包括複數個通訊晶片。例如，第一通訊晶片可專用於諸如Wi-Fi及藍牙之更短範圍的無線通訊，而第二通訊晶片可專用諸如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO及其他之更長範圍的無線通訊。
在存在高電壓波動(例如，PMIC 715內之7-10V電池功率調節、DC至DC轉換等)之情形中，可具體使用本文所述之第三族氮化物電晶體。如圖所示，在範例實施例中，PMIC 715具有耦合至電池713之輸入，並具有輸入，提供電流供應給SoC 710中的所有其他功能模組。在其他實施例中，在行動計算平台700內但在SoC 710外設置額外的IC的情況下，PMIC 715輸出進一步提供電流供應給所有這些在SoC 710外的額外IC。如進一步所示，在範例實施例中，RFIC 725具有耦合至天線的一輸出，且可進一步具有一輸入，其耦合至SoC 710上的通訊模組，諸如RF類比及數位基頻模組(未圖示)。替代地，此種通訊模組可被設置在SoC 710之晶片外IC上，且耦合至SoC 710用於傳輸。取決於所使用之第三族氮化物材料，本文所述之第三族氮化物電晶體(例如，200或100)可進一步提供大附加功率效率(PAE)，其為具有至少十倍載波頻率之Ft(例如，設計用於3G或GSM蜂 巢式通訊之RFIC 725中的1.9GHz)的功率放大器電晶體所需要。
應可理解的是，上面說明係示例的而非限制的。例如，雖然圖式中的流程圖顯示由本發明之某些實施例所實施之特別的操作順序，但應可理解的是，此種順序可能非必需的(例如，替代實施例可能以不同順序實施該等操作、結合某些操作、重疊某些操作等)。此外，許多其他實施例將在熟習此技藝之人士閱讀及理解上面說明後變得顯而易見。雖然本發明已參考特定範例實施例來說明，將可理解的是本發明並不限於所述之實施例，而可以在隨附之申請專利範圍之精神及範圍內的修改及變更來實施。因此，本發明之範圍應參考隨附之申請專利範圍，以及此等申請專利範圍所請求之等效的全部範圍。
100‧‧‧第三族氮化物電晶體
200‧‧‧第三族氮化物電晶體
205‧‧‧基底層
210A‧‧‧奈米線
210B‧‧‧奈米線
220‧‧‧源極區
245‧‧‧通道區
230‧‧‧汲極區
235A‧‧‧外部汲極區
235B‧‧‧外部汲極區
215‧‧‧半導體層
215A‧‧‧側壁部分
250‧‧‧閘極堆疊
250A‧‧‧閘極堆疊
240‧‧‧閘極介電層
212A‧‧‧半導體材料層
212B‧‧‧半導體材料層
212C‧‧‧半導體材料層
255‧‧‧間隔物
222A‧‧‧源極接觸
222B‧‧‧源極接觸
232A‧‧‧汲極接觸
232B‧‧‧汲極接觸

Claims (7)

  1. 一種第三族氮化物電晶體，包含：奈米線，設置在一基板上，其中該奈米線之縱向長度進一步包含：第一第三族氮化物材料之通道區，該第一第三族氮化物材料具有纖鋅礦結構的結晶結構；源極區，與該通道區之第一端電性耦合；汲極區，與該通道區之第二端電性耦合；及包含第二第三族氮化物材料的外部汲極區，分開該汲極區及該通道區，閘極堆疊，其完全地同軸環繞該通道區。
  2. 如申請專利範圍第1項之第三族氮化物電晶體，其中該第二第三族氮化物材料具有比該第一第三族氮化物材料之能帶隙更寬的能帶隙。
  3. 如申請專利範圍第1項之第三族氮化物電晶體，其中該外部汲極區為該第一及第二第三族氮化物材料之合金，具有在該第一及第二第三族氮化物材料之能帶隙之間的能帶隙中間值。
  4. 如申請專利範圍第1項之第三族氮化物電晶體，其中該第一第三族氮化物材料基本上由GaN構成、或基本上由InN構成、或基本上由AlxIn1-xN構成，其中x小於1、或基本上由AlxGa1-xN構成，其中x小於1。
  5. 如申請專利範圍第4項之第三族氮化物電晶體，其中該第二第三族氮化物包含AlN、GaN、InN、 AlzIn1-zN、或AlzGa1-zN，其中z不同於x。
  6. 一種系統單晶片(SoC)，包含：一電源管理積體電路(PMIC)，包括切換式電壓調節器或切換式DC-DC(直流-直流)轉換器之至少一者；及一RF積體電路(RFIC)，包括一功率放大器，其可以均至少為20GHz之截止頻率Ft及最大振盪頻率Fmax操作，並產生至少為2GHz之一載波頻率，其中該PMIC及RFIC兩者均係單片集成至一相同基板上，且其中PMIC及RFIC之至少一個包括如申請專利範圍第1項之第三族氮化物電晶體。
  7. 一種行動計算裝置，包含：一觸控螢幕；一電池；一天線；及如申請專利範圍第6項之SoC，其中該PMIC係耦合至該電池，且其中該RFIC係耦合至該天線。
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