JP5944149B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP5944149B2 JP5944149B2 JP2011265692A JP2011265692A JP5944149B2 JP 5944149 B2 JP5944149 B2 JP 5944149B2 JP 2011265692 A JP2011265692 A JP 2011265692A JP 2011265692 A JP2011265692 A JP 2011265692A JP 5944149 B2 JP5944149 B2 JP 5944149B2
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- element isolation
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
- H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
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- H01L29/0642—Isolation within the component, i.e. internal isolation
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Description
<半導体装置>
本発明の一実施の形態である半導体装置を図面を参照して説明する。本実施の形態の半導体装置は、半導体素子としてMISFETを有する半導体装置である。
本実施の形態の半導体装置の製造工程を図面を参照して説明する。図3および図4は、実施の形態1の半導体装置の製造工程の一部を示す製造プロセスフロー図である。図5〜図12および図18〜図22は、実施の形態1の半導体装置の製造工程中の要部断面図である。図13は、実施の形態1の第1変形例の半導体装置の製造工程の一部を示す製造プロセスフロー図である。図14〜図17は、実施の形態1の第1変形例の半導体装置の製造工程中の要部断面図である。なお、図5〜図12および図14〜図17では、素子分離領域近傍を拡大して示す。
図23は、酸化防止膜を形成しない比較例の半導体装置の素子分離領域近傍を拡大して示す要部断面図である。
そこで、本実施の形態では、素子分離領域5に溝7を形成した後、溝7の内部を被覆するように酸化防止膜9を堆積して形成する。また、第1変形例では、溝7の内部を窒化処理して酸化防止膜9を形成する。溝7を形成する際にBOX層3が溝7の側面7bに露出するが、酸化防止膜9を形成することにより、BOX層3のうち溝7の側面7bに露出した部分が酸化防止膜9により被覆される。すなわち、BOX層3と素子分離膜8との間に酸化防止膜9が介在する。これにより、BOX層3が酸化防止膜9により被覆された溝7を埋め込むように素子分離膜8を形成した後、アニール処理を行う際に、素子分離膜8およびBOX層3を通して酸素が拡散することを防止することができ、SOI層4が酸化されることを防止できる。
実施の形態1では、溝7の底面7aおよび側面7bと、素子分離膜8との間には、全面に亘り酸化防止膜9が介在した。それに対して、実施の形態2では、溝7の底面7aおよび側面7bに露出しているSOI層4および支持基板2と、素子分離膜8との間には、酸化防止膜9が介在しない。
図25および図26は、実施の形態2の半導体装置の要部断面図である。図26は、図25のnチャネル型のMISFETQ1近傍領域を拡大して示す図である。
本実施の形態の半導体装置の製造工程を図面を参照して説明する。図27は、実施の形態2の半導体装置の製造工程の一部を示す製造プロセスフロー図である。図28〜図33および図50〜図52は、実施の形態2の半導体装置の製造工程中の要部断面図である。図34は、実施の形態2の第1変形例の半導体装置の製造工程の一部を示す製造プロセスフロー図である。図35〜図41は、実施の形態2の第1変形例の半導体装置の製造工程中の要部断面図である。図42は、実施の形態2の第2変形例の半導体装置の製造工程の一部を示す製造プロセスフロー図である。図43〜図49は、実施の形態2の第2変形例の半導体装置の製造工程中の要部断面図である。なお、図28〜図33、図35〜図41および図43〜図49では、一つの素子分離領域の付近を拡大して示す。
本実施の形態では、素子分離領域5に溝7を形成し、BOX層3のうち溝7の側面7bに露出した部分をエッチングして溝7の側面7bに凹部7cを形成し、凹部7cに露出したBOX層3を被覆するように酸化防止膜9を形成する。また、第1変形例および第2変形例では、溝7の内部を全面に被覆するように堆積した後、BOX層3を被覆する部分が残るようにエッチングすることで酸化防止膜9を形成する。酸化防止膜9を形成することにより、BOX層3が酸化防止膜9により被覆される。すなわち、BOX層3と素子分離膜8との間に酸化防止膜9が介在する。これにより、BOX層3が酸化防止膜9により被覆された溝7を埋め込むように素子分離膜8を形成した後、アニール処理を行う際に、素子分離膜8およびBOX層3を通して酸素が拡散することを防止することができ、SOI層4が酸化されることを防止できる。
実施の形態1、2では、溝7の側面7bに露出したBOX層3と素子分離膜8との間に、酸化防止膜9が介在した。それに対して、実施の形態3では、BOX層3のうち、SOI層4側の部分または支持基板2側の部分が窒化されているSOI基板1を準備し、このようなSOI基板1に溝7を形成し、形成した溝7を埋め込むように素子分離膜8を形成する。
図53および図54は、実施の形態3の半導体装置の要部断面図である。図54は、図53のnチャネル型のMISFETQ1近傍領域を拡大して示す図である。
本実施の形態の半導体装置の製造工程を図面を参照して説明する。図55は、実施の形態3の半導体装置の製造工程の一部を示す製造プロセスフロー図である。図56〜図58、図59(a)および図60〜図68は、実施の形態3の半導体装置の製造工程中の要部断面図である。図59(b)は、窒素濃度の分布を模式的に示すグラフである。なお、図60〜図65では、素子分離領域近傍を拡大して示す。
本実施の形態では、BOX層3のうち、SOI層4側の部分または支持基板2側の部分が窒化されているSOI基板1を準備し、素子分離領域5に溝7を形成する。BOX層3は溝7の側面7bに露出してはいるものの、BOX層3のSOI層4側の部分または支持基板2側の部分が窒化されているため、BOX層3が全く窒化されていない場合に比べ、酸素が拡散しにくくなっている。これにより、溝7を埋め込むように素子分離膜8を形成した後、アニール処理を行う際に、素子分離膜8およびBOX層3を通して酸素が拡散することを防止することができ、SOI層4が酸化されることを防止できる。
2、102 支持基板
3、103 BOX層
4、104 SOI層
5、105 素子分離領域
6A、106A n型MISFET形成領域
6B、106B p型MISFET形成領域
6C 高耐圧MISFET形成領域
7、7d、7f、107 溝(素子分離溝)
7a、7e 底面
7b 側面
7c 凹部
8、8a、8c、108 素子分離膜
8b 上面
9 酸化防止膜
10 層間絶縁膜
11、21〜23、121、122 絶縁膜
31、32 半導体基板
33、35 基体
34、36 絶縁層
101A、101B 端部側領域
101C、101D 中心側領域
CNT コンタクトホール
DW ディープウェル領域
GE ゲート電極
GI ゲート絶縁膜
HW 高耐圧ウェル領域
M1 配線
NW n型ウェル領域
PG プラグ
PR1 フォトレジストパターン
PW p型ウェル領域
Q1〜Q3 MISFET
SD ソース・ドレイン領域
SW サイドウォールスペーサ
Claims (9)
- 基体と、前記基体上の絶縁層と、前記絶縁層上の半導体層とを有する半導体基板と、
前記半導体層に形成された半導体素子と、
素子分離領域において、前記半導体層、前記絶縁層および前記基体に形成された溝部に埋め込まれた素子分離膜と
を有し、
前記絶縁層と前記素子分離膜との間に酸化防止膜が介在し、
前記溝部の側面に露出している前記半導体層、および、前記溝部の底面に露出している前記基体は、前記素子分離膜と直接接していることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記絶縁層と前記素子分離膜は酸化シリコン膜を含むことを特徴とする半導体装置。 - 請求項2記載の半導体装置において、
前記酸化防止膜は窒化シリコン膜を含むことを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記絶縁層は、前記溝部の側面から後退しており、
前記酸化防止膜は、後退した前記絶縁層と前記素子分離膜との間に介在するとともに、上下から前記半導体層と前記基体に挟まれていることを特徴とする半導体装置。 - 請求項4記載の半導体装置において、
前記酸化防止膜は、前記溝部の側面に露出している前記半導体層と前記素子分離膜との間、ならびに、前記溝部の底面および前記溝部の側面に露出している前記基体と前記素子分離膜との間には、介在しない、半導体装置。 - (a)基体と、前記基体上の絶縁層と、前記絶縁層上の半導体層とを有する半導体基板を準備する工程、
(b)素子分離領域において、前記半導体層、前記絶縁層および前記基体をエッチングして溝部を形成する工程、
(c)前記絶縁層のうち、前記溝部の側面に露出した部分をエッチングして前記溝部の側面に凹部を形成する工程、
(d)前記凹部を埋め込むとともに前記溝部の側面を被覆するように酸化防止膜を形成する工程、
(e)形成された前記酸化防止膜のうち、前記凹部を埋め込む部分が残るように、前記酸化防止膜をエッチングする工程、
(f)前記凹部が前記酸化防止膜により埋め込まれた状態で、前記溝部を埋め込むように素子分離膜を形成する工程、
を有することを特徴とする半導体装置の製造方法。 - 請求項6記載の半導体装置の製造方法において、
前記絶縁層と前記素子分離膜は酸化シリコン膜を含むことを特徴とする半導体装置の製造方法。 - 請求項7記載の半導体装置の製造方法において、
前記酸化防止膜は窒化シリコン膜を含むことを特徴とする半導体装置の製造方法。 - 請求項6記載の半導体装置の製造方法において、
(g)形成された前記素子分離膜を研磨する工程、
を有することを特徴とする半導体装置の製造方法。
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TW101139914A TWI557913B (zh) | 2011-12-05 | 2012-10-29 | Semiconductor device and manufacturing method thereof |
US13/691,800 US9343527B2 (en) | 2011-12-05 | 2012-12-02 | Semiconductor device including an isolation film buried in a groove |
CN201210513055.3A CN103137705B (zh) | 2011-12-05 | 2012-12-04 | 半导体装置及其制造方法 |
US15/054,696 US20160181147A1 (en) | 2011-12-05 | 2016-02-26 | Semiconductor device and method of manufacturing the same |
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JP6076224B2 (ja) * | 2013-09-05 | 2017-02-08 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP6340310B2 (ja) * | 2014-12-17 | 2018-06-06 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置およびウェラブル装置 |
US9859422B2 (en) * | 2015-05-28 | 2018-01-02 | Sandisk Technologies Llc | Field effect transistor with elevated active regions and methods of manufacturing the same |
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TWI631662B (zh) * | 2016-02-24 | 2018-08-01 | 格羅方德半導體公司 | 在絕緣體上半導體基板上形成隔離結構之方法 |
JP6594261B2 (ja) * | 2016-05-24 | 2019-10-23 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP6254234B2 (ja) * | 2016-09-07 | 2017-12-27 | ラピスセミコンダクタ株式会社 | 半導体装置 |
JP6629159B2 (ja) * | 2016-09-16 | 2020-01-15 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
KR102639101B1 (ko) * | 2017-02-24 | 2024-02-22 | 에스케이하이닉스 주식회사 | 전자기간섭 차폐 구조를 갖는 반도체 패키지 |
WO2018159126A1 (ja) * | 2017-03-03 | 2018-09-07 | ソニーセミコンダクタソリューションズ株式会社 | 半導体装置および半導体装置の製造方法並びに電子機器 |
US10707330B2 (en) | 2018-02-15 | 2020-07-07 | Globalfoundries Inc. | Semiconductor device with interconnect to source/drain |
JP6947663B2 (ja) * | 2018-03-07 | 2021-10-13 | ルネサスエレクトロニクス株式会社 | 半導体装置及び半導体装置の製造方法 |
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